JP2008117236A - Reference voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit capable of regulating a reference voltage within a prescribed allowable range even when the voltage level of the reference voltage to be generated becomes high. <P>SOLUTION: A mode switching circuit 12 supplies a feeding current of a larger current value as the voltage level of a reference voltage becomes high according to the reference voltage to be generated, a regulation circuit 14 outputs a voltage on a prescribed position in a feeding current supply passage as a reference voltage Vref and regulates the voltage level of the reference voltage Vref output by changing the resistance value of the current supply passage, and a reference current control circuit 16 branches a part of the feeding current supplied into the current supply passage when the voltage level of the reference voltage to be generated is high. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit capable of selectively generating a reference voltage from a plurality of predetermined reference voltages having different voltage levels.

  Conventionally, in a reference voltage generation circuit provided in a semiconductor integrated circuit, the voltage level of the generated reference voltage may vary due to manufacturing variations of the circuit. As a technique for correcting such a variation in the voltage level of the reference voltage, Patent Document 1 discloses an adjustment in which a plurality of energization paths configured to include a fuse element and a resistor are provided in parallel in the reference voltage generation circuit. A circuit (described as “trimming circuit” in Patent Document 1) is built in, and the fuse element of the adjustment circuit is cut in accordance with the variation in the voltage level of the reference voltage generated after the circuit is manufactured to change the resistance value of the energization path. Thus, a technique for adjusting the voltage level of the reference voltage is disclosed.

  By the way, some of this type of reference voltage generation circuit can selectively generate a reference voltage from a plurality of predetermined reference voltages having different voltage levels.

  FIG. 4 shows an example of a conventional reference voltage generation circuit 10 ′ that can selectively generate two types of reference voltages, a predetermined low voltage and a high voltage whose voltage level is higher than the low voltage. Yes.

  The reference voltage generation circuit 10 ′ shown in FIG. 10 is configured to generate either one of two types of reference voltages Vref, a low voltage and a high voltage, by designating a low voltage mode or a high voltage mode by a modelel signal from the outside. This is a circuit that is selectively generated and includes a mode switching circuit 12 ′ and an adjustment circuit 14 ′.

  The mode switching circuit 12 ′ is a circuit that switches the current value of the supply current to be supplied to the adjustment circuit 14 ′ in response to the modelsel signal, and includes a current source I1 ′ and a PMOS transistor PM0 ′ connected to the current source I1 ′. And two PMOS transistors PM1 ′ and PM2 ′ connected to the PMOS transistor PM0 ′ in a mirror configuration, and a PMOS transistor PM3 ′ to which a modelel ′ signal is input to the gate terminal.

  On the other hand, the adjustment circuit 14 ′ is supplied with the supply current supplied from the mode switching circuit 12 ′, outputs the voltage at a predetermined position in the supply path of the supply current as a reference voltage, and changes the resistance value of the supply path. The reference voltage generating resistor R1 ′, four sets of reference voltage generating MOS blocks 18A ′ to 18D ′, and four block selecting PMOSs Transistors PM4 ′ to PM7 ′ are provided. The reference voltage generating MOS block 18A ′ includes a reference voltage generating PMOS transistor PM8 ′ and a reference voltage generating NMOS transistor NM0 ′, and the reference voltage generating MOS block 18B ′ includes a reference voltage generating PMOS transistor. PM9 ′ and a reference voltage generating NMOS transistor NM1 ′ are provided. The reference voltage generation MOS block 18C ′ includes a reference voltage generation PMOS transistor PM10 ′ and a reference voltage generation NMOS transistor NM2 ′. The reference voltage generation MOS block 18D ′ includes a reference voltage generation PMOS transistor 18D ′. A transistor PM11 ′ and a reference voltage generating NMOS transistor NM3 ′ are provided.

  One terminal of the reference voltage generating resistor R1 ′ is connected to a wiring 20 ′ through which a supply current supplied from the mode switching circuit 12 ′ is energized, and an output power line 11 ′ is connected to the one end side. The voltage on one end side is output as the reference voltage Vref via the output power line 11 ′.

  The adjustment circuit 14 'selects a reference voltage generation MOS block used for adjustment of the reference voltage Vref from the four sets of reference voltage generation MOS blocks 18A' to 18D 'by the trimming signals trm0' to trm3 '.

  Next, the operation of the reference voltage generation circuit 10 'will be described. Note that the current value of the current flowing through the PMOS transistor PM1 'of the mode switching circuit 12' is Iref1, and the current value of the current flowing through the PMOS transistor PM2 'is Iref2.

  When the mode switching circuit 12 ′ is in the low voltage mode (here, the modsel signal is at a high level), the PMOS transistor PM3 ′ is turned off, and the current value Iref of the supply current supplied to the adjustment circuit 14 ′ is Iref = Iref1. The trimming signals trm0 ′ to trm3 are assumed when the on resistances of the PMOS transistors PM8 ′ to PM11 ′ when the supply current of the current value Iref1 flows are RP10 to RP13 and the on resistances of the NMOS transistors NM0 ′ to NM3 ′ are RN10 to RN13. The reference voltages Vref10 to Vref13 output via the output power line 11 ′ when the reference voltage generating MOS blocks 18A ′ to 18D ′ are individually selected by “are expressed by the following equations (1) to (4). become that way.

このときのＶｒｅｆ１１−Ｖｒｅｆ１０として求められる電圧レベルの調整幅Ｖｓｔｗ１は、次の（５）式により求めることができる。

The voltage level adjustment width Vstw1 obtained as Vref11-Vref10 at this time can be obtained by the following equation (5).

なお、調整回路１４’には、ＰＭＯＳトランジスタＰＭ８’〜ＰＭ１１’及びＮＭＯＳトランジスタＮＭ０’〜ＮＭ３’として、Ｖｒｅｆ１３−Ｖｒｅｆ１２、及びＶｒｅｆ１２−Ｖｒｅｆ１１がＶｓｔｗ１と等しくなるようなオン抵抗ＲＰ１０〜ＲＰ１３及びオン抵抗ＲＮ１０〜ＲＮ１３のものが適用されている。

The adjustment circuit 14 ′ includes PMOS transistors PM8 ′ to PM11 ′ and NMOS transistors NM0 ′ to NM3 ′, which have on-resistances RP10 to RP13 and an on-resistance RN10 such that Vref13-Vref12 and Vref12-Vref11 are equal to Vstw1. ~ RN13 are applied.

  On the other hand, when the mode switching circuit 12 ′ is in the high voltage mode (here, the modsel signal is at a low level), the PMOS transistor PM3 ′ is turned on, and the current value of the supply current supplied to the adjustment circuit 14 ′. Iref becomes Iref = Iref1 + Iref2. When the on-resistances of the PMOS transistors PM8 ′ to PM11 ′ when the supply current of the current value Iref1 + Iref2 flows are RP20 to RP23 and the on-resistances of the NMOS transistors NM0 ′ to NM3 ′ are RN20 to RN23, the trimming signals trm0 ′ to trm3 When the reference voltage generating MOS blocks 18A 'to 18D' are individually selected by ', reference voltages Vref20 to Vref23 output via the output power line 11' are expressed by the following equations (6) to (10). become that way.

このときのＶｒｅｆ２１−Ｖｒｅｆ２０として求められる電圧レベルの調整幅Ｖｓｔｗ２は、次の（１０）式により求めることができる。

The voltage level adjustment width Vstw2 obtained as Vref21-Vref20 at this time can be obtained by the following equation (10).

なお、調整回路１４’には、ＰＭＯＳトランジスタＰＭ８’〜ＰＭ１１’及びＮＭＯＳトランジスタＮＭ０’〜ＮＭ３’として、Ｖｒｅｆ２３−Ｖｒｅｆ２２、及びＶｒｅｆ２２−Ｖｒｅｆ２１がＶｓｔｗ２と等しくなるようなオン抵抗ＲＰ２０〜ＲＰ２３及びオン抵抗ＲＮ２０〜ＲＮ２３のものが適用されている。

The adjustment circuit 14 ′ includes PMOS transistors PM8 ′ to PM11 ′ and NMOS transistors NM0 ′ to NM3 ′, which have on-resistances RP20 to RP23 and on-resistance RN20 such that Vref23-Vref22 and Vref22-Vref21 are equal to Vstw2. ~ RN23 are applied.

In this way, the reference voltage generation circuit 10 ′ can generate two types of reference voltages Vref, a low voltage and a high voltage, by switching the modsel signal.
JP-A-2005-182113

  However, in the reference voltage generation circuit 10 ′, the current value Iref of the supply current supplied to the adjustment circuit 14 ′ is larger in the high voltage mode than in the low voltage mode. Will become bigger.

  FIG. 3 shows an example of a graph showing the relationship between the current value Iref of the supply current supplied from the mode switching circuit 12 'and the reference voltage Vref output via the output power line 11'. For example, when Iref1 = 50 nA and Iref2 = 150 nA, the supply current is set to the high voltage mode rather than the voltage level adjustment width Vstw1 when the supply current value Iref is set to 50 nA in the low voltage mode. When the current value Iref is 200 nA, the voltage level adjustment width Vstw2 is larger.

  As described above, in the high voltage mode, the adjustment range of the voltage level by the adjustment circuit 14 'is larger than that in the low voltage mode, and the variation in the adjusted reference voltage Vref is also increased. Therefore, the reference voltage Vref is set to a predetermined value. There was a problem that adjustment could not be made within the allowable range.

  Note that the reference voltage generation circuit described in Patent Document 1 cannot selectively generate a plurality of reference voltages having different voltage levels. Further, when the reference voltage generation circuit described in Patent Document 1 is configured to selectively generate a plurality of reference voltages, the above-described problem occurs because the current value of the supply current supplied to the adjustment circuit increases. .

  The present invention has been made to solve the above-described problems, and provides a reference voltage generation circuit capable of adjusting a reference voltage within a predetermined allowable range even when the voltage level of the generated reference voltage becomes high. The purpose is to provide.

  In order to achieve the above object, according to the first aspect of the present invention, a reference voltage generated from a plurality of predetermined reference voltages having different voltage levels can be selectively specified, and the reference voltage can be specified according to the specified reference voltage. The switching means for switching the supply current so as to supply a current having a larger current value as the voltage level of the reference voltage becomes higher, and the supply current is energized, and the voltage at a predetermined position in the energization path of the supply current is the specified reference An adjustment means for adjusting a voltage level of a reference voltage output by changing a resistance value of the energization path, and a supply current branched from the energization path and energized to the energization path Control means for controlling the current value of the current that is supplied to the adjusting means by controlling the current value of the current that is partially energized and energized.

  According to the first aspect of the present invention, the switching means switches the supply current so as to supply a current having a larger current value as the voltage level of the reference voltage increases in accordance with the designated reference voltage, and supplies the current from the switching means. The supplied current is supplied to the adjustment means, and the voltage at a predetermined position in the supply path of the supply current is output as the reference voltage, and the reference is output when the adjustment means changes the resistance value of the supply path. The voltage level of the voltage is adjusted, and the adjusting unit is controlled by controlling the current value of the energized current by the control unit that is energized by a part of the supply current branched from the energizing path and energized in the energizing path. The current value of the current passed through is controlled.

  Thus, according to the first aspect of the present invention, the supply current having a larger current value is supplied as the voltage level of the reference voltage increases in accordance with the designated reference voltage, and the voltage at a predetermined position in the supply current energization path Is output as a reference voltage, and the voltage level of the output reference voltage is adjusted by changing the resistance value of the energization path, and the energization path is energized when the specified reference voltage level is high. By branching a part of the supplied current, it is possible to suppress an increase in the current value of the current supplied to the energization path, so even if the voltage level of the generated reference voltage increases, the reference voltage Can be adjusted within a predetermined tolerance.

  The control means according to the first aspect of the invention provides a current of current that is supplied to the adjustment means when the current value of the supply current is switched by the switching means as in the second aspect of the invention. You may make it control the electric current value of the electric current branched and supplied from the said electricity supply path so that a value may become the same as before the switching by the said switching means.

  According to a first aspect of the present invention, as in the third aspect of the present invention, the control means controls the current value of the current passed through the adjusting means, thereby adjusting the output reference voltage. The level adjustment range may be controlled.

  As described above, according to the present invention, a supply current having a larger current value is supplied as the voltage level of the reference voltage increases in accordance with a designated reference voltage, and a voltage at a predetermined position in the supply current energization path is obtained. The voltage level of the output reference voltage is adjusted by changing the resistance value of the current-carrying path as well as being output as a reference voltage, and the current-carrying path is energized when the specified reference voltage level is high By branching a part of the supply current, it is possible to suppress an increase in the current value of the current passed through the energization path, so even if the voltage level of the generated reference voltage increases, the reference voltage can be reduced. It has an excellent effect that it can be adjusted within a predetermined allowable range.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 shows a configuration of a reference voltage generation circuit 10 according to the present embodiment.

  The reference voltage generation circuit 10 is a circuit that selectively generates one of two kinds of reference voltages Vref, a low voltage and a high voltage, by designating a low voltage mode or a high voltage mode by a model signal from the outside. A mode switching circuit 12, an adjustment circuit 14, and a reference current control circuit 16 are provided.

  The mode switching circuit 12 is a circuit that switches the current value of the supply current supplied to the adjustment circuit 14 according to the model signal, and includes a current source I1 and four PMOS transistors PM0 to PM3.

  The source terminal of the PMOS transistor PM0 is connected to a power supply line (not shown) to which the external power supply voltage VDD is supplied, the gate terminal of the PMOS transistor PM0 is connected to the gate terminal of the PMOS transistor PM1, and the drain terminal of the PMOS transistor PM0 is the current source I1. And is connected to a node nd0 on the wiring connecting the gate terminal of the PMOS transistor PM0 and the gate terminal of the PMOS transistor PM1.

  The PMOS transistor PM1 has a mirror configuration with the PMOS transistor PM0, the source terminal of the PMOS transistor PM1 is connected to a power supply line (not shown) to which the external power supply voltage VDD is supplied, and the drain terminal of the PMOS transistor PM1 is connected to the adjustment circuit 14. It is connected to the connected wiring 20. The PMOS transistor PM2 is also mirrored with the PMOS transistor PM0, the source terminal of the PMOS transistor PM2 is connected to a power supply line (not shown) to which the external power supply voltage VDD is supplied, and the drain terminal of the PMOS transistor PM2 is the PMOS transistor. It is connected to the source terminal of PM3, and the gate terminal of the PMOS transistor PM2 is connected to the node nd0. The drain terminal of the PMOS transistor PM3 is connected to the wiring 20, and the gate terminal of the PMOS transistor PM3 is connected to a signal line 22 to which a model signal is input.

  On the other hand, the adjustment circuit 14 is supplied with the supply current supplied from the mode switching circuit 12, outputs a voltage at a predetermined position in the supply path of the supply current as a reference voltage, and changes the resistance value of the supply path. The reference voltage generating resistor R1, four sets of reference voltage generating MOS blocks 18A to 18D, and four block selecting PMOS transistors PM4 to PM7, It has. The reference voltage generation MOS block 18A includes a reference voltage generation PMOS transistor PM8 and a reference voltage generation NMOS transistor NM0. The reference voltage generation MOS block 18B includes a reference voltage generation PMOS transistor PM9 and a reference voltage generation NMOS transistor NM0. A voltage generating NMOS transistor NM1 is provided. The reference voltage generating MOS block 18C includes a reference voltage generating PMOS transistor PM10 and a reference voltage generating NMOS transistor NM2. The reference voltage generating MOS block 18D includes a reference voltage generating PMOS transistor PM11, A reference voltage generating NMOS transistor NM3 is provided.

  One terminal of the reference voltage generating resistor R <b> 1 is connected to the wiring 20 connected to the mode switching circuit 12, and the output power line 11 is connected to the one end side, and the voltage on one end side passes through the output power line 11. Is output as the reference voltage Vref. The other terminal of the reference voltage generating resistor R1 is connected in parallel with the source terminals of the block selecting PMOS transistors PM4, PM5, PM6, and PM7.

  The gate terminal of the block selecting PMOS transistor PM4 is connected to the signal line 24 to which the trimming signal trm0 is input, and the drain terminal of the block selecting PMOS transistor PM4 is connected to the source terminal of the reference voltage generating PMOS transistor PM8. The drain terminal of the reference voltage generating PMOS transistor PM8 is connected to the drain terminal of the reference voltage generating NMOS transistor NM0, and the gate terminal of the reference voltage generating PMOS transistor PM8 is connected to the gate terminal of the reference voltage generating NMOS transistor NM0. In addition, the drain terminal of the reference voltage generating PMOS transistor PM8 and the drain terminal of the reference voltage generating NMOS transistor NM0 are connected to a node nd4 on the wiring. The source terminal of the reference voltage generating NMOS transistor NM0 is connected to GND.

  The gate terminal of the block selecting PMOS transistor PM5 is connected to the signal line 26 to which the trimming signal trm1 is input, and the drain terminal of the block selecting PMOS transistor PM5 is connected to the source terminal of the reference voltage generating PMOS transistor PM9. The drain terminal of the reference voltage generating PMOS transistor PM9 is connected to the drain terminal of the reference voltage generating NMOS transistor NM1, and the gate terminal of the reference voltage generating PMOS transistor PM9 is connected to the gate terminal of the reference voltage generating NMOS transistor NM1. In addition, the drain terminal of the reference voltage generating PMOS transistor PM9 and the drain terminal of the reference voltage generating NMOS transistor NM1 are connected to a node nd6 on the wiring. The source terminal of the reference voltage generating NMOS transistor NM1 is connected to GND.

  The gate terminal of the block selecting PMOS transistor PM6 is connected to the signal line 28 to which the trimming signal trm2 is input, and the drain terminal of the block selecting PMOS transistor PM6 is connected to the source terminal of the reference voltage generating PMOS transistor PM10. The drain terminal of the reference voltage generating PMOS transistor PM10 is connected to the drain terminal of the reference voltage generating NMOS transistor NM2, and the gate terminal of the reference voltage generating PMOS transistor PM10 is connected to the gate terminal of the reference voltage generating NMOS transistor NM2. In addition, the drain terminal of the reference voltage generating PMOS transistor PM10 and the drain terminal of the reference voltage generating NMOS transistor NM2 are connected to a node nd8 on the wiring. The source terminal of the reference voltage generating NMOS transistor NM2 is connected to GND.

The gate terminal of the block selecting PMOS transistor PM7 is connected to the signal line 30 to which the trimming signal trm3 is input, and the drain terminal of the block selecting PMOS transistor PM7 is connected to the source terminal of the reference voltage generating PMOS transistor PM11.
The drain terminal of the reference voltage generating PMOS transistor PM11 is connected to the drain terminal of the reference voltage generating NMOS transistor NM3, and the gate terminal of the reference voltage generating PMOS transistor PM11 is connected to the gate terminal of the reference voltage generating NMOS transistor NM3. In addition, the drain terminal of the reference voltage generating PMOS transistor PM11 and the drain terminal of the reference voltage generating NMOS transistor NM3 are connected to the node nd10 on the wiring. The source terminal of the reference voltage generating NMOS transistor NM3 is connected to GND.

  On the other hand, the reference current control circuit 16 is energized to the adjustment circuit 14 by controlling a current value of the supplied current that is branched from the adjustment circuit 14 and energized to the adjustment circuit 14. This is a circuit that controls the current value of the generated current, and includes two PMOS transistors PM12 and PM13 and two NMOS transistors NM4 and NM5.

  The source terminal of the PMOS transistor PM12 is connected to a power supply line (not shown) to which the external power supply voltage VDD is supplied, the drain terminal of the PMOS transistor PM12 is connected to the drain terminal of the NMOS transistor NM4, and the gate terminal of the PMOS transistor PM12 is the node nd0. It is connected to the. The source terminal of the NMOS transistor NM4 is connected to GND, the gate terminal of the NMOS transistor NM4 is connected to the gate terminal of the NMOS transistor NM5, and on the wiring where the drain terminal of the PMOS transistor PM12 and the drain terminal of the NMOS transistor NM4 are connected. Node nd11. The source terminal of the NMOS transistor NM5 is connected to GND, and the drain terminal of the NMOS transistor NM5 is connected to the drain terminal of the PMOS transistor PM13. The source terminal of the PMOS transistor PM13 is connected to the node nd2, which is a branch point of the wiring connecting the source terminals of the block selection PMOS transistors PM4 to PM7 in parallel, and the gate terminal of the PMOS transistor PM13 is a signal line to which a modesel signal is input. 22 is connected.

  Next, the operation of the reference voltage generation circuit 10 according to the present embodiment will be described. Note that the current value of the current flowing through the PMOS transistor PM1 of the mode switching circuit 12 is Iref1, the current value of the current flowing through the PMOS transistor PM2 is Iref2, and the current value of the current flowing through the NMOS transistor NM5 of the reference current control circuit 16 is Iref3. And

  When the mode switching circuit 12 is in the low voltage mode (here, the modsel signal is at a high level), the PMOS transistor PM3 is turned off, and the current value Iref of the supply current supplied to the adjustment circuit 14 becomes Iref = Iref1. Further, the PMOS transistor PM13 of the reference current control circuit 16 is turned off. Subsequent operations are the same as those of the conventional reference voltage generation circuit described in the background art, and thus the description thereof is omitted.

  On the other hand, when the mode switching circuit 12 is in the high voltage mode (here, the modsel signal is at low level), the PMOS transistor PM3 is turned on, and the current value Iref of the supply current supplied to the adjustment circuit 14 is Iref = Iref1 + Iref2. Become. Further, the PMOS transistor PM13 of the reference current control circuit 16 is also turned on. At this time, the current value Irefm of the current flowing through the reference voltage generating MOS block via the node nd2 is Irefm = Ire1 + Iref2−Iref3. When the on-resistances of the PMOS transistors PM8 to PM11 when the current Irefm flows are RP30 to RP33 and the on-resistances of the NMOS transistors NM0 to NM3 are RN30 to RN33, the reference voltage generating MOS is generated by the trimming signals trm0 to trm3. When the blocks 18A to 18D are individually selected, the reference voltages Vref30 to Vref33 output via the output power line 11 are expressed by the following equations (10) to (13).

このときのＶｒｅｆ３１−Ｖｒｅｆ３０として求められる電圧レベルの調整幅Ｖｓｔｗ３は、次の（１４）式により求めることができる。

The voltage level adjustment width Vstw3 obtained as Vref31-Vref30 at this time can be obtained by the following equation (14).

なお、調整回路１４には、ＰＭＯＳトランジスタＰＭ８〜ＰＭ１１及びＮＭＯＳトランジスタＮＭ０〜ＮＭ３として、Ｖｒｅｆ３３−Ｖｒｅｆ３２、及びＶｒｅｆ３２−Ｖｒｅｆ３１がＶｓｔｗ３と等しくなるようなオン抵抗ＲＰ３０〜ＲＰ３３及びオン抵抗ＲＮ３０〜ＲＮ３３のものが適用されている。

The adjustment circuit 14 includes PMOS transistors PM8 to PM11 and NMOS transistors NM0 to NM3 that have on-resistances RP30 to RP33 and on-resistances RN30 to RN33 such that Vref33-Vref32 and Vref32-Vref31 are equal to Vstw3. Has been applied.

  Here, the ratio of the gate width to the gate length (W / L ratio) of the PMOS transistor PM2 and the PMOS transistor PM12 in the mirror configuration is made equal, and the ratio of the gate width to the gate length of the NMOS transistor NM4 and the NMOS transistor NM5 is changed. If equal, Iref2 = Iref3.

  As a result, the current value Irefm of the current flowing through the reference voltage generating MOS block becomes Irem = Iref1, and the on-resistances of the reference voltage generating MOS are RP10 to RP13 and RP30 to RP33, and RN10 to RN13 and RN30 to RN33, respectively. Equal between corresponding resistors. Therefore, the reference voltages Vref30 to Vref33 output via the output power line 11 when the reference voltage generating MOS blocks 18A to 18D are individually selected by the trimming signals trm0 to trm3 are the following (15). It becomes like Formula-(18) Formula.

このときのＶｒｅｆ３１−Ｖｒｅｆ３０として求められる電圧レベルの調整幅Ｖｓｔｗ３は、次の（１９）式により求めることができる。

The voltage level adjustment width Vstw3 obtained as Vref31-Vref30 at this time can be obtained by the following equation (19).

この（１９）式及び上記（５）式から、Ｖｓｔｗ１＝Ｖｓｔｗ３となり、高電圧モードと低電圧モードの電圧レベルの調整幅が等しくなる。

From this equation (19) and the above equation (5), Vstw1 = Vstw3, and the adjustment range of the voltage level in the high voltage mode and the low voltage mode is equal.

  That is, in the conventional reference voltage generation circuit, as shown in FIG. 3, for example, when Iref1 = 50 nA and Iref2 = 150 nA, the low voltage mode is set and the current value Iref of the supply current is 50 nA. The voltage level adjustment width Vstw2 when the current value Iref of the supply current is 200 nA in the high voltage mode is larger than the voltage level adjustment width Vstw1.

  On the other hand, in the reference voltage generation circuit 10 according to the present embodiment, since the current Irefm flowing through the reference current generation MOS block is equal in the high voltage mode and the low voltage mode, the voltage level adjustment width Vstw3 in the high voltage mode is low. The adjustment width Vstw1 of the voltage level in the voltage mode becomes equal.

  As described above, according to the present embodiment, by providing the reference current control circuit 16 that controls the current flowing in the reference current generating MOS block, the reference current generating MOS block flows in the high voltage mode and the low voltage mode. Since the current Irefm becomes equal and the voltage level adjustment range of the high voltage mode and the low voltage mode becomes equal, the reference voltage is adjusted within a predetermined allowable range even when the voltage level of the generated reference voltage is increased. Can do.

[Second Embodiment]
Next, an example in which the voltage level adjustment width in the high voltage mode and the low voltage mode is individually controlled will be described.

  FIG. 2 shows the configuration of the reference voltage generation circuit 10 according to the second embodiment. Note that the same components in FIG. 1 as those in FIG. 1 are denoted by the same reference numerals as those in FIG.

  The reference current control circuit 16 according to the second embodiment branches from Iref using the trimming signals tri0 to tri2 in order to adjust the adjustment range of the voltage level of the reference voltage Vref in the high voltage mode. This circuit controls the current value Ireft of the current that flows through the control circuit 16, and includes five PMOS transistors PM12 to PM15 and four NMOS transistors NM4 to NM7.

  The source terminal of the PMOS transistor PM12 is connected to a power supply line (not shown) to which the external power supply voltage VDD is supplied, the drain terminal of the PMOS transistor PM12 is connected to the drain terminal of the NMOS transistor NM4, and the gate terminal of the PMOS transistor PM12 is the node nd0. It is connected to the. The source terminal of the NMOS transistor NM4 is connected to GND, the gate terminal of the NMOS transistor NM4 is connected to the gate terminal of the NMOS transistor NM5, and on the wiring where the drain terminal of the PMOS transistor PM12 and the drain terminal of the NMOS transistor NM4 are connected. Node nd11.

  The source terminal of the PMOS transistor PM13 is connected to the node nd2, and the drain terminal of the PMOS transistor PM13 is connected in parallel to the source terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM15, and the source terminal of the PMOS transistor PM16. The gate terminal of the PMOS transistor PM13 is connected to a signal line 22 to which a model signal is input.

  The drain terminal of the PMOS transistor PM14 is connected to the drain terminal of the NMOS transistor NM5, and the gate terminal of the PMOS transistor PM14 is connected to the signal line 32 to which the trimming signal tri0 is input. The source terminal of the NMOS transistor NM5 is connected to GND.

  The drain terminal of the PMOS transistor PM15 is connected to the drain terminal of the NMOS transistor NM6, and the gate terminal of the PMOS transistor PM15 is connected to the signal line 34 to which the trimming signal tri1 is input. The source terminal of the NMOS transistor NM6 is connected to GND, and the gate terminal of the NMOS transistor NM6 is connected to the node nd11.

  The drain terminal of the PMOS transistor PM16 is connected to the drain terminal of the NMOS transistor NM7, and the gate terminal of the PMOS transistor PM16 is connected to the signal line 36 to which the trimming signal tri2 is input. The source terminal of the NMOS transistor NM7 is connected to GND, and the gate terminal of the NMOS transistor NM7 is connected to the node nd11.

  Next, the operation of the reference voltage generation circuit 10 according to the present embodiment will be described.

  When the mode switching circuit 12 is in the low voltage mode (here, the modsel signal is at a high level), the PMOS transistor PM3 is turned off, and the current value Iref of the supply current supplied to the adjustment circuit 14 becomes Iref = Iref1. Further, the PMOS transistor PM13 of the reference current control circuit 16 is turned off. Subsequent operations are the same as those of the conventional reference voltage generation circuit described in the background art, and thus the description thereof is omitted.

  On the other hand, when the mode switching circuit 12 is in the high voltage mode (here, the modsel signal is at low level), the PMOS transistor PM3 is turned on, and the current value Iref of the supply current supplied to the adjustment circuit 14 is Iref = Iref1 + Iref2. Become. Further, the PMOS transistor PM13 of the reference current control circuit 16 is also turned on. At this time, the current value Irefm of the current flowing through the reference voltage generating MOS block via the node nd2 is Irefm = Iref1 + Iref2-Ireft. This Ireft is a current value controlled by the signals tri0 to tri2. When the on-resistances of the PMOS transistors PM8 to PM11 when the current of the current value Irefm flows are RP40 to RP43 and the on-resistances of the NMOS transistors NM0 to NM3 are RN40 to RN43, the trimming signals trm0 to trm3 are used to generate the reference voltage generation MOS. When the blocks 18A to 18D are individually selected, the reference voltages Vref40 to Vref43 output via the output power line 11 are expressed by the following equations (20) to (23).

このときのＶｒｅｆ４１−Ｖｒｅｆ４０として求められる電圧レベルの調整幅Ｖｓｔｗ４は、次の（２４）式により求めることができる。

The voltage level adjustment width Vstw4 obtained as Vref41-Vref40 at this time can be obtained by the following equation (24).

この（２４）式及び上記（１０）式から、トリミング信号ｔｒｉ０〜ｔｒｉ３を用いてＩｒｅｆｔを調整することによって、高電圧モードの電圧レベルの調整幅を調整することができる。

From this equation (24) and the above equation (10), the adjustment width of the voltage level in the high voltage mode can be adjusted by adjusting Ireft using the trimming signals tri0 to tri3.

  As described above, according to the present embodiment, it is possible to adjust the voltage level adjustment range in the high voltage mode by controlling the amount of current that is supplied by the reference current control circuit 16. .

  In the second embodiment, the case where the adjustment range of the voltage level in the high voltage mode is adjusted by adjusting Ireft using the trimming signals tri0 to tri3 is described, but the present invention is not limited to this. For example, the source terminals of the PMOS transistors PM14 to PM16 may be directly connected to the node nd2 to adjust both the voltage level adjustment widths in the high voltage mode and the low voltage mode.

  In each of the above embodiments, the case where each reference voltage generating MOS block is configured by a PMOS transistor and an NMOS transistor has been described. However, the present invention is not limited to this, for example, only the PMOS transistor or A reference voltage generating MOS block composed of only NMOS transistors can also be used.

  In each of the above embodiments, the circuit that generates two types of reference voltages has been described. However, the present invention can also be applied to a circuit that generates two or more types of reference voltages.

  In addition, the configuration (see FIGS. 1 and 2) of the reference voltage generation circuit 10 described in the above embodiments is merely an example, and can be appropriately changed without departing from the gist of the present invention. Needless to say.

1 is a circuit diagram showing a configuration of a reference voltage generation circuit according to a first embodiment. FIG. It is a circuit diagram which shows the structure of the reference voltage generation circuit which concerns on 2nd Embodiment. It is a graph which shows the relationship of electric current Iref-reference voltage Vref. It is a circuit diagram which shows the structure of the conventional reference voltage generation circuit.

Explanation of symbols

10 reference voltage generation circuit 12 mode switching circuit (switching means)
14 Adjustment circuit (Adjustment means)
16 Reference current control circuit (control means)

Claims (3)

A reference voltage generated from a plurality of predetermined reference voltages having different voltage levels can be selectively specified, and a current having a larger current value is supplied as the voltage level of the reference voltage increases according to the specified reference voltage. Switching means for switching the supply current so as to
The supply current is energized, the voltage at a predetermined position in the energization path of the supply current is output as the specified reference voltage, and the voltage level of the reference voltage output by changing the resistance value of the energization path Adjusting means for adjusting
Control for controlling the current value of the current supplied to the adjusting means by controlling a current value of the supplied current that is branched from the current supply path and supplied to the current supply path. Means,
A reference voltage generating circuit. When the current value of the supply current is switched by the switching unit, the control unit is configured so that the current value of the current supplied to the adjustment unit is the same as that before the switching by the switching unit. The reference voltage generation circuit according to claim 1, wherein the current value of a current that is branched and energized is controlled. The reference voltage generation circuit according to claim 1, wherein the control unit controls an adjustment range of a voltage level for adjusting the output reference voltage by controlling a current value of a current passed through the adjustment unit.

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