CN104952744A - Wafer level package structure manufacturing method - Google Patents
Wafer level package structure manufacturing method Download PDFInfo
- Publication number
- CN104952744A CN104952744A CN201510261020.9A CN201510261020A CN104952744A CN 104952744 A CN104952744 A CN 104952744A CN 201510261020 A CN201510261020 A CN 201510261020A CN 104952744 A CN104952744 A CN 104952744A
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- CN
- China
- Prior art keywords
- gully
- manufacture method
- insulating barrier
- wiring layer
- metal pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The invention relates to a wafer level package structure manufacturing method. The method includes: forming an insulating layer on the upper surface of a semiconductor chip, and arranging an opening portion on the insulating layer to enable an electroconductive metal pad of the semiconductor chip to be exposed; forming a gully on the insulating layer, wherein the gully is communicated with the opening portion; forming a rewiring layer in the opening portion and the gully, wherein the rewiring layer is communicated with the electroconductive metal pad. Compared with the prior art, the rewiring layer is arranged in the gully of the insulating layer, electromigration path formed among rewiring layers (RDL) of a package device is prevented effectively, and abnormality like shorting-out is avoided, so that failing of the device is reduced.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of manufacture method of wafer level packaging structure.
Background technology
Wafer-level packaging product increases just with surprising rapidity, the device of this growth is pulled to be the device such as integrated circuit, high performance storage device, as flash memory/EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM), high speed dram (DRAM), static RAM (SRAM) etc., the increasing product of this type of wafer level packaging starts to adopt the thick metal mode that connects of distribution again, splicing ear and chip surface electrode, have the requirements such as high power, high conductivity, low resistance.Along with wafer-level packaging (WLP) dimensioned area reduces, surface again distribution area increases, the spacing again between distribution must be caused to reduce, the depth-to-width ratio formed along with distribution thickness and spacing distance is again increasing, inevitable easily cause the adjacent short circuit caused because of electron transfer between distribution again etc. abnormal, cause component failure.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides a kind of manufacture method of wafer level packaging structure, comprising: surface forms insulating barrier on a semiconductor die, and insulating barrier has peristome, and the conducting metal pad of semiconductor chip is exposed; Described insulating barrier forms gully, and described gully is communicated with described peristome; In described peristome and described gully, form wiring layer again, described wiring layer is again communicated with described conducting metal pad.
Compare and prior art, being arranged in the gully of insulating barrier by connecting up again, effectively preventing the electro-migration pathways formed between the wiring layer again (RDL) of packaging, avoiding the exceptions such as short circuit, thus reducing the generation of component failure.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the FB(flow block) of wafer level packaging structure manufacture method of the present invention;
Fig. 2-Fig. 8 is the structural representation of each step of corresponding wafer level packaging structure manufacture method of the present invention;
The schematic diagram in the gully that Fig. 9 is formed for wafer level packaging structure manufacture method of the present invention.
Reference numeral: 101-wafer; 103-conducting metal pad; 102-protective layer; 201-insulating barrier; 301-is wiring layer again; 302-copper pillar bump; 401-mounting mat; 402-substrate; 501-protecting glue.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not paying creative work, all belongs to the scope of protection of the invention.
In the following embodiment of the present invention, the sequence number of embodiment and/or sequencing are only convenient to describe, and do not represent the quality of embodiment.The description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.
The present invention relates to a kind of manufacture method of wafer level packaging structure, the method comprises as shown in Figure 1:
Step 10, as shown in Figure 2, surface forms insulating barrier on a semiconductor die, and insulating barrier has peristome, and the conducting metal pad on semiconductor chip is exposed; It is noted that this semiconductor chip includes wafer 101, conducting metal pad 103 and protective layer 102.Conducting metal pad is formed in the upper surface of wafer, and protective layer 102 covers on wafer, and conducting metal pad is exposed, and namely protective layer also has opening, and conducting metal pad is exposed, and certainly, the opening of this protective layer is corresponding with the peristome of insulating barrier.Insulating barrier is formed on the protection layer.
Step 20, forms gully on the insulating layer, and gully is communicated with described peristome (see Fig. 3); Optionally, the bottom in gully is 3-4 μm apart from the distance of described protective layer.That is, the thickness forming the insulating barrier at gully place is 3-4 μm, and the insulating barrier of this thickness can provide stress buffer.(also describe the wafer level packaging structure formed according to the method below, also illustrate that this thickness).See Fig. 9, shown in it is the structural representation using gully manufactured by said method of the present invention, and the part shown in alphabetical A is gully, and Fig. 9 is only signaling function, can not be used for the setting position, quantity, shape etc. that limit actual gully.Optionally, gully is formed by exposure technology, comprises and uses exposure tool to block insulating barrier, then expose described insulating barrier.Exposure tool can by the transparent area organized the different film of color more and form, and the part colours that at least will form described gully in correspondence is different from other part colours.Because the color of film is different, thus through the color of light different, the energy contained by the light of different colours is different, thus different to the exposure effect on insulating barrier, and the energy of the light at corresponding formation gully place is comparatively large, thus forms gully.Certainly, this is optional execution mode, and other modes also can be used for forming above-mentioned gully.
Below when the structure manufactured by the method is described, gully can be illustrated.
Step 30, as shown in Figure 4, in peristome and described gully, form wiring layer again, described wiring layer is again communicated with described conducting metal pad.Optionally, then wiring layer is logical flushes with insulating barrier.
This mode, being arranged in the gully of insulating barrier by connecting up again, effectively preventing the electro-migration pathways formed between the wiring layer again (RDL) of packaging.
Further, manufacture method of the present invention does not also comprise step 40, and described wiring layer again forms copper pillar bump.Optionally, copper pillar bump be formed at by the mode of plating described in again (as shown in Figure 5) on wiring layer.
Step 50, by the mode of copper pillar bump by upside-down mounting, on the mounting mat of upside-down mounting on substrate (as shown in Figure 6).
Step 60; plastic packaging material is filled between substrate and described semiconductor chip; as shown in Figure 7 and Figure 8; two kinds of modes of protecting glue are filled between substrate and wafer; can as the void area of Fig. 7 only between substrate and wafer; also can be as Fig. 8, fill outside void area therebetween, also wrap up wafer surrounding.Certainly, this is only optional execution mode in two, such as, can also be wrapping to bottom etc.
By above-mentioned method, the wafer level packaging structure of manufacture, has semiconductor chip, and this semiconductor chip includes wafer 101, conducting metal pad 103 and protective layer 102.Further; this encapsulating structure is except above-mentioned semiconductor chip; also there is insulating barrier 201 and wiring layer 301 again; conducting metal pad is arranged on wafer; the set-up mode of certain wafer and conducting metal pad is that those skilled in the art can know; protective layer covers the upper surface of wafer; and protective layer has opening; this opening makes conducting metal pad expose; needs are known; this metal gasket exposed can be used to plant ball or arrange ubm layer, also or arrange copper post etc. in follow-up operation, concrete by described below.
Go on to say crystal circle structure; protective layer 102 covers insulating barrier 201; insulating barrier has peristome, and conducting metal pad is exposed, and the opening of this peristome and protective layer matches haply; at the upper surface of this insulating barrier; also there is gully, and gully is communicated with peristome, then wiring layer is just formed in gully; further, conductive metal sheet is communicated with.
Contrary with traditional Wafer-Level Packaging Technology, being arranged in the gully of insulating barrier by connecting up again, effectively preventing the electro-migration pathways formed between the wiring layer again (RDL) of packaging.
In the optional execution mode of one, then wiring layer is formed at described gully, peristome and conducting metal pad surface by electrolysis plating.Plated by electrolysis, the stress of distribution again because electroplating technology produces can be discharged, the short circuit that containment electron transfer causes.
Optionally, wiring layer is more also provided with copper pillar bump 302, and this copper pillar bump can be formed on wiring layer by plating again.Further comprise substrate 402, substrate has mounting mat 401, copper pillar bump upside-down mounting is fixedly installed on described mounting mat.Between substrate and wafer, fill protecting glue 501, optionally, this protecting glue is resin.Fig. 7 and Fig. 8 two kinds of filling modes are had at least as above-mentioned.
In the optional execution mode of one, bottom surface, gully distance protection layer 3-4 μm.Namely the degree of depth that the gross thickness of insulating barrier deducts gully equals 3-4 μm.In other words, the thickness forming the insulating barrier at gully place is 3-4 μm, and the insulating barrier of this thickness can provide stress buffer.Further, then the upper surface flush of the upper surface of wiring layer and described insulating barrier.I.e. wiring layer again, fills up described gully.
Although last it is noted that described the present invention and advantage thereof in detail above, be to be understood that and can carry out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and converting.And scope of the present invention is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (10)
1. a manufacture method for wafer level packaging structure, is characterized in that, comprising:
Surface forms insulating barrier on a semiconductor die, and insulating barrier has peristome, and the conducting metal pad of semiconductor chip is exposed;
Described insulating barrier forms gully, and described gully is communicated with described peristome;
In described peristome and described gully, form wiring layer again, described wiring layer is again communicated with described conducting metal pad.
2. manufacture method according to claim 1, is characterized in that,
The bottom in described gully is 3-4 μm apart from the distance of described protective layer.
3. manufacture method according to claim 1, is characterized in that,
Described gully is formed by exposure technology, comprises and uses exposure tool to block described insulating barrier, then expose described insulating barrier.
4. manufacture method according to claim 3, is characterized in that,
Described exposure tool is by the transparent area organized the different film of color more and form, and the part colours that at least will form described gully in correspondence is different from other part colours.
5. manufacture method according to claim 1, is characterized in that,
The mode that described wiring layer is again plated by electrolytics is formed.
6. manufacture method according to claim 1, is characterized in that,
Described wiring layer is again logical to be flushed with described insulating barrier.
7. the manufacture method according to any one of claim 1-6, is characterized in that,
Again wiring layer forms copper pillar bump described in being also included in.
8. manufacture method according to claim 7, is characterized in that,
Described in described copper pillar bump is formed at by the mode of plating again on wiring layer.
9. manufacture method according to claim 7, is characterized in that,
By the mode of copper pillar bump by upside-down mounting, on the mounting mat of upside-down mounting on substrate.
10. manufacture method according to claim 9, is characterized in that,
Plastic packaging material is filled between described substrate and described semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261020.9A CN104952744A (en) | 2015-05-20 | 2015-05-20 | Wafer level package structure manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261020.9A CN104952744A (en) | 2015-05-20 | 2015-05-20 | Wafer level package structure manufacturing method |
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| Publication Number | Publication Date |
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| CN104952744A true CN104952744A (en) | 2015-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510261020.9A Pending CN104952744A (en) | 2015-05-20 | 2015-05-20 | Wafer level package structure manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582366A (en) * | 2020-12-11 | 2021-03-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333561A (en) * | 2001-06-08 | 2002-01-30 | 财团法人工业技术研究院 | Method for preparing non-electroplating more than two layers of metal convex blocks |
| CN1375871A (en) * | 2001-03-01 | 2002-10-23 | 株式会社东芝 | Semiconductor device and mfg. method for same |
| JP2002313991A (en) * | 2001-04-12 | 2002-10-25 | Nec Saitama Ltd | Semiconductor device and its mounting structure |
| CN103633020A (en) * | 2012-08-21 | 2014-03-12 | 新科金朋有限公司 | Semiconductor device and method of forming rdl using uv-cured conductive ink over wafer level package |
-
2015
- 2015-05-20 CN CN201510261020.9A patent/CN104952744A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375871A (en) * | 2001-03-01 | 2002-10-23 | 株式会社东芝 | Semiconductor device and mfg. method for same |
| JP2002313991A (en) * | 2001-04-12 | 2002-10-25 | Nec Saitama Ltd | Semiconductor device and its mounting structure |
| CN1333561A (en) * | 2001-06-08 | 2002-01-30 | 财团法人工业技术研究院 | Method for preparing non-electroplating more than two layers of metal convex blocks |
| CN103633020A (en) * | 2012-08-21 | 2014-03-12 | 新科金朋有限公司 | Semiconductor device and method of forming rdl using uv-cured conductive ink over wafer level package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582366A (en) * | 2020-12-11 | 2021-03-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging structure and preparation method thereof |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20150930 |