CN104952715B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN104952715B CN104952715B CN201410113739.3A CN201410113739A CN104952715B CN 104952715 B CN104952715 B CN 104952715B CN 201410113739 A CN201410113739 A CN 201410113739A CN 104952715 B CN104952715 B CN 104952715B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000000463 material Substances 0.000 claims abstract description 147
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000012159 carrier gas Substances 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000015654 memory Effects 0.000 abstract description 22
- 239000010410 layer Substances 0.000 description 188
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Semiconductor substrate is provided, the control gate dielectric layer in the Semiconductor substrate formed with some FGS floating gate structuries and positioned at the FGS floating gate structure top surface；First with row graph is formed on the semiconductor substrate and graphically controls gate material layer, and the described first graphical control gate material layer covers the part floating gate dielectric layer on some FGS floating gate structuries；Mask layer is formed on the semiconductor substrate, and the part first that the mask layer is exposed above FGS floating gate structure graphically controls gate material layer and the Semiconductor substrate of gate material layer both sides is graphically controlled positioned at the part first；Using the mask layer as mask, the control gate mutually disconnected is not formed by the first of mask layer covering the graphical control gate material layer described in removal；Remove the mask layer；Side wall is formed in the sidewall surfaces of the FGS floating gate structure, control gate dielectric layer and control gate.Methods described can improve the reliability of flash memory.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Logic, memory and simulation
Circuit, wherein memory device account for sizable ratio in IC products, such as RAM (random access memory), DRAM (dynamics
Random access memory), ROM (read-only storage), EPROM (Erasable Programmable Read Only Memory EPROM), FLASH (flash memory) and
FRAM (ferroelectric memory) etc..The development of flush memory device in memory is particularly rapid.It is mainly characterized by not powered
In the case of can keep the information of storage for a long time, there is high integrated level, faster access speed and be easy to the multiple advantages such as erasing, because
And it is widely used in the multinomial field such as microcomputer, Automated condtrol.
Flash memory structure generally comprises：Floating gate dielectric layer positioned at substrate surface, the floating boom positioned at floating gate dielectric layer surface, position
Control gate dielectric layer, the control gate positioned at the control gate dielectric layer surface in floating gate surface.As integrated circuit integrates
The continuous improvement of degree, the process node of semiconductor also declines therewith, due to being limited by photoetching resolution, single figure chemical industry
Skill can not form the control gate with higher pattern quality.In order to improve the pattern quality of the control gate of formation, it will usually use
Double-patterning method forms the control gate.Specifically, the Double-patterning method includes：In the control gate dielectric layer
Surface is formed after control gate material layer, carries out first graphically to the control gate material layer, it is single to form the multiple storages of covering
The continuous control gate of member；Then second graphical is carried out to the continuous control gate, makes the control between consecutive storage unit
Grid processed disconnect, and form independent control gate.
Flash memories the problems such as short circuit often occurs that prior art is formed, the reliabilities of flash memories need into
The raising of one step.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of forming method of semiconductor structure, the reliable of flush memory device can be improved
Property.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Semiconductor lining is provided
Bottom, the control gate medium in the Semiconductor substrate formed with some FGS floating gate structuries and positioned at the FGS floating gate structure top surface
Layer, the FGS floating gate structure are included positioned at the floating gate dielectric layer of semiconductor substrate surface and positioned at the floating of the floating gate dielectric layer surface
Grid；First with row graph is formed on the semiconductor substrate and graphically controls gate material layer, and described first is graphical
Gate material layer is controlled to cover the part floating gate dielectric layer on some FGS floating gate structuries；Mask layer is formed on the semiconductor substrate,
The part first that the mask layer is exposed above FGS floating gate structure graphically controls gate material layer and positioned at the part
The Semiconductor substrate of one graphical control gate material layer both sides；Using the mask layer as mask, do not covered described in removal by mask layer
The graphical control gate material layer of the first of lid, forms the control gate mutually disconnected；Remove the mask layer；In the floating boom knot
The sidewall surfaces of structure, control gate dielectric layer and control gate form side wall.
Optionally, the first graphical control gate material layer of the exposure is removed using anisotropic etch process.
Optionally, the anisotropic etch process is dry etch process.
Optionally, the dry etch process is more than to control gate to the etch rate of the first graphical control gate material layer
The etch rate of dielectric layer.
Optionally, using plasma etching technics etches the control gate.
Optionally, the etching gas that the plasma etch process uses include Cl2, HBr, carrier gas He, wherein, Cl2
Flow be 80sccm~2000sccm, HBr flow be 50sccm~2000sccm, He flow for 100sccm~
2000sccm。
Optionally, the mask layer also exposes control gate of the part not by the first graphical control gate material layer covering and is situated between
The surface of matter layer.
Optionally, the material of the control gate dielectric layer includes the first silicon oxide layer positioned at floating boom surface, positioned at first
The silicon nitride layer on silicon oxide layer surface, the second silicon oxide layer positioned at silicon nitride layer surface.
Optionally, the forming method of the described first graphical control gate material layer includes：In the semiconductor substrate surface
Form control gate material layer, the control gate material layer covering control gate dielectric layer；Formed in the control gate material surface
First Patterned masking layer；Using first Patterned masking layer as gate material layer is controlled described in mask etching, the first figure is formed
Shapeization controls gate material layer；Remove first Patterned masking layer.
Optionally, the material for controlling gate material layer is polysilicon.
Optionally, it is 1200 angstroms that first positioned at the control gate dielectric layer surface, which graphically controls the thickness of gate material layer,
~1700 angstroms.
Optionally, the material of the floating boom is polysilicon.
Optionally, the thickness of the floating boom is 900 angstroms~1300 angstroms.
Optionally, the material of the floating gate dielectric layer includes silica, silicon oxynitride or hafnium oxide.
Optionally, the material of the side wall includes the one or more in silica, silicon nitride or silicon oxynitride.
Optionally, the forming method of the side wall includes：The table at the top of the semiconductor substrate surface, control gate dielectric layer
Face, control gate top surface, floating gate dielectric layer sidewall surfaces, floating gate side walls surface, control gate dielectric layer sidewall surfaces and control
Grid sidewall surfaces form spacer material layer；Using without mask etching technique, remove positioned at control gate top surface, control gate medium
The spacer material layer of layer top surface and semiconductor substrate surface, form covering floating gate dielectric layer, floating boom, control gate medium
Layer, control gate sidewall surfaces side wall.
Compared with prior art, technical scheme has advantages below：
In technical scheme, formed after FGS floating gate structure, formed on a semiconductor substrate on a semiconductor substrate
The first graphical control gate material layer with row graph, the described first graphical control gate material layer cover some floating boom knots
Part floating gate dielectric layer on structure；Then, mask layer is formed on the semiconductor substrate, and the mask layer is exposed positioned at floating
The part first of grid superstructure graphically controls gate material layer and graphically controls gate material layer two positioned at the part first
The Semiconductor substrate of side；Using the mask layer as mask, not by the first graphical control gate material of mask layer covering described in removal
After the bed of material, then the sidewall surfaces formation side wall in the FGS floating gate structure, control gate dielectric layer and control gate.The mask layer is opened
Mouth is larger, so the mask layer not only exposes part first and graphically controls gate material layer also to expose positioned at the part
The Semiconductor substrate of first graphical control gate material layer both sides, is removing the first uncovered graphical control gate material
During the bed of material, because the described first graphical control gate material layer can be fully exposed in etching gas so that it is described not
The graphical control gate material layer of capped first can be removed completely so that completely disconnected between the control gate ultimately formed
Open, avoid that the problems such as short-circuit occurs between the control gate between different memory cell, can so as to improve the flash memory of formation
By property.
Further, anisotropic dry etch process can be used to remove not graphical by the first of mask layer covering
Control the etching technics used during gate material layer to be more than the etch rate of the first graphical control gate material layer to be situated between to control gate
The etch rate of matter layer, will not Damage Coutrol grid Jie during graphically controlling gate material layer in removal described first
Floating boom below matter layer, and the control gate dielectric layer.
Brief description of the drawings
Fig. 1 to Fig. 4 is that the semiconductor structure of one embodiment of the present of invention forms the structural representation of process；
Fig. 5 to Figure 14 is that the semiconductor structure of an alternative embodiment of the invention forms the structural representation of process.
Embodiment
As described in the background art, the problems such as failing or be short-circuit often occurs in the flash memory that prior art is formed.
The present invention provides the embodiment of the forming process of a semiconductor structure, refer to Fig. 1 to Fig. 4, is the implementation
The structural representation of the semiconductor forming process of example.
Refer to Fig. 1, carried out on floating boom 10 first it is graphical after, the vertical view formed after continuous control gate 20 is shown
It is intended to.In Fig. 1, control gate dielectric layer, Semiconductor substrate etc. is not shown.
The floating gate 10 is arranged in parallel, and the continuous control gate 20 covers some floating booms 10, due to the control gate
20 are belonging respectively to different memory cell, follow-up to need to carry out second graphical to the control gate 20, remove dashed box portion in Fig. 1
The part control gate 21 divided, continuous control gate 20 is disconnected, so as to avoid occurring between the control gate of different memory cell
The problems such as short-circuit.
Fig. 2 is refer to, is diagrammatic cross-sections of the Fig. 1 along secant AA '.
Formed with floating gate dielectric layer 11, floating boom 10, control gate dielectric layer 22, and control gate in the Semiconductor substrate 30
21。
Fig. 3 is refer to, in the floating gate dielectric layer 11, floating boom 10, control gate dielectric layer 22, and the side wall table of control gate 21
Face forms side wall 40.
Generally, while the side wall 40 is the transistor formation side wall in the peripheral circuit of flush memory device, institute is formed
State side wall 40.
Fig. 4 is refer to, second graphical processing is carried out, removes the control gate 21 (refer to Fig. 3).
Mask layer is formed on a semiconductor substrate, other regions beyond control gate 21 is covered, then to the control gate
21 perform etching, and remove the control gate 21.
After forming the side wall 40, side wall 21 protects the side wall of the control gate 21, is etching the control gate
During 21, with the decline of the thickness of control gate 21, groove occurs between side wall 40, due to the width of the control gate 21
Degree is smaller, and the depth-to-width ratio of the groove can gradually increase, and can be less than the quarter of groove top in the etching gas concentration of bottom portion of groove
Gas concentration is lost, so after the control gate 21 to control gate dielectric layer 22 surface is etched, can be in the groove-bottom
The control grid material 21a that residual fraction is not removed at portion's side wall and corner position, the control grid material 21a of the residual can
The control gate 20 (refer to Fig. 1) that can make remains in that continuous state, is subsequently formed after memory, the memory
Short circuit problem will occur between consecutive storage unit, cause out of memory.
In order to solve the above problems, in another embodiment of the present invention, it is proposed that another formation side of semiconductor structure
Method, removing part control gate and then forming side wall.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
It refer to Fig. 5, there is provided Semiconductor substrate 100, FGS floating gate structure is formed in the Semiconductor substrate 100, it is described floating
Grid structure is included positioned at the floating gate dielectric layer 201 on the surface of Semiconductor substrate 100 and positioned at the floating of the surface of floating gate dielectric layer 201
Grid 202.
Forming the forming method of the FGS floating gate structure includes：Floating boom Jie is sequentially formed on the surface of Semiconductor substrate 100
The material bed of material and the floating gate material layer positioned at the floating gate dielectric material surface；Mask is formed in institute's floating gate material layer surface
Layer, the mask layer define size and the position for the FGS floating gate structure being subsequently formed；Using the mask layer as mask, to described floating
Gate material layer, floating gate dielectric material layer perform etching, and form FGS floating gate structure.
The material of the floating gate dielectric layer 201 is the high K dielectric materials such as oxide or hafnium oxide such as silica, silicon oxynitride
Material.
The material of the floating boom 202 is polysilicon.The thickness of the floating boom 202 is 900 angstroms~1300 angstroms.
In the present embodiment, some FGS floating gate structuries arranged in parallel are formed on a semiconductor substrate 100, as the multiple of flash memory
The FGS floating gate structure of memory cell.
Fig. 6 is refer to, control gate dielectric layer 203 is formed on the surface of floating boom 202.
Forming the method for the control gate dielectric layer 203 includes：In the surface of Semiconductor substrate 100, FGS floating gate structure table
Face forms control gate layer of dielectric material；The control gate layer of dielectric material is etched, the control gate positioned at the surface of floating boom 202 is formed and is situated between
Matter layer 203.
In the present embodiment, the control gate layer of dielectric material for ONO stacked structures, including the first silicon oxide layer, be located at
The silicon nitride layer on the first silicon oxide layer surface, the second silicon oxide layer positioned at silicon nitride layer surface.
The control gate dielectric layer is used to isolate the control gate and floating boom 202 being subsequently formed.
Fig. 7 is refer to, it is graphical to form first on the control surface of gate dielectric layer 203 and the surface of Semiconductor substrate 100
Control gate material layer 204.Fig. 7 is the schematic top plan view to be formed after the described first graphical control gate material layer 204.
In order to improve the pattern quality of the control gate ultimately formed, in the present embodiment, formed using Dual graphing technique
The control gate, is specifically included：Formed in Semiconductor substrate 100 and FGS floating gate structure after control gate material layer, to the control
Gate material layer processed carries out the first graphical treatment, forms first and graphically controls gate material layer 204；Graphical to described first
Control gate material layer 204 to carry out second graphical processing, form final control gate.Control gate phase is graphically formed with single
Than forming the control gate using Dual graphing technique, the difficulty of single patterning process can be reduced, improving the control of formation
The pattern quality of grid processed.
Forming the method for the described first graphical control gate material layer 204 includes：In the surface shape of Semiconductor substrate 100
Into control gate material layer, the control gate material layer covering control gate dielectric layer 203；Formed in the control gate material surface
First Patterned masking layer；Using first Patterned masking layer as gate material layer is controlled described in mask etching, the first figure is formed
Shapeization controls gate material layer 204.
The material for controlling gate material layer is polysilicon.
Described first graphical control gate material layer 204 covers the part control gate dielectric layer above multiple FGS floating gate structuries
203.In the present embodiment, the described first graphical figure for control gate material layer 204 be a row graph, and subsequently needs pass through
Second graphical technique, the described first graphical control gate material layer 204 is disconnected, forms independent control gate.Positioned at described
The the first graphical thickness for control gate material layer 204 for controlling the surface of gate dielectric layer 203 is 1200 angstroms~1700 angstroms.
In the present embodiment, the part first in Fig. 7 in dotted line frame graphically controls gate material layer 204a to need to remove
Part, to cause the described first graphical control gate material layer 204 to be disconnected, form independent control gate.The present invention's
In other described examples, the part that the described first graphical control gate material layer 204 is removed can also be other positions, Ke Yigen
According to the requirement for the flush memory device being actually formed, the position of the gap is adjusted.
Fig. 8 is refer to, for the diagrammatic cross-section of the secant BB ' along Fig. 7.
Fig. 9 is refer to, second graphical mask layer 300, institute are formed on the Semiconductor substrate 100 (refer to Fig. 7)
State the part first that second graphical mask layer 300 is exposed on control gate dielectric layer and graphically control gate material layer 204a
And described first graphical control gate material layer 204a both sides part semiconductor substrate 100.Figure 10 is the secant CC ' along Fig. 9
Diagrammatic cross-section.
In the present embodiment, the opening of the second graphical mask layer 300 is larger, exposes the first graphical control gate material
Bed of material 204a and its Semiconductor substrate 100 of both sides, also expose between the adjacent first graphical control gate material layer 204a
The control gate dielectric layer 203 on the surface of floating boom 202.
The material of the second graphical mask layer 300 is the mask materials such as silicon nitride, silica or photoresist.Described
The opening of two Patterned masking layers 300 is larger, can improve the photoetching to be formed during the mask layer 300 or etching technics
Process window, reduce the difficulty for forming the second graphical mask layer 300.
Figure 11 is refer to, with the second graphical mask layer 300 (refer to Fig. 9) for mask, removes first figure
Shapeization control gate material layer 204a (refer to Fig. 9), remaining part first graphically control gate material layer 204 as control
Grid.Figure 12 is refer to, Figure 12 is along secant DD ' diagrammatic cross-section in Figure 11.
Anisotropic dry etch process can be used to remove the described first graphical control gate material layer 204a.Institute
State in anisotropic dry etch process, the first graphical control gate material layer 204a material and control gate dielectric layer 203
Between there is higher Etch selectivity, so as to, will not control gate material layer graphical to described first in etching process
The uncovered control gate dielectric layer 203 in 204a both sides causes to damage.
In the present embodiment, the anisotropic dry etch process is plasma etch process.The plasma
The etching gas that etching technics uses is Cl2, HBr mixed gas, carrier gas He, wherein, Cl2Flow for 80sccm~
2000sccm, HBr flow are 50sccm~2000sccm, and He flow is 100sccm~2000sccm.
Because the opening of the second graphical mask layer 300 is larger so that in etching process, etching gas can fill
Tap touches the described first graphical control gate material layer 204a, so as to completely remove the described first graphical control grid material
Layer 204a, make to be fully disconnected between the remaining first graphical control gate material layer 204 (refer to Fig. 7), with prior art phase
Than that can avoid the problems such as short-circuit occur between memory cell, the performance of the flush memory device of formation can be improved.
It is described partly to lead because the described first graphical material for controlling gate material layer 204a is polysilicon in the present embodiment
The material of body substrate 100 is silicon, moreover, the second graphical mask layer 300 also exposes the described first graphical control gate
The part semiconductor substrate 100 of material layer 204a both sides, so etching the described first graphical control gate material layer 204a's
During, certain etching can be also carried out to the Semiconductor substrate 100, but due to the described first graphical control grid material
There is larger difference in height between layer 204a and Semiconductor substrate 100, so, the described first graphical control gate material layer 204a
The concentration of the etching gas of contact is larger, has higher etch rate, so, remove the first graphical control gate material in etching
It is less to the etching of the Semiconductor substrate 100 of its both sides during bed of material 204a.Also, the described first graphical control gate material layer
The Semiconductor substrate 100 of 204a both sides does not form a part for flash cell, so not having shadow to the performance of flush memory device
Ring.
Figure 13 is refer to, removes the second graphical mask layer 300 (refer to Figure 11).
The second graphical mask layer 300 is removed using wet-etching technology, according to the second graphical mask layer
300 material selects suitable etching solution, can be the one or more in hydrofluoric acid, phosphoric acid or salpeter solution.When described
When the material of second graphical mask layer 300 is photoresist, cineration technics can also be used to remove the second graphical mask
Layer 300.
After removing the second graphical mask layer 300, the control gate 204b, the control gate 204b that expose disconnection are
Remove the part first and graphically control remaining first graphical control gate material after gate material layer 204a (refer to Fig. 9)
The bed of material.Mutually disconnected between the control gate 204b, respectively as the control gate of different memory cell.
Figure 14 is refer to, (is asked in the floating gate dielectric layer 201, floating boom 202, control gate dielectric layer 203, control gate 204b
With reference to figure 12) sidewall surfaces formation side wall 400.Figure 14 is floating gate dielectric layer 201, floating boom 202, control gate medium in fig. 12
The schematic diagram that 203 sidewall surfaces of layer are formed after side wall 400.
The material of the side wall 400 is the one or more in silica, silicon nitride or silicon oxynitride.The side wall 400
Forming method includes：The table at the top of the surface of Semiconductor substrate 100, control gate dielectric layer 203 top surface, control gate 204b
Face, the sidewall surfaces of floating gate dielectric layer 201, the sidewall surfaces of floating boom 202, the control sidewall surfaces of gate dielectric layer 203 and control gate 204b
Sidewall surfaces form spacer material layer；Using without mask etching technique, remove and be situated between positioned at control gate 204b top surfaces, control gate
The top surface of matter layer 203 and the spacer material layer on the surface of Semiconductor substrate 100, form covering floating gate dielectric layer 201, floating boom
202nd, control gate dielectric layer 203, control gate 204b sidewall surfaces side wall 400.
In the present embodiment, after the first graphical control gate material layer 204 is formed, first to the described first graphical control
Gate material layer 204 carries out second graphical processing, removes part first and graphically controls gate material layer 204a, formation is fully disconnected
Control gate 204b, then re-form side wall 400.And gate material layer is graphically controlled in etching first if being initially formed side wall,
Due to be initially formed side wall, it is necessary to remove part first graphically control gate material layer both sides to be protected by side wall, carving
Only surface can touch etching gas during erosion, and as the continuation of etching process, meeting form groove between side wall,
Because the width of the described first graphical control gate material layer is typically small, the depth-to-width ratio of the groove is larger, bottom portion of groove
Etching gas concentration is smaller, so, it is easy to control grid material in bottom portion of groove residual fraction so that the control gate ultimately formed
Between can not be fully disconnected and influence the performance of flush memory device.The present embodiment carries out second graphical before side wall 400 is formed
Processing, during removing part first and graphically controlling gate material layer 204a, the graphical control gate material in part first
Bed of material 204a both sides do not have the protection of side wall, fully can be contacted with etching gas, so that the part first is graphical
Control gate material layer 204a can be removed completely so that it is fully disconnected between the control gate of the different units ultimately formed, can
To improve the reliability of the flash memory formed.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (16)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Semiconductor substrate is provided, formed with some FGS floating gate structuries and positioned at table at the top of the FGS floating gate structure in the Semiconductor substrate The control gate dielectric layer in face, the FGS floating gate structure are included positioned at the floating gate dielectric layer of semiconductor substrate surface and positioned at the floating boom The floating boom of dielectric layer surface；First with row graph is formed on the semiconductor substrate and graphically controls gate material layer, and described first is graphical Gate material layer is controlled to cover the part floating gate dielectric layer on some FGS floating gate structuries；Mask layer is formed on the semiconductor substrate, and the mask layer exposes the figure of part first above FGS floating gate structure Shapeization controls gate material layer and the Semiconductor substrate of gate material layer both sides is graphically controlled positioned at the part first；Using the mask layer as mask, the graphical control gate material layer of first not covered by the mask layer is removed, forms phase The control gate mutually disconnected；Remove the mask layer；Side wall is formed in the sidewall surfaces of the FGS floating gate structure, control gate dielectric layer and control gate.
- 2. the forming method of semiconductor structure according to claim 1, it is characterised in that using anisotropic etch process Remove the first graphical control gate material layer of the exposure.
- 3. the forming method of semiconductor structure according to claim 2, it is characterised in that the anisotropic etch process For dry etch process.
- 4. the forming method of semiconductor structure according to claim 3, it is characterised in that the dry etch process is to The etch rate of one graphical control gate material layer is more than the etch rate to controlling gate dielectric layer.
- 5. the forming method of semiconductor structure according to claim 4, it is characterised in that using plasma etching technics Etch the described first graphical control gate material layer.
- 6. the forming method of semiconductor structure according to claim 5, it is characterised in that the plasma etch process The etching gas of use include Cl2, HBr, carrier gas He, wherein, Cl2Flow for 80sccm~2000sccm, HBr flow For 50sccm~2000sccm, He flow is 100sccm~2000sccm.
- 7. the forming method of semiconductor structure according to claim 1, it is characterised in that the mask layer also exposes portion Divide not by the surface of the control gate dielectric layer of the first graphical control gate material layer covering.
- 8. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of the control gate dielectric layer Material includes the first silicon oxide layer positioned at floating boom surface, the silicon nitride layer positioned at the first silicon oxide layer surface, positioned at silicon nitride layer Second silicon oxide layer on surface.
- 9. the forming method of semiconductor structure according to claim 1, it is characterised in that the first graphical control gate The forming method of material layer includes：Control gate material layer is formed in the semiconductor substrate surface, the control gate material layer is covered Lid control gate dielectric layer；The first Patterned masking layer is formed in the control gate material surface；Graphically covered with described first Film layer is that gate material layer is controlled described in mask etching, forms first and graphically controls gate material layer；It is graphical to remove described first Mask layer.
- 10. the forming method of semiconductor structure according to claim 9, it is characterised in that the control gate material layer Material is polysilicon.
- 11. the forming method of semiconductor structure according to claim 9, it is characterised in that positioned at the control gate medium It is 1200 angstroms~1700 angstroms that the first of layer surface, which graphically controls the thickness of gate material layer,.
- 12. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of the floating boom is more Crystal silicon.
- 13. the forming method of semiconductor structure according to claim 1, it is characterised in that the thickness of the floating boom is 900 Angstrom~1300 angstroms.
- 14. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of the floating gate dielectric layer Material includes silica, silicon oxynitride or hafnium oxide.
- 15. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of the side wall includes One or more in silica, silicon nitride or silicon oxynitride.
- 16. the forming method of semiconductor structure according to claim 1, it is characterised in that the forming method of the side wall Including：In the semiconductor substrate surface, control gate dielectric layer top surface, control gate top surface, floating gate dielectric layer side wall Surface, floating gate side walls surface, control gate dielectric layer sidewall surfaces and control gate sidewall surfaces form spacer material layer；Covered using nothing Film etching technics, remove positioned at the side of control gate top surface, control gate dielectric layer top surface and semiconductor substrate surface The walling bed of material, formed covering floating gate dielectric layer, floating boom, control gate dielectric layer, control gate sidewall surfaces side wall.
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| CN103400753A (en) * | 2013-08-14 | 2013-11-20 | 上海华力微电子有限公司 | Method for manufacturing grid lines with high uniformity through double exposure |
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| KR100515374B1 (en) * | 2003-01-30 | 2005-09-14 | 동부아남반도체 주식회사 | Flash memory and fabrication method thereof |
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| CN1607669A (en) * | 2003-08-07 | 2005-04-20 | 三星电子株式会社 | Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same |
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| CN102760654A (en) * | 2011-04-29 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming grid pattern |
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