CN104935344A - Multi-bit comparator with combination of time and digital converter and voltage digitizing method - Google Patents
Multi-bit comparator with combination of time and digital converter and voltage digitizing method Download PDFInfo
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Abstract
The present invention relates to a multi-bit comparator with the combination of a time and digital converter and a voltage digitizing method. The multi-bit comparator comprises a one-bit comparator, a time and digital converter, an inverter, and an XOR gate. The input end of the one-bit comparator is connected to the positive and negative ends of an input signal and a clock signal. The input end of the XOR gate is connected to the output end of the one-bit comparator. The input end of the time and digital converter is connected to the output end of the XOR gate and the clock signal which is processed by the inverter. According to the multi-bit comparator, by using the relation that the judgment time of the comparator in low voltage is increased with the reduction of input voltage, a judgment time is converted into a corresponding digital code through TDC conversion, thus the digitization of low power consumption and high precision small signal voltage is realized, and the multi-bit comparator and the method have the advantages of low power consumption, adaption to low-voltage design, small size and fast speed.
Description
Technical field
The invention belongs to analog integrated circuit and digital integrated circuit field, relate to a kind of comparator, be specifically related to a kind of multidigit comparator of binding time digital quantizer, and utilize this multidigit comparator to realize the method for voltage multilevel quantization.
Background technology
Along with the development of digital processing technology, increasing information system have employed digital signal processor to complete each generic operation.And most of outer signals is continuous print analog signal, at this time just needs analog to digital converter (A/D Converter) as the interface of simulated world and digital world, continuous print analog signal is converted to discrete digital signal and corresponding code.
Comparator (Comparator) is the essential elements bearing quantification in analog to digital converter, and also comparator generally can be regarded as the analog to digital converter of 1 by extensive application in a lot of fields.The performance of comparator is to the overall system performance important of analog to digital converter.CMOS technology and supply voltage is ceaselessly reduced to the pursuit of low-power consumption, this is that the design of comparator brings new challenge.
Field-effect transistor (MOS) although threshold voltage decrease along with reducing of process, reduce in proportion as process.Under relatively low supply voltage and relatively high threshold voltage, the input stage of comparator is operated near subthreshold region, and mutual conductance reduces, and causes the speed of service degradation of comparator.The method of traditional raising comparator speed increases electric current, or add preset amplifying stage.Conventional renewable bistable state comparator circuit is the framework that speed and precision are all very high.But this comparator also exists metastable issues, especially when the voltage difference of input signal is less, comparator is in the metastable time and greatly extends.For the analog to digital converter of a 8bit, under 1V supply voltage, corresponding minimum input signal is 4mV, and the comparator decision time is now at 100 picoseconds; But under 0.5V supply voltage, about the comparator decision time now will extend to for 100 nanoseconds.This is one of difficult point of the design of Low-voltage Low-power analog to digital converter.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of multidigit comparator of binding time digital quantizer, and utilize this multidigit comparator to realize the method for voltage multilevel quantization, utilize comparator at lower voltages time decision with input voltage reduce and increase relation, digital code corresponding to time decision convert to through TDC, thus realize the digitlization of low-power consumption, high-precision small signal.
The technical solution used in the present invention is as follows:
A multidigit comparator for binding time digital quantizer, comprises 1 bit comparator, time-to-digit converter, inverter, XOR gate, and the input of described 1 bit comparator connects positive and negative terminal and the clock signal of input signal; The input of described XOR gate connects the output of described 1 bit comparator; The input of described time-to-digit converter connects the output of described XOR gate and the clock signal after described inverter process.
Further, described 1 bit comparator has positive negative output, the dynamic comparer under clock control, gets final product regrowth dynamics comparator, as the renewable dynamic comparer of bistable state etc.
Further, described time-to-digit converter comprises some controllable delay unit and corresponding trigger, the output of described XOR gate is connected with the input of described controllable delay unit, the signal of the controllable delay unit of described trigger incoming clock signal and correspondence.
Further, described trigger is d type flip flop, also can replace with JK flip-flop or other triggers.
The present invention also provides a kind of method realizing comparator multilevel quantization, and utilize above-mentioned multidigit comparator, by quantifying the time decision of comparator, utilize the relation between this time decision and input voltage, realize the multilevel quantization of input voltage, its concrete steps comprise:
1) half period before a clock cycle, when clock is low level, two of 1 bit comparator export as high level, and the now output of XOR gate is low level;
2) after jumping in clock signal, voltage difference due to two input pipe grids of 1 bit comparator causes the gap of both sides electric current, positive feedback latch structure is started working afterwards, and output signal starts gradually toward one high and one low change, and XOR gate becomes high level after a certain time;
3) defining the upper time of jumping between edge of clock being jumped edge and XOR gate output is the time decision of comparator, can determine the size of input signal according to the length of time decision, and the quantification of elapsed time digital conversion unit can obtain corresponding coding.
Compared with prior art, beneficial effect of the present invention is as follows:
1) high accuracy.The voltage quantization precision of tradition comparator is difficult to reach 1mV, and the present invention utilizes the high accuracy characteristic of time quantization, easily can realize the quantification of 0.5mV precision.
2) low-power consumption.Renewable comparator of the present invention does not have quiescent dissipation, and remaining power consumption is mainly from the trigger in time-to-digit converter and XOR gate, and these digital circuit quiescent dissipations are almost nil.
3) low voltage designs is adapted to.Voltage is lower, and the change of time decision that input voltage causes is more obvious, and this also means that this voltage arrives digital conversion again to the time can be more accurate.
4) the little speed of area is fast.The design of common employing time-to-digit converter is first through voltage time transducer, then entry time digital quantizer, and two step operations, not only need to consume extra chip area, and need two or more clock cycle complete operation.The present invention can complete quantization operation within a clock cycle.
Accompanying drawing explanation
Fig. 1 is the comparator configuration figure in the present invention.
Fig. 2 is the output signal schematic diagram of comparator.
Fig. 3 is the time-to-digit converter in the present invention.
Fig. 4 is the overall structure figure of the multidigit comparator of binding time digital quantizer in the present invention.
Fig. 5 is the overall structure figure of the multidigit comparator comprising encoder in the present invention.
Fig. 6 is the overall structure figure of the multidigit comparator after increase by two inverters and latch.
Embodiment
Below by specific embodiment, and coordinate accompanying drawing, the present invention is described in detail.
Fig. 1 is classical renewable dynamic comparer structure chart.As shown in Figure 1, when clock is low level, circuit is in reproduced state, M7, M8 conducting, exports VOP(output head anode), VON(negative pole of output end) be essentially pulled up to high level VDD(supply voltage).When clock becomes high level, circuit enters comparison phase, M9 conducting, and the mutual conductance amplifying stage be made up of M5, M6 is opened, VOP and VON node voltage declines.VIP(input anode) and VIN(input cathode) between the voltage difference that exists cause the difference between current of both sides branch road, therefore VOP with VON voltage drop speed is different.When VOP and VON drops to VDD-V
thptime (supply voltage deducts threshold voltage), M2, M4 open, and latch is started working, and voltage difference small between VOP and VON is not stopped to widen due to positive feedback, and final one rises to VDD, and one drops to low level, now compares end.
The time dependent curve of VOP and VON as shown in Figure 2.In figure, t
0for the time required for M2 unlatching, i.e. the time of first stage, t
latchfor opening from M2, drop to 0.5V to output
dDrequired time, V
0be two inconsistent output node voltage differences caused of branch current, V
thpfor the threshold voltage of PMOS, Δ V
outfor output voltage swing, V
dDfor supply voltage.T in figure
compbe exactly time decision, in this moment, with VOP and VON for the output of the XOR gate of input can become high level.Through the analytical calculation to circuit, can show that time decision and input stage voltage difference exist following relation:
Wherein, C
lrefer to the load capacitance of output, g
mrefer to the mutual conductance of latch, g
minrefer to the mutual conductance of input stage M5, M6, Δ V
outrefer to output voltage swing, Δ V
init is then input stage voltage difference.In conjunction with suitable value, under certain resolution, between time decision and input stage voltage difference, near-linear relation can be realized.This time is quantized by time-to-digit converter, in conjunction with the Output rusults of comparator itself, just can realize the multilevel quantization to small voltage within a clock cycle.
The structure of time-to-digit converter as shown in Figure 3, is made up of controllable delay unit and d type flip flop.The rising edge of XOR gate, after delay cell, is jumped near edge under being positioned at global clock.Due to the clock of d type flip flop and global clock anti-phase, jump under global clock along time, d type flip flop latches, and its result corresponds to the length of time decision, thus the time that realizes is to digital conversion.D type flip flop can be replaced with JK flip-flop or other triggers.The realization of time-to-digit converter has a variety of mode, and the time-to-digit converter structure of other kind also can be applied in this invention.
Fig. 4 is the structure chart of the multidigit comparator of binding time digital quantizer.As shown in Figure 4, the multidigit comparator of binding time digital quantizer comprises 1 bit comparator, time-to-digit converter, inverter, XOR gate.The output of comparator generally only has high and low two kinds, is most basic analog-digital converter, the namely analog-digital converter of 1.1 bit comparator also can directly be called " comparator ".1 bit comparator accesses positive and negative terminal and the clock signal of input signal respectively; XOR gate accesses the output of 1 bit comparator; Time-to-digit converter accesses the output of XOR gate and the clock signal after inverter process respectively.
Utilize above-mentioned multidigit comparator, by quantifying the time decision of comparator, utilize the relation between this time decision and input voltage, realize the multilevel quantization of input voltage, its concrete steps comprise:
1) half period before a clock cycle, when clock is low level, two of 1 bit comparator export as high level, and the now output of XOR gate is low level;
2) after jumping in clock signal, voltage difference due to two input pipe grids of 1 bit comparator causes the gap of both sides electric current, positive feedback latch structure is started working afterwards, and output signal starts gradually toward one high and one low change, and XOR gate becomes high level after a certain time;
3) defining the upper time of jumping between edge of clock being jumped edge and XOR gate output is the time decision of comparator, can determine the size of input signal according to the length of time decision, and the quantification of elapsed time digital conversion unit can obtain corresponding coding.
Wherein, comparator signal outputs to XOR gate, is unidirectional output.A voltage signal can obtain two quantized result, but finally can merge into final output.For convenience of realizing, a new module also can be added in Fig. 4, encoder, the output of connect hours digital quantizer and comparator, namely as shown in Figure 5.In Fig. 5, D [3:0] and [2:0] are encoding examples.D [3:0], although be 4, can become 2 corresponding codings through correct coding.0000 corresponds to 00,0001 corresponds to 01,0011 corresponding to 10,0111 corresponding to 11.Merge with COMP again after coding, finally obtain effective 3 Output rusults.COMP is as highest order.
As shown in Figure 6, on the comparator of multidigit shown in Fig. 5 basis, the output of 1 bit comparator can increase by two inverters and latch, can ensure the stable of output so further.
Above embodiment is only in order to illustrate technical scheme of the present invention but not to be limited; those of ordinary skill in the art can modify to technical scheme of the present invention or equivalent replacement; and not departing from the spirit and scope of the present invention, protection scope of the present invention should be as the criterion with described in claim.
Claims (9)
1. a multidigit comparator for binding time digital quantizer, is characterized in that, comprises 1 bit comparator, time-to-digit converter, inverter, XOR gate, and the input of described 1 bit comparator connects positive and negative terminal and the clock signal of input signal; The input of described XOR gate connects the output of described 1 bit comparator; The input of described time-to-digit converter connects the output of described XOR gate and the clock signal after described inverter process.
2. multidigit comparator as claimed in claim 1, it is characterized in that, described 1 bit comparator is the renewable dynamic comparer of bistable state.
3. multidigit comparator as claimed in claim 1, it is characterized in that, described time-to-digit converter comprises some controllable delay unit and corresponding trigger, the output of described XOR gate is connected with the input of described controllable delay unit, the controllable delay signal of described trigger incoming clock signal and correspondence.
4. multidigit comparator as claimed in claim 3, it is characterized in that, described trigger is d type flip flop or JK flip-flop.
5. the multidigit comparator according to any one of Claims 1-4, is characterized in that, also comprise encoder, the output of connect hours digital quantizer and the output of comparator.
6. multidigit comparator as claimed in claim 5, it is characterized in that, the output of described 1 bit comparator is provided with inverter and latch, in order to ensure the stable of output.
7. one kind adopts multidigit comparator described in claim 1 to realize the method for voltage digital, it is characterized in that: utilize described multidigit comparator, the time decision of comparator by quantifying, utilizes the relation between this time decision and input voltage, realizes the multilevel quantization of input voltage.
8. method as claimed in claim 7, is characterized in that, comprise the steps:
1) half period before a clock cycle, when clock is low level, two of 1 bit comparator export as high level, and the now output of XOR gate is low level;
2) after jumping in clock signal, voltage difference due to two input pipe grids of 1 bit comparator causes the gap of both sides electric current, positive feedback latch structure is started working afterwards, and output signal starts gradually toward one high and one low change, and XOR gate becomes high level after a certain time;
3) defining the upper time of jumping between edge of clock being jumped edge and XOR gate output is the time decision of comparator, and according to the size of the length determination input signal of time decision, the quantification of elapsed time digital conversion unit can obtain corresponding coding.
9. method as claimed in claim 7 or 8, it is characterized in that, the pass of described time decision and input stage voltage difference is:
Wherein, T
comptime decision, C
lthe load capacitance of output, g
mthe mutual conductance of latch, g
mininput stage mutual conductance, Δ V
outoutput voltage swing, Δ V
init is input stage voltage difference.
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| WO2017197581A1 (en) * | 2016-05-17 | 2017-11-23 | 华为技术有限公司 | Time-to-digital converter and digital phase-locked loop |
| CN111313871A (en) * | 2019-11-29 | 2020-06-19 | 湖南国科微电子股份有限公司 | Dynamic pre-amplifying circuit and dynamic comparator |
| CN114690611A (en) * | 2022-04-14 | 2022-07-01 | 东南大学 | Time-to-digital converter with low power consumption and conversion method |
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Cited By (10)
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| CN105162441A (en) * | 2015-09-25 | 2015-12-16 | 中国电子科技集团公司第二十四研究所 | High-speed low-power-consumption dynamic comparator |
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| US10693481B2 (en) | 2016-05-17 | 2020-06-23 | Huawei Technologies Co., Ltd. | Time-to-digital converter and digital phase locked loop |
| CN111313871A (en) * | 2019-11-29 | 2020-06-19 | 湖南国科微电子股份有限公司 | Dynamic pre-amplifying circuit and dynamic comparator |
| CN111313871B (en) * | 2019-11-29 | 2024-03-26 | 湖南国科微电子股份有限公司 | Dynamic pre-amplification circuit and dynamic comparator |
| CN114690611A (en) * | 2022-04-14 | 2022-07-01 | 东南大学 | Time-to-digital converter with low power consumption and conversion method |
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Application publication date: 20150923 |