CN104934376B - A method of making semiconductor devices - Google Patents

A method of making semiconductor devices Download PDF

Info

Publication number
CN104934376B
CN104934376B CN201410100745.5A CN201410100745A CN104934376B CN 104934376 B CN104934376 B CN 104934376B CN 201410100745 A CN201410100745 A CN 201410100745A CN 104934376 B CN104934376 B CN 104934376B
Authority
CN
China
Prior art keywords
region
high
dummy gate
threshold voltage
groove
Prior art date
Application number
CN201410100745.5A
Other languages
Chinese (zh)
Other versions
CN104934376A (en
Inventor
库尔班·阿吾提
Original Assignee
中芯国际集成电路制造(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中芯国际集成电路制造(上海)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to CN201410100745.5A priority Critical patent/CN104934376B/en
Publication of CN104934376A publication Critical patent/CN104934376A/en
Application granted granted Critical
Publication of CN104934376B publication Critical patent/CN104934376B/en

Links

Abstract

The invention discloses a kind of methods for making semiconductor devices, production method according to the present invention changes the physical thickness of boundary layer (IL) using oxygen clean-up effect, the method achieve the dielectric layers that the different zones in semiconductor substrate form different-thickness, the dielectric layer includes high k dielectric layer and IL dielectric layer, the requirement for adjusting different voltages device is met simultaneously, the overall performance for improving semiconductor devices, improves the yields of semiconductor.Production method of the invention is suitable for plane field effect transistor semiconductor technology and FinFET(FinFET) semiconductor technology.

Description

A method of making semiconductor devices

Technical field

The present invention relates to semiconductor fabrication process more particularly to a kind of use modulation voltage and adjust multivoltage device.

Background technique

Main devices in integrated circuit (IC) especially super large-scale integration are metal oxide semiconductcor field effects Transistor (MOS) is answered, with the maturation of semiconductor integrated circuit industrial technology increasingly, the rapid hair of ultra-large integrated circuit Exhibition, with higher performance and the bigger component density of more powerful integrated circuit requirement, and between all parts, element or Size, size and the space of each element itself are also required to further reduce.For the CMOS with more advanced technology node For, high K/ metal gates (high-k and metal gate) technology has been widely used in cmos device, high K/ gold Belong to grid and replaces polysilicon gate and traditional gate dielectric layer, gate dielectric layer such as silica or silicon oxynitride, to keep away Exempt from damage of the high-temperature processing technology to device.

In order to preferably control under the short-channel effect (SCE) and drain induced barrier of high K/ metal gate semiconductor device Drop (DIBL), the MOSFET semiconductor devices of plane be changed as FinFET(FinFET) semiconductor devices, This method mainly changes the planform of semiconductor devices.

Can there are many variations, example in actual semiconductor device fabrication process and the debugging process of semiconductor devices Such as, the production of voltage adjustment (VT modulation) and multivoltage (Multi-VT) device.In the prior art, using voltage Injection material is doped in semiconductor substrate the voltage for adjusting semiconductor devices by injection technology, then executes subsequent high K/ The production of metal gates can also adjust the voltage of semiconductor devices using the technique for adjusting work function.

In order to further increase the performance of K/ metal gate semiconductor device, advanced voltage adjusting process and mostly electricity are needed The adjusting technique of voltage device.

Summary of the invention

A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.

In order to solve the problems in the existing technology, the invention proposes a kind of method for making semiconductor devices, packets It includes: the semiconductor substrate with standard threshold voltage region, high threshold region and low threshold region, the mark is provided Quasi- threshold voltage regions include the first dummy gate, and the low threshold region includes the second dummy gate, the high threshold Voltage regime includes third dummy gate;First dummy gate in the standard threshold voltage region is removed, institute is removed Second dummy gate in low threshold region is stated, the virtual grid of the third in the high threshold region are removed Pole forms second groove in the low threshold region to form first groove in the standard threshold voltage region, Third groove is formed in the high threshold region;In the first groove, the second groove and the third groove Bottom and side wall on be sequentially depositing to form high k dielectric layer and coating;Remove in the high threshold region described covers Cap rock is to expose the high k dielectric layer;Oxygen scavenger injection is executed to the low threshold region;Execute annealing steps.

The invention also provides the methods of another production semiconductor devices, comprising: providing has standard threshold voltage area Domain, high threshold region and low threshold region semiconductor substrate, the standard threshold voltage region includes first empty Quasi- grid, the low threshold region include the second dummy gate, and the high threshold region includes third dummy gate; First dummy gate in the standard threshold voltage region is removed, described in the low threshold region is removed Two dummy gates remove the third dummy gate in the high threshold region, in the standard threshold voltage area First groove is formed in domain, forms second groove in the low threshold region, the shape in the high threshold region At third groove;Shape is sequentially depositing on the first groove, the bottom of the second groove and the third groove and side wall At high k dielectric layer and coating;Respectively to the standard threshold voltage region, the high threshold region and the Low threshold Voltage regime executes oxygen scavenger injection;Execute annealing steps.

Preferably, the material of the oxygen scavenger is Ti, Al or Hf.

Preferably, interfacial TCO layer is formed between the semiconductor substrate and the high k dielectric layer.

Preferably, the reaction temperature of the annealing steps is 600 to 800 DEG C, and the reaction time of the annealing steps is 30 To 60s, the reaction pressure of the annealing steps is 1 to 20atm, is executed under conditions of being passed through the mixed gas of oxygen and nitrogen The annealing steps.

Preferably, when using identical oxygen scavenger material, the doping injection of the low threshold region is greater than institute The implantation concentration in standard threshold voltage region is stated, the implantation concentration in the standard threshold voltage region is greater than the high threshold voltage The implantation concentration in region.

Preferably, when the implantation concentration of oxygen scavenger is identical, oxygen scavenger in the low threshold region it is clear Removing solid capacity is greater than the Scavenging activity of the oxygen scavenger in the standard threshold voltage region, in the standard threshold voltage region The Scavenging activity of oxygen scavenger is greater than the Scavenging activity of the oxygen scavenger in the high threshold region.

It preferably, further include removing the remaining coating after the annealing steps to expose the high k dielectric Layer.

It preferably, further include being formed newly on the high k dielectric layer of exposing after removing the remaining coating Coating.

In conclusion the physics that production method according to the present invention changes boundary layer (IL) using oxygen clean-up effect is thick Degree, the method achieve the dielectric layer that the different zones in semiconductor substrate form different-thickness, the dielectric layer includes that high K is situated between Electric layer and IL dielectric layer, while the requirement for adjusting different voltages device is met, the overall performance of semiconductor devices is improved, is improved The yields of semiconductor.Production method of the invention is suitable for plane field effect transistor semiconductor technology and FinFET(fin Field effect transistor) semiconductor technology.

Detailed description of the invention

Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings,

Figure 1A -1D is that the semiconductor devices of MG structure after having rear HK/ according to one embodiment of the present invention production is related The schematic diagram of the section structure of step device obtained;

Fig. 2 is the technique stream of the semiconductor devices of MG structure after having rear HK/ according to one embodiment of the present invention production Cheng Tu;

Fig. 3 A-3E is the semiconductor devices phase for having MG structure after rear HK/ according to another embodiment of the present invention production Close the schematic diagram of the section structure of step device obtained;

Fig. 4 is the technique of the semiconductor devices of MG structure after having rear HK/ according to another embodiment of the present invention production Flow chart.

Specific embodiment

In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So And it will be apparent to one skilled in the art that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into Row description.

In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate method of the invention. Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor field is familiar with.Preferable reality of the invention Example is applied to be described in detail as follows, however other than these detailed descriptions, the present invention can also have other embodiments.

It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more Other a features, entirety, step, operation, element, component and/or their combination.

Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.

In the present invention by it is appropriate it is material doped arrive high k dielectric layer, boundary layer and coating (scavenger layer, Scavenging layer) between can generate oxygen clean-up effect (Oxygen scavenging effect), for example, zirconium (Zr) It is doped to hafnium oxide (HfO2) in will generate the lesser crystal boundary of high k dielectric layer (grain boundary), this can make oxygen (Oxygen) atom is easily diffused into wherein.In this case, pass through scavenger layer easily in annealing process Oxygen atom in semiconductor devices is disposed.

It is described in detail below in conjunction with preparation method of Figure 1A -1D to semiconductor devices of the present invention.Such as Figure 1A It is shown, semiconductor substrate 100 is provided, semiconductor substrate 100 may include any semiconductor material, this semiconductor material may include but It is not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP and other III-V or II-VI compounds of group half Conductor.It is also optionally, semiconductor substrate 100 may include epitaxial layer.Semiconductor substrate 100 can also include organic semiconductor Or such as SiGe(SGOI on Si/SiGe, silicon-on-insulator (SOI) or insulator) layered semiconductor.

Semiconductor substrate 100 includes various isolation structures 101, these isolated parts may include different structure, and by Different processing technique is formed.Such as isolated part may include shallow trench isolation component (STI).Semiconductor substrate 100 is also Including trap.

Semiconductor substrate 100 includes the NMOS standard threshold voltage region (NSVT) and the area PMOS standard threshold voltage (PSVT) Domain, the NMOS low threshold voltage region (NLVT) and the region PMOS low threshold voltage (PLVT), the area NMOS high threshold voltage (NHVT) Domain and the region PMOS high threshold voltage (PHVT).NMOS area has the dummy gate knot being formed on the channel region of Uniform Doped Structure, the dummy gate structure include grid oxic horizon and dummy gate and gate oxide level and dummy gate two sides shape At grid gap wall, PMOS area has the dummy gate structure that is formed on the channel region of Uniform Doped, the virtual grid Pole structure includes grid oxic horizon and dummy gate and gate oxide level and the gate pitch that dummy gate two sides are formed Wall, the material of dummy gate can be polysilicon or be silicon nitride or agraphitic carbon, wherein the material of dummy gate is preferred Undoped polysilicon, grid gap wall can be for a kind of in silica, silicon nitride, silicon oxynitride or they combine composition. As an optimal enforcement mode of the present embodiment, the clearance wall is silica, silicon nitride collectively constitutes.Semiconductor substrate 100 further include the source-drain area positioned at NMOS dummy gate and PMOS dummy gate two sides.

Interlayer dielectric layer 102 is formed above semiconductor substrate 100 and dummy gate.Implement chemical mechanical grinding (CMP) Technique removes extra interlayer dielectric layer, so that exposing the dummy gate layer of dummy gate.It can also be using other mode shapes Expose the dummy gate layer of dummy gate at interlayer dielectric layer.

Implement etching technics to remove dummy gate in NMOS area and PMOS area and grid oxic horizon reservation and be located at The grid gap wall of dummy gate and grid oxic horizon two sides, to form metal gates ditch in NMOS area and PMOS area Slot.Etching technics may include the combination of dry etching, wet etching or dry etching and wet etching.Removing virtual grid After surface of the pole to expose semiconductor substrate, for example diluted hydrofluoric acid or other suitable techniques can also be used to remove grid Pole oxide layer forms metal gates groove to be completely exposed the surface of semiconductor substrate.

On interlayer dielectric layer 102, in grid gap wall, in the bottom of metal gates groove and level deposition form interface Layer (IL) and high K(HK) dielectric layer 103.IL layers can for thermal oxide layer, nitrogen oxide layer, chemical oxide layer or other Suitable film layer.Boundary layer can be formed using CVD, ALD or PVD etc. suitable technique.The thickness range of boundary layer is 5 Angstrom to 10 angstroms.The material of high-k dielectrics can choose for but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(BST), Al2O3、Si3N4, nitrogen oxides or Other suitable materials.High k dielectric layer can be formed using CVD, ALD or PVD etc. suitable technique.The thickness of high k dielectric layer Spending range is 10 angstroms to 30 angstroms.

Coating 104 is formed on high k dielectric layer 103, the material of coating 104 can be La2O3、AL2O3、Ga2O3、 In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable film layers.CVD, ALD can be used Or the technique formation coating that PVD etc. is suitable.The thickness range of coating is 5 angstroms to 20 angstroms.It is embodied in the present invention one In example, coating 104 is scavenger layer, and scavenger layer helps to remove the oxygen atom in semiconductor devices.

As shown in Figure 1B, the coating in NMOS high threshold region and PMOS high threshold region is removed to expose High k dielectric layer.

Mask layer 105 is formed on coating 104, the hard mask layer is but is not limited to patterned photoresist layer, institute It states mask layer 105 and covers low threshold region and standard threshold voltage region exposing NMOS high threshold region and PMOS high Threshold voltage regions remove the covering in NMOS high threshold region and PMOS high threshold region according to mask layer 105 Layer exposes high k dielectric layer.The high k dielectric layer can be removed using dry etching, dry method etch technology includes but is not limited to: reaction Ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably by one or more RIE step Carry out dry etching.Alternatively, can remove the high k dielectric layer using wet etching, wet etch method can use hydrofluoric acid solution, Such as buffer oxide etch agent or hydrofluoric acid buffer solution.

The mask layer 105 is removed, for example, the patterned photoresist layer 105 is removed using cineration technics, to expose Coating in low threshold region and standard threshold voltage region.

As shown in Figure 1 C, doping injection technology is executed to NMOS low threshold region and PMOS low threshold region, Specifically, oxygen scavenger is injected into NMOS low threshold region and PMOS low threshold region, the oxygen scavenger Material can be suitable for Ti, Al or Hf etc. material, wherein neither executes doping to standard threshold voltage region and injects work Skill does not execute the removal of coating yet.The dosage and energy of the oxygen scavenger injection can choose model commonly used in the art It encloses, details are not described herein.

In a specific embodiment of the invention, mask layer 106 is formed on a semiconductor substrate 100, the hard mask layer can Think that patterned photoresist layer, mask layer 106 expose NMOS low threshold region and the covering of PMOS low threshold region High threshold region and standard threshold voltage region, using mask layer 106 as exposure mask to NMOS low threshold region and PMOS low threshold region executes the doping injection of oxygen scavenger.

As shown in figure iD, annealing steps are executed after oxygen scavenger injection doping, helps to create oxygen and removes effect It answers, the annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain temperature It is heat-treated, is preferably nitrogen in high-purity gas of the present invention, while being passed through a certain amount of oxygen in reaction chamber, Middle oxygen accounts for the 1% to 3% of nitrogen amount, and the temperature of the annealing steps is 600-800 DEG C, and the annealing steps time is 30-60, The reaction pressure of the annealing steps is 1 to 20atm.

It should be noted that the technological parameter of above-mentioned exit step is only exemplary, limitation is not joined with above-mentioned technique Number, those skilled in the art can also select process conditions appropriate according to practical integrated artistic and device performance.

As a further preference, rapid thermal annealing can be selected in the present invention, specifically, can be selected following several One of mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser are fast Fast annealing and non-coherent broad band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.Those skilled in the art can be with It is selected as needed, is also not limited to examples cited.

After the annealing steps, thicker, Low threshold that the thickness of the boundary layer in high threshold region device becomes The thickness for the boundary layers relatively thin, in standard threshold voltage region devices that the thickness of boundary layer in voltage regime device becomes is not Become.It can be by adjusting the process conditions of annealing steps and doping injection step to realize required device architecture.

After executing annealing steps, removes remaining coating 104 and expose high k dielectric layer 103, on high k dielectric layer Form new coating.

Then barrier layer, workfunction layers and electrode layer are formed on new coating, it is subsequent to form metal gates Specifically processing step is well known for those skilled in the art, is not just described in detail herein.

Referring to Fig. 2, for according to work of one embodiment of the present invention production with the semiconductor devices of MG structure after rear HK/ Skill flow chart, for schematically illustrating the process of entire manufacturing process.

In step 201, semi-conductive substrate is provided, semiconductor substrate includes NMOS standard threshold voltage region and PMOS Standard threshold voltage region, NMOS low threshold region and PMOS low threshold region, NMOS high threshold region and PMOS high threshold region is formed with interlayer dielectric layer (ILD0) on a semiconductor substrate, the dummy gate in NMOS area Dummy gate structure in structure and PMOS area.Remove the virtual grid in the dummy gate structure and PMOS area in NMOS area Pole structure, to form metal gates groove;

In step 202, be sequentially depositing in the metal gates groove in NMOS area and PMOS area to be formed boundary layer, High k dielectric layer, coating;

In step 203, the coating in PMOS high threshold region and NMOS high threshold region is removed;

In step 204, oxygen scavenger injection is executed to PMOS low threshold region and NMOS low threshold region;

In step 205, annealing steps are executed.

Fig. 3 A-3E is the semiconductor devices phase for having MG structure after rear HK/ according to another embodiment of the present invention production Close the schematic diagram of the section structure of step device obtained;Below in conjunction with Fig. 3 A-3E to semiconductor devices of the present invention Preparation method is described in detail.As shown in Figure 3A, semiconductor substrate 300 is provided, semiconductor substrate 300 may include any partly leading Body material, this semiconductor material may include but be not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and Other III-V or group Ⅱ-Ⅵ compound semiconductor.It is also optionally, semiconductor substrate 300 may include epitaxial layer.Semiconductor Substrate 300 can also include SiGe on organic semiconductor or such as Si/SiGe, silicon-on-insulator (SOI) or insulator (SGOI) layered semiconductor.

Semiconductor substrate 300 includes various isolation structures 301, these isolated parts may include different structure, and by Different processing technique is formed.Such as isolated part may include shallow trench isolation component (STI).Semiconductor substrate 100 is also Including trap.

Semiconductor substrate 300 includes the NMOS standard threshold voltage region (NSVT) and the area PMOS standard threshold voltage (PSVT) Domain, the NMOS low threshold voltage region (NLVT) and the region PMOS low threshold voltage (PLVT), the area NMOS high threshold voltage (NHVT) Domain and the region PMOS high threshold voltage (PHVT).NMOS area has the dummy gate knot being formed on the channel region of Uniform Doped Structure, the dummy gate structure include grid oxic horizon and dummy gate and gate oxide level and dummy gate two sides shape At grid gap wall, PMOS area has the dummy gate structure that is formed on the channel region of Uniform Doped, the virtual grid Pole structure includes grid oxic horizon and dummy gate and gate oxide level and the gate pitch that dummy gate two sides are formed Wall, the material of dummy gate can be polysilicon or be silicon nitride or agraphitic carbon, wherein the material of dummy gate is preferred Undoped polysilicon, grid gap wall can be for a kind of in silica, silicon nitride, silicon oxynitride or they combine composition. As an optimal enforcement mode of the present embodiment, the clearance wall is silica, silicon nitride collectively constitutes.Semiconductor substrate 300 further include the source-drain area positioned at NMOS dummy gate and PMOS dummy gate two sides.

Interlayer dielectric layer 302 is formed above semiconductor substrate 300 and dummy gate.Implement chemical mechanical grinding (CMP) Technique removes extra interlayer dielectric layer, so that exposing the dummy gate layer of dummy gate.It can also be using other mode shapes Expose the dummy gate layer of dummy gate at interlayer dielectric layer.

Implement etching technics to remove dummy gate in NMOS area and PMOS area and grid oxic horizon reservation and be located at The grid gap wall of dummy gate and grid oxic horizon two sides, to form metal gates ditch in NMOS area and PMOS area Slot.Etching technics may include the combination of dry etching, wet etching or dry etching and wet etching.Removing virtual grid After surface of the pole to expose semiconductor substrate, for example diluted hydrofluoric acid or other suitable techniques can also be used to remove grid Pole oxide layer forms metal gates groove to be completely exposed the surface of semiconductor substrate.

On interlayer dielectric layer 302, in grid gap wall, in the bottom of metal gates groove and level deposition form interface Layer (IL) 302 and high K(HK) dielectric layer 303.IL layers can for thermal oxide layer, nitrogen oxide layer, chemical oxide layer or Other suitable film layers.Boundary layer can be formed using CVD, ALD or PVD etc. suitable technique.The thickness model of boundary layer Enclose is 5 angstroms to 10 angstroms.The material of high-k dielectrics can choose for but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(BST), Al2O3、Si3N4, nitrogen oxidation Object or other suitable materials.High k dielectric layer can be formed using CVD, ALD or PVD etc. suitable technique.High k dielectric The thickness range of layer is 10 angstroms to 30 angstroms.

Coating 304 is formed on high k dielectric layer 303, the material of coating 304 can be La2O3、AL2O3、Ga2O3、 In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable film layers.CVD, ALD can be used Or the technique formation coating that PVD etc. is suitable.The thickness range of coating is 5 angstroms to 20 angstroms.It is embodied in the present invention one In example, coating 104 is scavenger layer, and scavenger layer helps to remove the oxygen atom in semiconductor devices.

As shown in Figure 3B, doping injection work is executed to NMOS standard threshold voltage region and PMOS standard threshold voltage region Oxygen scavenger is specifically injected into NMOS standard threshold voltage region and PMOS standard threshold voltage region, the oxygen by skill The material that the material of scavenger can be suitble to for Ti, Al or Hf etc..

Illustratively, the different zones shape in semiconductor substrate is realized by adjusting the condition of the oxygen scavenger injection At the dielectric layer of different-thickness, the condition of oxygen scavenger injection includes dosage, material and the energy of the oxygen scavenger injection.

In a specific embodiment of the invention, mask layer 105 is formed on a semiconductor substrate 100, the hard mask layer can Think that patterned photoresist layer, mask layer 105 expose NMOS standard threshold voltage region and PMOS standard threshold voltage region High threshold region and low threshold region are covered, using mask layer 105 as exposure mask to NMOS standard threshold voltage region The doping injection of oxygen scavenger is executed with PMOS standard threshold voltage region.

As shown in Figure 3 C, doping injection technology is executed to NMOS low threshold region and PMOS low threshold region, Specifically, oxygen scavenger is injected into NMOS low threshold region and PMOS low threshold region, the oxygen scavenger Material can be suitable for Ti, Al or Hf etc. material.

Illustratively, the different zones shape in semiconductor substrate is realized by adjusting the condition of the oxygen scavenger injection At the dielectric layer of different-thickness, the condition of oxygen scavenger injection includes dosage, material and the energy of the oxygen scavenger injection.

In a specific embodiment of the invention, mask layer 106 is formed on a semiconductor substrate 100, the hard mask layer can Think that patterned photoresist layer, mask layer 106 expose NMOS low threshold region and the covering of PMOS low threshold region High threshold region and standard threshold voltage region, using mask layer 106 as exposure mask to NMOS low threshold region and PMOS low threshold region executes the doping injection of oxygen scavenger.

As shown in Figure 3D, doping injection technology is executed to NMOS high threshold region and PMOS high threshold region, Specifically, oxygen scavenger is injected into NMOS high threshold region and PMOS high threshold region, the oxygen scavenger Material can be suitable for Ti, Al or Hf etc. material.

Illustratively, the different zones shape in semiconductor substrate is realized by adjusting the condition of the oxygen scavenger injection At the dielectric layer of different-thickness, the condition of oxygen scavenger injection includes dosage, material and the energy of the oxygen scavenger injection.

In a specific embodiment of the invention, mask layer 107 is formed on a semiconductor substrate 100, the hard mask layer can Think that patterned photoresist layer, mask layer 107 expose NMOS high threshold region and the covering of PMOS high threshold region Low threshold region and standard threshold voltage region, using mask layer 107 as exposure mask to NMOS high threshold region and PMOS high threshold region executes the doping injection of oxygen scavenger.

As shown in FIGURE 3 E, annealing steps are executed after executing above-mentioned oxygen scavenger injection doping, it is clear helps to create oxygen Except effect, the annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain Temperature is heat-treated, and is preferably nitrogen in high-purity gas of the present invention, while a certain amount of oxygen is passed through in reaction chamber Gas, wherein oxygen accounts for the 1% to 3% of nitrogen amount, and the temperature of the annealing steps is 600-800 DEG C, and the annealing steps time is 30-60, the reaction pressure of the annealing steps are 1 to 20atm.

It should be noted that the technological parameter of above-mentioned exit step is only exemplary, limitation is not joined with above-mentioned technique Number, those skilled in the art can also select process conditions appropriate according to practical integrated artistic and device performance.

As a further preference, rapid thermal annealing can be selected in the present invention, specifically, can be selected following several One of mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser are fast Fast annealing and non-coherent broad band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.Those skilled in the art can be with It is selected as needed, is also not limited to examples cited.

After executing the annealing steps, the thickness of the boundary layer in above-mentioned semiconductor device is thinning, but high threshold The thickness change of voltage regime device, standard threshold voltage region devices and the boundary layer in low threshold region device is different Sample is finally less than the thickness of standard threshold voltage region devices median surface layer in the thickness of high threshold region device median surface layer The thickness of degree, standard threshold voltage region devices median surface layer is less than the thickness of high threshold region device median surface layer.

It realizes by adjusting annealing process condition and oxygen scavenger injection technology condition in the not same district of semiconductor substrate The dielectric layer of domain formation different-thickness.

Illustratively, when high threshold region device, standard threshold voltage region devices and low threshold region device The material for the oxygen scavenger that part is injected separately into is identical, then high threshold region device, standard threshold voltage region devices and The implantation concentration of low threshold region is different, low threshold region, standard threshold voltage region, high threshold region Implantation concentration gradually decreases, and is equivalent to, and the oxygen scavenger implantation concentration of low threshold region is greater than standard threshold voltage region Oxygen scavenger implantation concentration, the oxygen that the oxygen scavenger implantation concentration in standard threshold voltage region is greater than high threshold region is clear Except agent implantation concentration.

Illustratively, when high threshold region device, standard threshold voltage region devices and low threshold region device When the implantation concentration for the oxygen scavenger that part is injected separately into is identical, the Scavenging activity of the oxygen scavenger of low threshold region injection is big In the clear of the oxygen scavenger that the Scavenging activity for the oxygen scavenger that standard threshold voltage region is injected, standard threshold voltage region inject Removing solid capacity is greater than the Scavenging activity of the oxygen scavenger of high threshold region injection.

Referring to Fig. 4, for according to work of one embodiment of the present invention production with the semiconductor devices of MG structure after rear HK/ Skill flow chart, for schematically illustrating the process of entire manufacturing process.

In step 401, semi-conductive substrate is provided, semiconductor substrate includes NMOS standard threshold voltage region and PMOS Standard threshold voltage region, NMOS low threshold region and PMOS low threshold region, NMOS high threshold region and PMOS high threshold region is formed with interlayer dielectric layer (ILD0) on a semiconductor substrate, the dummy gate in NMOS area Dummy gate structure in structure and PMOS area.Remove the virtual grid in the dummy gate structure and PMOS area in NMOS area Pole structure, to form metal gates groove;

In step 402, be sequentially depositing in the metal gates groove in NMOS area and PMOS area to be formed boundary layer, High k dielectric layer, coating;

In step 403, standard threshold voltage region, low threshold region and high threshold region are executed respectively Oxygen scavenger injection;

In step 404, annealing steps are executed.

In conclusion the physics that production method according to the present invention changes boundary layer (IL) using oxygen clean-up effect is thick Degree, the method achieve the dielectric layer that the different zones in semiconductor substrate form different-thickness, the dielectric layer includes that high K is situated between Electric layer and IL dielectric layer, while the requirement for adjusting different voltages device is met, the overall performance of semiconductor devices is improved, is improved The yields of semiconductor.Production method of the invention is suitable for plane field effect transistor semiconductor technology and FinFET(fin Field effect transistor) semiconductor technology.

The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art Member it is understood that the present invention is not limited to the above embodiments, can also make according to the present invention more kinds of modifications and Modification, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention is by attached Claims and its equivalent scope are defined.

Claims (8)

1. a kind of method for making semiconductor devices, comprising:
The semiconductor substrate for having standard threshold voltage region, high threshold region and low threshold region is provided, it is described Standard threshold voltage region includes the first dummy gate, and the low threshold region includes the second dummy gate, the high threshold Threshold voltage region includes third dummy gate;
First dummy gate in the standard threshold voltage region is removed, the institute in the low threshold region is removed The second dummy gate is stated, the third dummy gate in the high threshold region is removed, in the level threshold value electricity First groove is formed in intermediate pressure section, forms second groove in the low threshold region, in the high threshold region Middle formation third groove;
It is sequentially depositing to form high K Jie on the first groove, the bottom of the second groove and the third groove and side wall Electric layer and coating form interfacial TCO layer between the semiconductor substrate and the high k dielectric layer;
The coating in the high threshold region is removed to expose the high k dielectric layer;
Oxygen scavenger injection is executed to the low threshold region;
Execute annealing steps.
2. a kind of method for making semiconductor devices, comprising:
The semiconductor substrate for having standard threshold voltage region, high threshold region and low threshold region is provided, it is described Standard threshold voltage region includes the first dummy gate, and the low threshold region includes the second dummy gate, the high threshold Threshold voltage region includes third dummy gate;
First dummy gate in the standard threshold voltage region is removed, the institute in the low threshold region is removed The second dummy gate is stated, the third dummy gate in the high threshold region is removed, in the level threshold value electricity First groove is formed in intermediate pressure section, forms second groove in the low threshold region, in the high threshold region Middle formation third groove;
It is sequentially depositing to form high K Jie on the first groove, the bottom of the second groove and the third groove and side wall Electric layer and coating form interfacial TCO layer between the semiconductor substrate and the high k dielectric layer;
It is clear that oxygen is executed to the standard threshold voltage region, the high threshold region and the low threshold region respectively Except agent is injected;
Execute annealing steps.
3. method according to claim 1 or 2, which is characterized in that the material of the oxygen scavenger is Ti, Al or Hf.
4. method according to claim 1 or 2, which is characterized in that the reaction temperature of the annealing steps is 600 to 800 DEG C, The reaction time of the annealing steps is 30 to 60s, and the reaction pressures of the annealing steps is 1 to 20atm, be passed through oxygen and The annealing steps are executed under conditions of the mixed gas of nitrogen.
5. method according to claim 2, which is characterized in that when using identical oxygen scavenger material, the Low threshold The doping injection of voltage regime is greater than the implantation concentration in the standard threshold voltage region, the note in the standard threshold voltage region Enter the implantation concentration that concentration is greater than the high threshold region.
6. method according to claim 2, which is characterized in that when the implantation concentration of oxygen scavenger is identical, the Low threshold The Scavenging activity of oxygen scavenger in voltage regime is greater than the Scavenging activity of the oxygen scavenger in the standard threshold voltage region, The Scavenging activity of oxygen scavenger in the standard threshold voltage region is greater than the oxygen scavenger in the high threshold region Scavenging activity.
7. the method as described in claim 1, which is characterized in that further include removed after the annealing steps it is remaining described Coating is to expose the high k dielectric layer.
8. the method for claim 7, which is characterized in that further include exposing after removing the remaining coating The high k dielectric layer on form new coating.
CN201410100745.5A 2014-03-18 2014-03-18 A method of making semiconductor devices CN104934376B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410100745.5A CN104934376B (en) 2014-03-18 2014-03-18 A method of making semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410100745.5A CN104934376B (en) 2014-03-18 2014-03-18 A method of making semiconductor devices

Publications (2)

Publication Number Publication Date
CN104934376A CN104934376A (en) 2015-09-23
CN104934376B true CN104934376B (en) 2019-01-18

Family

ID=54121480

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410100745.5A CN104934376B (en) 2014-03-18 2014-03-18 A method of making semiconductor devices

Country Status (1)

Country Link
CN (1) CN104934376B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107706099A (en) * 2016-08-08 2018-02-16 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1282098A (en) * 1999-07-21 2001-01-31 摩托罗拉公司 Method for forming semiconductor device
CN101218684A (en) * 2004-11-15 2008-07-09 国际商业机器公司 Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7274076B2 (en) * 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
CN101685800B (en) * 2008-09-26 2012-02-01 台湾积体电路制造股份有限公司 A method of manufacturing a semiconductor device
CN101764094B (en) * 2008-12-24 2012-07-11 北大方正集团有限公司 Method for regulating threshold voltage of complementary metal oxide semiconductor
CN101783299B (en) * 2009-01-20 2011-07-20 中芯国际集成电路制造(上海)有限公司 MOS (Metal Oxide Semiconductor) formation method and threshold voltage adjustment method thereof
DE102009021486B4 (en) * 2009-05-15 2013-07-04 Globalfoundries Dresden Module One Llc & Co. Kg Method for field effect transistor production
CN102157379B (en) * 2010-02-11 2013-10-02 中国科学院微电子研究所 High-performance semiconductor device and manufacturing method thereof
CN102403335A (en) * 2010-09-07 2012-04-04 无锡华润上华半导体有限公司 MOS (metal oxide semiconductor) device and manufacturing method for same
CN102420185A (en) * 2010-09-25 2012-04-18 中芯国际集成电路制造(上海)有限公司 Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor)
CN102810479A (en) * 2011-06-01 2012-12-05 广东中显科技有限公司 Polycrystalline silicon thin-film transistor manufacturing method capable of driving in nickel and adjusting threshold voltage simultaneously

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1282098A (en) * 1999-07-21 2001-01-31 摩托罗拉公司 Method for forming semiconductor device
CN101218684A (en) * 2004-11-15 2008-07-09 国际商业机器公司 Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Also Published As

Publication number Publication date
CN104934376A (en) 2015-09-23

Similar Documents

Publication Publication Date Title
US9000531B2 (en) Method and manufacture of transistor devices
US8476678B2 (en) CMOS Transistor with dual high-k gate dielectric
US8785286B2 (en) Techniques for FinFET doping
US8786028B2 (en) Semiconductor device and method of fabricating the same
US9659962B2 (en) Semiconductor devices and methods of manufacture thereof
CN103762236B (en) Integrated circuit package and its manufacture method
US7462538B2 (en) Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
CN104681613B (en) The FIN structures of semiconductor devices
US9257348B2 (en) Methods of forming replacement gate structures for transistors and the resulting devices
US9450097B2 (en) Methods for doping Fin field-effect transistors and Fin field-effect transistor
US8309419B2 (en) CMOS integration with metal gate and doped high-K oxides
US20070052037A1 (en) Semiconductor devices and methods of manufacture thereof
US8390080B2 (en) Transistor with dopant-bearing metal in source and drain
US9054130B2 (en) Bottle-neck recess in a semiconductor device
CN102117750B (en) Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof
US7253050B2 (en) Transistor device and method of manufacture thereof
US8004047B2 (en) Semiconductor devices and methods of manufacture thereof
US20060073643A1 (en) Transistor with doped gate dielectric
US9318388B2 (en) Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
CN104022037A (en) Fin type field effect transistor and forming method thereof
US20150255557A1 (en) Semiconductor device and method for manufacturing the same
TW201036070A (en) Semiconductor devices and fabrication methods thereof
US8395215B2 (en) Germanium field effect transistors and fabrication thereof
WO2011044776A1 (en) Forming method for semiconductor device
US9425194B2 (en) Transistor devices with high-k insulation layers

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
GR01