CN104917573B - The absolute time delay calibrating installation of a kind of antenna beam synthesis phase and method - Google Patents
The absolute time delay calibrating installation of a kind of antenna beam synthesis phase and method Download PDFInfo
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Abstract
The invention provides a kind of absolute time delay calibrating installation and the method for antenna beam synthesis phase, described device includes that the attenuator module being sequentially connected with, radio frequency variable connector module, radio frequency down-conversion module, analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module, code phase carrier phase resolve module.The present invention is capable of the absolute latency measurement of multichannel, reduces the resource that multichannel distance measurement is consumed simultaneously.
Description
Technical field
The present invention relates to signal transacting field, be specifically related to the exhausted of a kind of antenna beam synthesis phase
To time-delay calibration device and method.
Background technology
Multichannel width tests system mutually based on DSSS, is applied to the aerial array of digital beam-forming
Amplitude-phase consistency test, existing antenna beam synthesis width test equipment mutually in, for single-pass
For road system, it is difficult to carry out absolute latency measurement, and for multi-channel system, be also only limitted to
Value in relative time delay between energy Measurement channel.But, the measurement of the absolute time delay of system is directly connected to
Systematic parameter index and multi channel signals arrive the phase difference of test interface, simultaneously as be
System is made a start the unpredictable of carrier phase, can also calculate by means of absolute latency measurement and make a start
Phase place, and then improve the measuring precision.Therefore, the absolute time delay of antenna beam synthesis phase
Measure and there is important practical significance.
Summary of the invention
For defect of the prior art, the present invention provides the exhausted of a kind of antenna beam synthesis phase
To time-delay calibration device and method, it is achieved that the absolute latency measurement of multichannel, reduce many simultaneously
The resource that passage range finding is consumed.
For solving above-mentioned technical problem, the present invention provides techniques below scheme:
First aspect, the invention provides the absolute time-delay calibration of a kind of antenna beam synthesis phase
Device, including the attenuator module being sequentially connected with, radio frequency variable connector module, radio frequency down-conversion
Module, analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module,
Code phase carrier phase resolves module；
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code with
Track module and code phase carrier phase resolve module composition IF signal processing system, system under test (SUT)
The pulse per second (PPS) reference signal of output and homology clock connect the input of IF signal processing system；
Described attenuator module includes the first attenuator, the second attenuator ..., kth decays
Device, k >=1, described kth attenuator is for the merit of the signal to the output of system under test (SUT) kth passage
Rate decays；The spreading rate of the signal of described system under test (SUT) output is Y；
Described radio frequency variable connector module is for carrying out the signal of system under test (SUT) kth passage output
Time-division switches；
Described radio frequency down-conversion module is for carrying out becoming under radio frequency to input a certain road therein signal
Frequency is to intermediate-freuqncy signal；
Described analog-to-digital conversion module obtains numeral letter for described intermediate-freuqncy signal carries out analog-to-digital conversion
Number；
Described intermediate frequency down conversion module, for described data signal is carried out Digital Down Convert, obtains
Two-way baseband signal, including I roadbed band signal and Q roadbed band signal；
Described Code acquisition module is for carrying out acquiring pseudo code to the two-way baseband signal obtained；
Described code tracking module is for adopting by pulse per second (PPS) reference signal after receiving acquisition success signal
The phase place of sample code ring followed the tracks of after current code phase and I road and the result of Q road relevant peaks；
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT).
Wherein, described code phase carrier phase resolves module specifically for mode as described below
The absolute time delay of calculating system under test (SUT):
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is absolute
Delay measurements.
Wherein, described code tracking module includes that code tracking loop, described code tracking loop include mirror
Phase device, loop filter and code NCO；
Described phase discriminator is for the PN code corresponding with this locality respectively according to the signal of output after capture
Current road, advanced road and delayed road carry out the correlation result that digital matched filtering obtains and enter
Row dot product phase demodulation, and identified result is input to loop filter；
Loop filtering result is input to described code NCO by described loop filter, with control and regulation
The output code phase place of local code improves tracking accuracy, the current code phase after output tracking and I, Q
The correlation peak of two-way.
Wherein, described code tracking loop is first-order loop.
Wherein, described intermediate frequency down conversion module is additionally operable to described data signal is carried out high-frequency signal
Filter.
Wherein, the if sampling speed that described radio frequency down-conversion module is used is described tested system
Spreading rate non-integral multiple of the signal of system output.
Second aspect, present invention also offers the absolute time delay school of a kind of antenna beam synthesis phase
Quasi-method, including:
S1, the multiple signals of reception system under test (SUT) output, described multiple signals are by system under test (SUT)
Multiple passages export respectively；The spreading rate of the signal of described system under test (SUT) output is Y；
S2, to receive multiple signals decay and control described multiple signals according to time-division side
Formula carries out subsequent step S2-S8；
S3, a certain road signal is carried out radio frequency down-conversion to intermediate-freuqncy signal；
S4, described intermediate-freuqncy signal is carried out analog-to-digital conversion obtain data signal；
S5, described data signal is carried out Digital Down Convert, obtain two-way baseband signal, including I
Roadbed band signal and Q roadbed band signal；
S6, the baseband signal obtained is carried out acquiring pseudo code；
S7, receive acquisition success signal after obtain by the phase place of pulse per second (PPS) reference signal samples code ring
Current code phase after tracking and I road and the result of Q road relevant peaks；Described pulse per second (PPS) benchmark is believed
It number it is the pps pulse per second signal of described system under test (SUT) output；
S8, the absolute time delay of calculating system under test (SUT).
Wherein, described step S8 mode as described below calculates the absolute time delay of system under test (SUT):
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is absolute
Delay measurements.
Wherein, described step S5 is when carrying out Digital Down Convert to described data signal, also to institute
State data signal to carry out high-frequency signal and filter.
Wherein, after described step S3 radio frequency down-conversion, carry out signal transacting at intermediate frequency, use intermediate frequency
Measure the Amplitude-phase relation of radio frequency
As shown from the above technical solution, the present invention is by using the absolute of antenna beam synthesis phase
Latency measurement achieves the absolute latency measurement of multichannel, relative to existing multichannel latency measurement
Mode, decrease consumed resource, reduce the complexity of design.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing used required in embodiment or description of the prior art will be briefly described, aobvious and
Easily insight, the accompanying drawing in describing below is some embodiments of the present invention, common for this area
From the point of view of technical staff, on the premise of not paying creative work, it is also possible to according to these accompanying drawings
Obtain other accompanying drawing.
Fig. 1 is the absolute time-delay calibration of the antenna beam synthesis phase that the embodiment of the present invention one provides
The structural representation of device；
Fig. 2 is the acquiring pseudo code schematic flow sheet that the embodiment of the present invention one provides；
Fig. 3 is the pseudo-code tracing loop schematic flow sheet that the embodiment of the present invention one provides；
Fig. 4 is the absolute time-delay calibration of the antenna beam synthesis phase that the embodiment of the present invention two provides
The flow chart of method.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below will knot
Close the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear,
Complete description, it is clear that described embodiment be a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
Make the every other embodiment obtained under creative work premise, broadly fall into present invention protection
Scope.
The present invention is to solve that the port number that existing latency measurement system can be measured simultaneously is few, difficult
With the problem measuring absolute time delay, it is proposed that the absolute time delay of a kind of antenna beam synthesis phase is surveyed
Amount apparatus and method, it is achieved that the absolute latency measurement of multichannel, reduce multichannel distance measurement simultaneously
The resource consumed.
Fig. 1 shows the absolute time delay of the antenna beam synthesis phase that the embodiment of the present invention one provides
The structural representation of calibrating installation, sees Fig. 1, including the attenuator module being sequentially connected with, radio frequency
Variable connector module, radio frequency down-conversion module, analog-to-digital conversion module, intermediate frequency down conversion module,
Code acquisition module, code tracking module, code phase carrier phase resolve module；
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code with
Track module and code phase carrier phase resolve module composition IF signal processing system, tested system
The pulse per second (PPS) reference signal of system output and homology clock connect the input of IF signal processing system；
Described attenuator module includes the first attenuator, the second attenuator ..., kth decays
Device, k >=1, described kth attenuator is for the merit of the signal to the output of system under test (SUT) kth passage
Rate decays；The spreading rate of the signal of described system under test (SUT) output is Y；
Described radio frequency variable connector module is for carrying out the signal of system under test (SUT) kth passage output
Time-division switches；
Described radio frequency down-conversion module is for carrying out becoming under radio frequency to input a certain road therein signal
Frequency is to intermediate-freuqncy signal；
Described analog-to-digital conversion module obtains numeral letter for described intermediate-freuqncy signal carries out analog-to-digital conversion
Number；
Described intermediate frequency down conversion module, for described data signal is carried out Digital Down Convert, obtains
Two-way baseband signal, including I roadbed band signal and Q roadbed band signal；
Described Code acquisition module is for carrying out acquiring pseudo code to the two-way baseband signal obtained；Code is caught
The process that obtains specifically can be found in Fig. 2.
Described code tracking module is for adopting by pulse per second (PPS) reference signal after receiving acquisition success signal
The phase place of sample code ring followed the tracks of after current code phase and I road and the result of Q road relevant peaks；
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT).
Wherein, described code phase carrier phase resolves module specifically for mode as described below
The absolute time delay of calculating system under test (SUT):
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is exhausted
To delay measurements.
Further, described code tracking module includes code tracking loop, described code tracking loop bag
Include phase discriminator, loop filter and code NCO；
Described phase discriminator is for the PN code corresponding with this locality respectively according to the signal of output after capture
Current road, advanced road and delayed road carry out the correlation result that digital matched filtering obtains and enter
Row dot product phase demodulation, and identified result is input to loop filter；
Loop filtering result is input to described code NCO by described loop filter, with control and regulation
The output code phase place of local code improves tracking accuracy, the current code phase after output tracking and I, Q
The correlation peak of two-way.
Fig. 3 is code tracking block process schematic diagram, as seen from Figure 3, and code tracking loop route phase demodulation
Device, loop filter and code NCO composition.After capture, the signal of output is corresponding with this locality respectively
The current road of PN code, advanced road and delayed road carry out the related operation of digital matched filtering,
To result carry out dot product phase demodulation, identified result is input to loop filter, loop filter
Result is input to a yard NCO, and the output code phase place of control and regulation local code improves tracking accuracy, defeated
Go out the current code phase after following the tracks of and the correlation peak of I, Q two-way and calculate pseudo-random code ranging result
With carrier phase result, last solution calculates the multichannel absolute time delay result of carrier phase.
Preferably, described code tracking loop is first-order loop.
Preferably, described code tracking module is used for producing the current code phase with after capture is initial
Input signal is tracked by the local code of phase place, reduces local code phase place further and receives letter
The error of number phase alignment.
Preferably, described intermediate frequency down conversion module is additionally operable to described data signal is carried out high frequency letter
Number filter.
Preferably, the if sampling speed that described radio frequency down-conversion module is used is described tested
Spreading rate non-integral multiple of the signal of system output, to avoid obscure the complete cycle of chip.
It is measured as example with the absolute time delay of two passages below, the specific implementation process of the present invention is entered
Row explanation.It is defeated that the absolute time delay calibrating installation of described antenna beam synthesis phase receives system under test (SUT)
The pulse per second (PPS) reference signal of the 1pps gone out and the homology clock of 10.23MHz, system under test (SUT) exports
Radiofrequency signal respectively through two-way attenuator, access RF switch, wherein the penetrating of radiofrequency signal
Again and again point is 2492.028MHz, and spreading rate is 8.184MHz, specifically includes following steps:
Step a, the port number making the absolute latency measurement of multichannel are 2, receive system under test (SUT) output
Signal.
The signal received in step b, step a is input to penetrate after attenuator carries out power attenuation
Frequently the switching network time-division enters radio frequency down-conversion module, the sample rate of described radio frequency down-conversion module
For 140MHz, radio frequency down-conversion module is output as the intermediate-freuqncy signal of 75MHz.
Step c, by radio frequency down-conversion module export intermediate-freuqncy signal be input to analog-to-digital conversion module,
Analog-to-digital conversion module sends into intermediate frequency down coversion after the intermediate-freuqncy signal received is converted to data signal
Module, intermediate frequency down conversion module is defeated after using predeterminated frequency that described data signal is carried out down coversion
Go out I road and Q road two paths of signals is input to Code acquisition module.
The signal received and local pseudo-code are carried out related operation and obtain by step d, Code acquisition module
Relevant peaks compare with decision threshold, higher than decision threshold then acquisition success, output capture
Flag bit and current code phase also proceed to tracking module, referring specifically to Fig. 2.
Step e, tracking module by trapping module output signal and by catch code phase place initiate current
The local pseudo-code signal on road, advanced road and delayed road carries out related operation, result is exported a little
Long-pending phase discriminator, enters into a yard NCO module after loop filtering, and the local pseudo-code phase of regulation makes this
Ground pseudo-code phase and input code phase alignment, after receiving end is completely and in measured signal synchronization,
Gathered by pulse per second (PPS) and hold I road, current road and the current road code of the correlation peak on Q road and tracking
Phase place calculates time delay measures.
Understanding from the description above, transmitting-receiving two-end shares the reference clock of same 1pps, utilizes this
Individual reference clock can calculate the absolute time delay of system under test (SUT).Antenna beam synthesis phase exhausted
Latency measurement device can be measured multichannel absolute time delay value simultaneously, and at multi-channel parallel
On the basis of latency measurement system, due to the effect of time-division, decrease multi-channel system and consumed
Resource, reduce the complexity of system hardware.
Fig. 4 shows the absolute time delay of the antenna beam synthesis phase that the embodiment of the present invention two provides
The flow chart of calibration steps, sees Fig. 4, the antenna beam synthesis phase that the embodiment of the present invention two provides
The absolute time delay calibrating method of position includes:
Step 101: receiving the multiple signals of system under test (SUT) output, described multiple signals are by tested system
Multiple passages of system export respectively；The spreading rate of the signal of described system under test (SUT) output is Y.
Step 102: to receive multiple signals decay and control described multiple signals according to time
Point mode carries out subsequent step 103-108.
Step 103: a certain road signal is carried out radio frequency down-conversion to intermediate-freuqncy signal.
In this step, after radio frequency down-conversion, carry out signal transacting at intermediate frequency, use intermediate frequency to measure
The Amplitude-phase relation of radio frequency.
Step 104: described intermediate-freuqncy signal is carried out analog-to-digital conversion and obtains data signal.
Step 105: described data signal is carried out Digital Down Convert, obtains two-way baseband signal,
Including I roadbed band signal and Q roadbed band signal.
In this step, when described data signal is carried out Digital Down Convert, also to described number
Word signal carries out high-frequency signal and filters.
Step 106: the baseband signal obtained is carried out acquiring pseudo code.
Step 107: use the phase place of pulse per second (PPS) reference signal samples code ring after receiving acquisition success signal
Current code phase after being followed the tracks of and I road and the result of Q road relevant peaks；Described pulse per second (PPS) base
Calibration signal is the pps pulse per second signal of described system under test (SUT) output.
In this step, the absolute time delay calibrating installation of antenna beam synthesis phase and system under test (SUT)
Share a pulse per second (PPS) to exist as clock reference, the absolute time-delay calibration of antenna beam synthesis phase
Start after synchronously completing with pulse per second (PPS) to adopt current phase place and relevant peaks result and then to resolve final
Absolute time delay measures.
Step 108: calculate the absolute time delay of system under test (SUT).
In this step, mode calculates the absolute time delay of system under test (SUT) as described below:
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is absolute
Delay measurements.
Specifically, the device described in above-described embodiment one can be in order to perform described in the present embodiment two
Method, its principle is similar with technique effect, the most no longer describes in detail.
Below by verifying the effect of device and method described in above-described embodiment.
The absolute time delay calibrating installation of antenna beam synthesis phase described in this experiment receives tested system
The pulse per second (PPS) reference signal of the 1pps of system output and the homology clock of 10.23MHz, system under test (SUT)
The radiofrequency signal of output, respectively through two-way attenuator, accesses RF switch.RF spot is
2492.028MHz, modulation system is BPSK, and spreading rate is 8.184MHz, frequency expansion sequence
For m-sequence.
Table 1 is the calibration data measured result of passage 1 and passage 2；Table 2 and table 3 are respectively
Passage 1 and passage 2 calibration after power, phase place, delay inequality measured result.
Table 1
| Channel power poor (dB) | Phase difference between channels (is spent) | Channel time delay poor (ns) | |
| Passage 1 | -41.261 | 140.16 | 8.18180 |
| Passage 2 | -41.167 | 309.40 | 8.37055 |
Table 1 has been presented for the calibrator quantity of tester, uses this calibrator quantity, can be by advance
If this calibrator quantity after being calibrated the difference power of each passage, phase difference and channel time delay poor.Pass through
Repeatedly remeasure (totally 10 times), obtain the difference power relative to passage 1 calibration value, carrier wave
Phase difference and absolute delay inequality result totally 10 groups as follows.
Table 2
Then change into leading to by passage 1 by tested passage in the case of the not power-off of whole test environment
Road 2, on this basis by repeatedly remeasuring (totally 10 times), obtain passage 2 measured value and
Difference power between calibration value, carrier phase difference and definitely delay inequality result totally 10 groups as follows:
Table 3
| Channel power poor (dB) | Phase difference between channels (is spent) | Channel time delay poor (ns) | |
| For the first time | -0.079 | 0.29 | 0.00026 |
| For the second time | -0.053 | 0.25 | 0.00027 |
| For the third time | -0.036 | 0.34 | 0.00029 |
| 4th time | -0.041 | 0.32 | 0.00030 |
| 5th time | -0.022 | 0.28 | 0.00025 |
| 6th time | -0.041 | 0.25 | 0.00021 |
| 7th time | -0.073 | 0.24 | 0.00024 |
| 8th time | -0.023 | 0.27 | 0.00023 |
| 9th time | -0.026 | 0.34 | 0.00032 |
| Tenth time | -0.037 | 0.39 | 0.00026 |
By table 2 and table 3, it may be concluded that after Jiao Zhun, the measured value of each passage relative to
The difference power of calibration value and carrier phase difference are close to 0.According to " 10 measurements take majority "
Principle, each is calibrated the passage delay inequality measurement result relative to its calibration value also close to 0.By
This is visible, and calibration data determines that effectively.After loading calibration data, Measurement channel and Qi Ge
The power of self calibration value, phase place and delay inequality can make zero, thus reached the target of calibration.
In sum, application assembly of the invention realizes the absolute latency measurement of multichannel, completes many
The absolute time-delay calibration of passage, relative to the mode of existing multichannel latency measurement, decreases
The resource consumed, reduces the complexity of design.
Above example is merely to illustrate technical scheme, is not intended to limit；Although
With reference to previous embodiment, the present invention is described in detail, those of ordinary skill in the art
It is understood that the technical scheme described in foregoing embodiments still can be modified by it,
Or wherein portion of techniques feature is carried out equivalent；And these amendments or replacement, do not make
The essence of appropriate technical solution departs from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. the absolute time delay calibrating installation of an antenna beam synthesis phase, it is characterised in that bag
Include be sequentially connected with attenuator module, radio frequency variable connector module, radio frequency down-conversion module, mould
Number conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module, code phase carry
Wave phase resolves module；
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code with
Track module and code phase carrier phase resolve module composition IF signal processing system, system under test (SUT)
The pulse per second (PPS) reference signal of output and homology clock connect the input of IF signal processing system；
Described attenuator module includes that the first attenuator is to kth attenuator, k >=1, described kth
Attenuator is for decaying to the power of the signal of system under test (SUT) kth passage output；Described quilt
The spreading rate of the signal of examining system output is Y；
Described radio frequency variable connector module is for carrying out the signal of system under test (SUT) kth passage output
Time-division switches；
Described radio frequency down-conversion module is for carrying out becoming under radio frequency to input a certain road therein signal
Frequency is to intermediate-freuqncy signal；
Described analog-to-digital conversion module obtains numeral letter for described intermediate-freuqncy signal carries out analog-to-digital conversion
Number；
Described intermediate frequency down conversion module, for described data signal is carried out Digital Down Convert, obtains
Two-way baseband signal, including I roadbed band signal and Q roadbed band signal；
Described Code acquisition module is for carrying out acquiring pseudo code to the two-way baseband signal obtained；
Described code tracking module is for adopting by pulse per second (PPS) reference signal after receiving acquisition success signal
The phase place of sample code ring followed the tracks of after current code phase and I road and the result of Q road relevant peaks；
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT)；
Wherein, described code phase carrier phase resolves module specifically for mode as described below
The absolute time delay of calculating system under test (SUT):
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is absolute
Delay measurements.
Device the most according to claim 1, it is characterised in that described code tracking module bag
Including code tracking loop, described code tracking loop includes phase discriminator, loop filter and code NCO；
Described phase discriminator is for the PN code corresponding with this locality respectively according to the signal of output after capture
Current road, advanced road and delayed road carry out the correlation result that digital matched filtering obtains and enter
Row dot product phase demodulation, and identified result is input to loop filter；
Loop filtering result is input to described code NCO by described loop filter, with control and regulation
The output code phase place of local code improves tracking accuracy, the current code phase after output tracking and I, Q
The correlation peak of two-way.
Device the most according to claim 2, it is characterised in that described code tracking loop is
First-order loop.
Device the most according to claim 1, it is characterised in that described intermediate frequency down coversion mould
Block is additionally operable to that described data signal is carried out high-frequency signal and filters.
Device the most according to claim 1, it is characterised in that described radio frequency down-conversion mould
The if sampling speed that block is used is the non-of the spreading rate of the signal of described system under test (SUT) output
Integral multiple.
6. the absolute time delay calibrating method of an antenna beam synthesis phase, it is characterised in that bag
Include:
S1, the multiple signals of reception system under test (SUT) output, described multiple signals are by system under test (SUT)
Multiple passages export respectively；The spreading rate of the signal of described system under test (SUT) output is Y；
S2, to receive multiple signals decay and control described multiple signals according to time-division side
Formula carries out subsequent step S3-S8；
S3, a certain road signal is carried out radio frequency down-conversion to intermediate-freuqncy signal；
S4, described intermediate-freuqncy signal is carried out analog-to-digital conversion obtain data signal；
S5, described data signal is carried out Digital Down Convert, obtain two-way baseband signal, including I
Roadbed band signal and Q roadbed band signal；
S6, the baseband signal obtained is carried out acquiring pseudo code；
S7, receive acquisition success signal after obtain by the phase place of pulse per second (PPS) reference signal samples code ring
Current code phase after tracking and I road and the result of Q road relevant peaks；Described pulse per second (PPS) benchmark is believed
It number it is the pps pulse per second signal of described system under test (SUT) output；
S8, the absolute time delay of calculating system under test (SUT)；
Wherein, described S8 mode as described below calculates the absolute time delay of system under test (SUT):
Wherein, n is half yard when the reference clock of 1pps arrives of regeneration pseudo-code chip counter
The output of sheet counter, m is the output of the phase output register of 32bit phase accumulator, T
For integration checkout time, Y is the spreading rate of the signal of described system under test (SUT) output, and Δ is absolute
Delay measurements.
Method the most according to claim 6, it is characterised in that described step S5 is right
When described data signal carries out Digital Down Convert, also described data signal is carried out high-frequency signal filter
Remove.
Method the most according to claim 6, it is characterised in that described step S3 radio frequency
Carry out signal transacting at intermediate frequency after down coversion, use intermediate frequency to measure the Amplitude-phase relation of radio frequency.
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| CN105375966B (en) * | 2015-10-08 | 2018-07-27 | 成都中远信电子科技有限公司 | System and method are verified based on the digital bea mforming that array signal receives |
| CN107124204B (en) * | 2017-05-26 | 2018-03-13 | 北京理工大学 | A kind of ultra wide band synchronization method of numerical model analysis |
| CN107222274B (en) * | 2017-07-11 | 2020-07-07 | 成都德芯数字科技股份有限公司 | Delay detection method and system |
| CN108650048B (en) * | 2018-04-03 | 2019-12-31 | 广州大学 | High-precision digital array multi-channel delay compensation method |
| CN109001729B (en) * | 2018-06-15 | 2020-05-22 | 中国电子科技集团公司第四十一研究所 | Real-time calibration method and system for linearity of frequency-modulated continuous wave in terahertz imaging |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102325058A (en) * | 2011-09-06 | 2012-01-18 | 北京空间飞行器总体设计部 | Frequency change system group delay test method |
| CN102694609A (en) * | 2012-05-25 | 2012-09-26 | 北京空间飞行器总体设计部 | Calibration method for RDSS channel zero value |
| JP2014116877A (en) * | 2012-12-12 | 2014-06-26 | Nippon Hoso Kyokai <Nhk> | Wraparound canceller, and relay device |
| CN104601265A (en) * | 2013-11-01 | 2015-05-06 | 上海精密计量测试研究所 | Absolute delay measurement method for frequency converter |
Family Cites Families (3)
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| US6592524B2 (en) * | 2000-12-22 | 2003-07-15 | Siemens Medical Solutions Usa, Inc. | Transmit beamformer delay architecture and method for diagnostic medical ultrasound |
| JP5692803B2 (en) * | 2011-04-06 | 2015-04-01 | 埼玉日本電気株式会社 | Relay amplifier, relay amplifier control method, and program |
| CN102647223B (en) * | 2012-03-26 | 2014-07-02 | 北京空间飞行器总体设计部 | Absolute time delay calibration method for inter-satellite link of navigational satellite |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102325058A (en) * | 2011-09-06 | 2012-01-18 | 北京空间飞行器总体设计部 | Frequency change system group delay test method |
| CN102694609A (en) * | 2012-05-25 | 2012-09-26 | 北京空间飞行器总体设计部 | Calibration method for RDSS channel zero value |
| JP2014116877A (en) * | 2012-12-12 | 2014-06-26 | Nippon Hoso Kyokai <Nhk> | Wraparound canceller, and relay device |
| CN104601265A (en) * | 2013-11-01 | 2015-05-06 | 上海精密计量测试研究所 | Absolute delay measurement method for frequency converter |
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