CN104917573A - Antenna beam synthesizing phase absolute delay calibration device and method - Google Patents
Antenna beam synthesizing phase absolute delay calibration device and method Download PDFInfo
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Abstract
The invention provides an antenna beam synthesizing phase absolute delay calibration device and method. The device comprises an attenuator module, a radio-frequency multi-channel switch module, a radio-frequency down-conversion module, an analog to digital conversion module, an intermediate frequency down-conversion module, a code capturing module, a code tracking module and a code phase carrier phase solver module, wherein the attenuator module, the radio-frequency multi-channel switch module, the radio-frequency down-conversion module, the analog to digital conversion module, the intermediate frequency down-conversion module, the code capturing module, the code tracking module and the code phase carrier phase solver module are sequentially connected. According to the invention, multi-channel absolute delay measuring is realized, and at the same time resources consumed by multi-channel ranging are reduced.
Description
Technical field
The present invention relates to signal transacting field, be specifically related to a kind of absolute time delay calibrating installation and method of antenna beam synthesis phase.
Background technology
Multichannel width phase test macro is based on DSSS, be applied to the amplitude-phase consistency test of the aerial array of digital beam-forming, in existing antenna beam synthesis width phase testing equipment, for single channel system, be difficult to carry out absolute latency measurement, and for multi-channel system, be also only limitted to the value in relative time delay between energy Measurement channel.But, the measurement of the absolute time delay of system is directly connected to the phase difference that system parameters index and multi channel signals arrive test interface, meanwhile, because system is made a start the unpredictable of carrier phase, can also phase place of making a start be calculated by means of absolute latency measurement, and then improve the measuring precision.Therefore, the absolute latency measurement of antenna beam synthesis phase has important practical significance.
Summary of the invention
For defect of the prior art, the invention provides a kind of absolute time delay calibrating installation and method of antenna beam synthesis phase, achieve the absolute latency measurement of multichannel, reduce the resource that multichannel distance measurement consumes simultaneously.
For solving the problems of the technologies described above, the invention provides following technical scheme:
First aspect, the invention provides a kind of absolute time delay calibrating installation of antenna beam synthesis phase, comprise the attenuator module, radio frequency variable connector module, radio frequency down-conversion module, analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module, the code phase carrier phase that connect successively and resolve module;
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module and code phase carrier phase resolve module composition IF signal processing system, and the pulse per second (PPS) reference signal that system under test (SUT) exports is connected the input of IF signal processing system with homology clock;
Described attenuator module comprises the first attenuator, the second attenuator ..., the n-th attenuator, n >=1, described n-th attenuator is used for decaying to the power of the signal that system under test (SUT) n-th passage exports; The spreading rate of the signal that described system under test (SUT) exports is Y;
The signal that described radio frequency variable connector module is used for system under test (SUT) n-th passage exports carries out time-division switching;
Described radio frequency down-conversion module is used for carrying out radio frequency down-conversion to intermediate-freuqncy signal to input a certain road signal wherein;
Described analog-to-digital conversion module is used for that described intermediate-freuqncy signal is carried out analog-to-digital conversion and obtains digital signal;
Described intermediate frequency down conversion module is used for carrying out Digital Down Convert to described digital signal, obtains two-way baseband signal, comprises I roadbed band signal and Q roadbed band signal;
Described Code acquisition module is used for carrying out acquiring pseudo code to the two-way baseband signal obtained;
Described code tracking module is used for the result obtaining the current code phase after following the tracks of and I road and Q road relevant peaks after receiving acquisition success signal by the phase place of pulse per second (PPS) reference signal samples code ring;
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT).
Wherein, described code phase carrier phase resolves module specifically for calculating the absolute time delay of system under test (SUT) according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
Wherein, described code tracking module comprises code tracking loop, and described code tracking loop comprises phase discriminator, loop filter and code NCO;
Described phase discriminator is used for carrying out according to the signal of catching rear output the correlation result that digital matched filtering obtains respectively with the current road of the PN code of this locality correspondence, advanced road and delayed road and carries out dot product phase demodulation, and identified result is input to loop filter;
Loop filtering result is input to described code NCO by described loop filter, improves tracking accuracy, the current code phase after output tracking and the correlation peak of I, Q two-way with the output code phase place of regulating and controlling local code.
Wherein, described code tracking loop is first-order loop.
Wherein, described intermediate frequency down conversion module is also for carrying out high-frequency signal filtering to described digital signal.
Wherein, the if sampling speed that described radio frequency down-conversion module adopts is the non-integral multiple of the spreading rate of the signal that described system under test (SUT) exports.
Second aspect, present invention also offers a kind of absolute time delay calibrating method of antenna beam synthesis phase, comprising:
The multiple signals that S1, reception system under test (SUT) export, described multiple signals are exported respectively by multiple passages of system under test (SUT); The spreading rate of the signal that described system under test (SUT) exports is Y;
S2, the multiple signals received are decayed and controlled described multiple signals and carry out subsequent step S2-S8 according to time division way;
S3, radio frequency down-conversion is carried out to intermediate-freuqncy signal to a certain road signal;
S4, described intermediate-freuqncy signal is carried out analog-to-digital conversion obtain digital signal;
S5, Digital Down Convert is carried out to described digital signal, obtain two-way baseband signal, comprise I roadbed band signal and Q roadbed band signal;
S6, acquiring pseudo code is carried out to the baseband signal obtained;
S7, receive acquisition success signal after obtain the current code phase after following the tracks of and the result of I road and Q road relevant peaks by the phase place of pulse per second (PPS) reference signal samples code ring; Described pulse per second (PPS) reference signal is the pps pulse per second signal that described system under test (SUT) exports;
The absolute time delay of S8, calculating system under test (SUT).
Wherein, described step S8 calculates the absolute time delay of system under test (SUT) according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
Wherein, described step S5, when carrying out Digital Down Convert to described digital signal, also carries out high-frequency signal filtering to described digital signal.
Wherein, after described step S3 radio frequency down-conversion, carry out signal transacting at intermediate frequency, adopt intermediate frequency to measure the Amplitude-phase relation of radio frequency
As shown from the above technical solution, the present invention achieves the absolute latency measurement of multichannel by adopting the absolute latency measurement of antenna beam synthesis phase, relative to the mode of existing multichannel latency measurement, decrease consumed resource, reduce the complexity of design.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the absolute time delay calibrating installation of the antenna beam synthesis phase that the embodiment of the present invention one provides;
Fig. 2 is the acquiring pseudo code schematic flow sheet that the embodiment of the present invention one provides;
Fig. 3 is the pseudo-code tracing loop schematic flow sheet that the embodiment of the present invention one provides;
Fig. 4 is the flow chart of the absolute time delay calibrating method of the antenna beam synthesis phase that the embodiment of the present invention two provides.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, clear, complete description is carried out to the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The present invention is in order to the problem that the port number solving existing latency measurement system and can measure is few, be difficult to measure absolute time delay simultaneously, propose a kind of absolute time delay measuring device and method of antenna beam synthesis phase, achieve the absolute latency measurement of multichannel, reduce the resource that multichannel distance measurement consumes simultaneously.
Fig. 1 shows the structural representation of the absolute time delay calibrating installation of the antenna beam synthesis phase that the embodiment of the present invention one provides, see Fig. 1, comprise the attenuator module, radio frequency variable connector module, radio frequency down-conversion module, analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module, the code phase carrier phase that connect successively and resolve module;
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module and code phase carrier phase resolve module composition IF signal processing system, and the pulse per second (PPS) reference signal that system under test (SUT) exports is connected the input of IF signal processing system with homology clock;
Described attenuator module comprises the first attenuator, the second attenuator ..., the n-th attenuator, n >=1, described n-th attenuator is used for decaying to the power of the signal that system under test (SUT) n-th passage exports; The spreading rate of the signal that described system under test (SUT) exports is Y;
The signal that described radio frequency variable connector module is used for system under test (SUT) n-th passage exports carries out time-division switching;
Described radio frequency down-conversion module is used for carrying out radio frequency down-conversion to intermediate-freuqncy signal to input a certain road signal wherein;
Described analog-to-digital conversion module is used for that described intermediate-freuqncy signal is carried out analog-to-digital conversion and obtains digital signal;
Described intermediate frequency down conversion module is used for carrying out Digital Down Convert to described digital signal, obtains two-way baseband signal, comprises I roadbed band signal and Q roadbed band signal;
Described Code acquisition module is used for carrying out acquiring pseudo code to the two-way baseband signal obtained; Code acquisition process specifically can see Fig. 2.
Described code tracking module is used for the result obtaining the current code phase after following the tracks of and I road and Q road relevant peaks after receiving acquisition success signal by the phase place of pulse per second (PPS) reference signal samples code ring;
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT).
Wherein, described code phase carrier phase resolves module specifically for calculating the absolute time delay of system under test (SUT) according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
Further, described code tracking module comprises code tracking loop, and described code tracking loop comprises phase discriminator, loop filter and code NCO;
Described phase discriminator is used for carrying out according to the signal of catching rear output the correlation result that digital matched filtering obtains respectively with the current road of the PN code of this locality correspondence, advanced road and delayed road and carries out dot product phase demodulation, and identified result is input to loop filter;
Loop filtering result is input to described code NCO by described loop filter, improves tracking accuracy, the current code phase after output tracking and the correlation peak of I, Q two-way with the output code phase place of regulating and controlling local code.
Fig. 3 is code tracking block process schematic diagram, and as seen from Figure 3, code tracking loop route phase discriminator, loop filter and code NCO form.The signal exported after catching carries out the related operation of digital matched filtering with the current road of the PN code of this locality correspondence, advanced road and delayed road respectively, the result obtained carries out dot product phase demodulation, identified result is input to loop filter, loop filter result is input to a yard NCO, the output code phase place of regulating and controlling local code improves tracking accuracy, current code phase after output tracking and the correlation peak of I, Q two-way also calculate pseudo-random code ranging result and carrier phase result, and last solution calculates the absolute time delay result of multichannel of carrier phase.
Preferably, described code tracking loop is first-order loop.
Preferably, described code tracking module is followed the tracks of input signal for generation of the local code being start-phase with the current code phase after catching, and reduces the error of local code phase place and Received signal strength code phase alignment further.
Preferably, described intermediate frequency down conversion module is also for carrying out high-frequency signal filtering to described digital signal.
Preferably, the if sampling speed that described radio frequency down-conversion module adopts is the non-integral multiple of the spreading rate of the signal that described system under test (SUT) exports, to avoid the complete cycle of chip fuzzy.
Be measured as example with the absolute time delay of two passages below, specific embodiment of the invention process is described.The absolute time delay calibrating installation of described antenna beam synthesis phase receives the pulse per second (PPS) reference signal of 1pps and the homology clock of 10.23MHz of system under test (SUT) output, the radiofrequency signal that system under test (SUT) exports is respectively through two-way attenuator, access radio-frequency (RF) switch, wherein the RF spot of radiofrequency signal is 2492.028MHz, spreading rate is 8.184MHz, specifically comprises the steps:
Step a, make the port number of the absolute latency measurement of multichannel be 2, receive the signal that system under test (SUT) exports.
The signal received in step b, step a carries out being input to radio-frequency (RF) switch network Time Division after power attenuation through attenuator and enters radio frequency down-conversion module, the sample rate of described radio frequency down-conversion module is 140MHz, and radio frequency down-conversion module exports the intermediate-freuqncy signal for 75MHz.
Step c, by radio frequency down-conversion module export intermediate-freuqncy signal be input to analog-to-digital conversion module, analog-to-digital conversion module sends into intermediate frequency down conversion module after the intermediate-freuqncy signal received is converted to digital signal, and intermediate frequency down conversion module exports I road after adopting predeterminated frequency to carry out down-conversion to described digital signal and Q road two paths of signals is input to Code acquisition module.
The signal received and local pseudo-code are carried out relevant peaks that related operation obtains by steps d, Code acquisition module and decision threshold compares, higher than decision threshold then acquisition success, output is caught flag bit and current code phase and is proceeded to tracking module, specifically see Fig. 2.
Step e, tracking module carry out related operation by trapping module output signal with by current road, the in advance local pseudo-code signal on road and delayed road that catch code phase place is initial, result is outputted to dot product phase discriminator, a yard NCO module is entered into after loop filtering, local pseudo-code phase is regulated to make local pseudo-code phase and input code phase alignment, after on receiving end is complete and measured signal is synchronous, is gathered by pulse per second (PPS) and hold I road, current road and the correlation peak on Q road and the current road code phase of tracking to calculate time delay measures.
Describe known from above, transmitting-receiving two-end shares the reference clock of same 1pps, utilizes this reference clock can calculate the absolute time delay of system under test (SUT).The absolute time delay measuring device of antenna beam synthesis phase can measure multichannel absolute time delay value simultaneously, and on the basis of multi-channel parallel latency measurement system, due to the effect of time-division, decrease the resource that multi-channel system consumes, reduce the complexity of system hardware.
Fig. 4 shows the flow chart of the absolute time delay calibrating method of the antenna beam synthesis phase that the embodiment of the present invention two provides, and see Fig. 4, the absolute time delay calibrating method of the antenna beam synthesis phase that the embodiment of the present invention two provides comprises:
Step 101: receive the multiple signals that system under test (SUT) exports, described multiple signals are exported respectively by multiple passages of system under test (SUT); The spreading rate of the signal that described system under test (SUT) exports is Y.
Step 102: the multiple signals received are decayed and controlled described multiple signals and carries out subsequent step 103-108 according to time division way.
Step 103: radio frequency down-conversion is carried out to intermediate-freuqncy signal to a certain road signal.
In this step, after radio frequency down-conversion, carry out signal transacting at intermediate frequency, adopt intermediate frequency to measure the Amplitude-phase relation of radio frequency.
Step 104: described intermediate-freuqncy signal is carried out analog-to-digital conversion and obtains digital signal.
Step 105: carry out Digital Down Convert to described digital signal, obtains two-way baseband signal, comprises I roadbed band signal and Q roadbed band signal.
In this step, when carrying out Digital Down Convert to described digital signal, also high-frequency signal filtering is carried out to described digital signal.
Step 106: acquiring pseudo code is carried out to the baseband signal obtained.
Step 107: the result obtaining the current code phase after following the tracks of and I road and Q road relevant peaks after receiving acquisition success signal by the phase place of pulse per second (PPS) reference signal samples code ring; Described pulse per second (PPS) reference signal is the pps pulse per second signal that described system under test (SUT) exports.
In this step, the absolute time delay calibrating installation of antenna beam synthesis phase and system under test (SUT) share a pulse per second (PPS) as clock reference, after the absolute time delay of antenna beam synthesis phase is aligned in and synchronously completes beginning with pulse per second (PPS) to adopt current phase place and relevant peaks result and then to resolve final absolute time delay measures.
Step 108: the absolute time delay calculating system under test (SUT).
In this step, the absolute time delay of system under test (SUT) is calculated according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
Particularly, the device described in above-described embodiment one can in order to perform the method described in the present embodiment two, its principle and technique effect similar, no longer describe in detail herein.
The effect of device and method described in above-described embodiment is verified below by experiment.
The absolute time delay calibrating installation of the synthesis phase of antenna beam described in this experiment receives the pulse per second (PPS) reference signal of 1pps and the homology clock of 10.23MHz of system under test (SUT) output, the radiofrequency signal that system under test (SUT) exports, respectively through two-way attenuator, accesses radio-frequency (RF) switch.RF spot is 2492.028MHz, and modulation system is BPSK, and spreading rate is 8.184MHz, and frequency expansion sequence is m sequence.
Table 1 is the calibration data measured result of passage 1 and passage 2; Table 2 and table 3 be respectively passage 1 and passage 2 calibrate after power, phase place, delay inequality measured result.
Table 1
| Channel power difference (dB) | Phase difference between channels (degree) | Channel time delay difference (ns) | |
| Passage 1 | -41.261 | 140.16 | 8.18180 |
| Passage 2 | -41.167 | 309.40 | 8.37055 |
Giving the calibrator quantity of tester in table 1, used this calibrator quantity, namely having obtained calibrating the difference power of rear each passage, phase difference and channel time delay by presetting this calibrator quantity poor.By repeatedly remeasuring (totally 10 times), obtain relative to the difference power of passage 1 calibration value, carrier phase difference and definitely delay inequality result totally 10 groups as follows.
Table 2
| Channel power difference (dB) | Phase difference between channels (degree) | Channel time delay difference (ns) | |
| For the first time | -0.001 | 0.07 | 0.00012 |
| For the second time | 0.002 | 0.26 | 0.00023 |
| For the third time | -0.041 | 0.23 | 0.00024 |
| 4th time | -0.028 | 0.21 | 0.00020 |
| 5th time | -0.001 | 0.18 | 0.00015 |
| 6th time | -0.01 | 0.20 | 0.00023 |
| 7th time | -0.028 | 0.24 | 0.00021 |
| 8th time | -0.027 | -0.03 | 0.00001 |
| 9th time | -0.036 | 0.28 | 0.00031 |
| Tenth time | -0.022 | 0.07 | 0.00008 |
Then tested passage is changed into passage 2 by passage 1 when whole test environment not power-off, on this basis by repeatedly remeasuring (totally 10 times), obtain the difference power between passage 2 measured value and calibration value, carrier phase difference and definitely delay inequality result totally 10 groups as follows:
Table 3
| Channel power difference (dB) | Phase difference between channels (degree) | Channel time delay difference (ns) | |
| For the first time | -0.079 | 0.29 | 0.00026 |
| For the second time | -0.053 | 0.25 | 0.00027 |
| For the third time | -0.036 | 0.34 | 0.00029 |
| 4th time | -0.041 | 0.32 | 0.00030 |
| 5th time | -0.022 | 0.28 | 0.00025 |
| 6th time | -0.041 | 0.25 | 0.00021 |
| 7th time | -0.073 | 0.24 | 0.00024 |
| 8th time | -0.023 | 0.27 | 0.00023 |
| 9th time | -0.026 | 0.34 | 0.00032 |
| Tenth time | -0.037 | 0.39 | 0.00026 |
By table 2 and table 3, can reach a conclusion: after calibration, the measured value of each passage relative to the difference power of calibration value and carrier phase difference close to 0.According to the principle of " majority is got in 10 measurements ", each is calibrated the delay inequality measurement result of passage relative to its calibration value also close to 0.As can be seen here, calibration data determines effectively.Load after calibration data, Measurement channel and its separately the power of calibration value, phase place and delay inequality can make zero, thus reach the target of calibration.
In sum, apply device of the present invention and realize the absolute latency measurement of multichannel, complete multichannel absolute time-delay calibration, relative to the mode of existing multichannel latency measurement, decrease consumed resource, reduce the complexity of design.
Above embodiment only for illustration of technical scheme of the present invention, is not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. the absolute time delay calibrating installation of an antenna beam synthesis phase, it is characterized in that, comprise the attenuator module, radio frequency variable connector module, radio frequency down-conversion module, analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module, the code phase carrier phase that connect successively and resolve module;
Wherein, described analog-to-digital conversion module, intermediate frequency down conversion module, Code acquisition module, code tracking module and code phase carrier phase resolve module composition IF signal processing system, and the pulse per second (PPS) reference signal that system under test (SUT) exports is connected the input of IF signal processing system with homology clock;
Described attenuator module comprises the first attenuator to the n-th attenuator, n >=1, and described n-th attenuator is used for decaying to the power of the signal that system under test (SUT) n-th passage exports; The spreading rate of the signal that described system under test (SUT) exports is Y;
The signal that described radio frequency variable connector module is used for system under test (SUT) n-th passage exports carries out time-division switching;
Described radio frequency down-conversion module is used for carrying out radio frequency down-conversion to intermediate-freuqncy signal to input a certain road signal wherein;
Described analog-to-digital conversion module is used for that described intermediate-freuqncy signal is carried out analog-to-digital conversion and obtains digital signal;
Described intermediate frequency down conversion module is used for carrying out Digital Down Convert to described digital signal, obtains two-way baseband signal, comprises I roadbed band signal and Q roadbed band signal;
Described Code acquisition module is used for carrying out acquiring pseudo code to the two-way baseband signal obtained;
Described code tracking module is used for the result obtaining the current code phase after following the tracks of and I road and Q road relevant peaks after receiving acquisition success signal by the phase place of pulse per second (PPS) reference signal samples code ring;
Described code phase carrier phase resolves module for calculating the absolute time delay of system under test (SUT).
2. device according to claim 1, is characterized in that, described code phase carrier phase resolves module specifically for calculating the absolute time delay of system under test (SUT) according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
3. device according to claim 1, is characterized in that, described code tracking module comprises code tracking loop, and described code tracking loop comprises phase discriminator, loop filter and code NCO;
Described phase discriminator is used for carrying out according to the signal of catching rear output the correlation result that digital matched filtering obtains respectively with the current road of the PN code of this locality correspondence, advanced road and delayed road and carries out dot product phase demodulation, and identified result is input to loop filter;
Loop filtering result is input to described code NCO by described loop filter, improves tracking accuracy, the current code phase after output tracking and the correlation peak of I, Q two-way with the output code phase place of regulating and controlling local code.
4. device according to claim 1, is characterized in that, described code tracking loop is first-order loop.
5. device according to claim 1, is characterized in that, described intermediate frequency down conversion module is also for carrying out high-frequency signal filtering to described digital signal.
6. device according to claim 1, is characterized in that, the if sampling speed that described radio frequency down-conversion module adopts is the non-integral multiple of the spreading rate of the signal that described system under test (SUT) exports.
7. an absolute time delay calibrating method for antenna beam synthesis phase, is characterized in that, comprising:
The multiple signals that S1, reception system under test (SUT) export, described multiple signals are exported respectively by multiple passages of system under test (SUT); The spreading rate of the signal that described system under test (SUT) exports is Y;
S2, the multiple signals received are decayed and controlled described multiple signals and carry out subsequent step S2-S8 according to time division way;
S3, radio frequency down-conversion is carried out to intermediate-freuqncy signal to a certain road signal;
S4, described intermediate-freuqncy signal is carried out analog-to-digital conversion obtain digital signal;
S5, Digital Down Convert is carried out to described digital signal, obtain two-way baseband signal, comprise I roadbed band signal and Q roadbed band signal;
S6, acquiring pseudo code is carried out to the baseband signal obtained;
S7, receive acquisition success signal after obtain the current code phase after following the tracks of and the result of I road and Q road relevant peaks by the phase place of pulse per second (PPS) reference signal samples code ring; Described pulse per second (PPS) reference signal is the pps pulse per second signal that described system under test (SUT) exports;
The absolute time delay of S8, calculating system under test (SUT).
8. method according to claim 7, is characterized in that, described step S8 calculates the absolute time delay of system under test (SUT) according to described mode below:
Wherein, n is the output of half chip counter of regeneration pseudo-code chip counter when the reference clock of 1pps arrives, m is the output of the phase output register of 32bit phase accumulator, T is the integrate and dump time, Y is the spreading rate of the signal that described system under test (SUT) exports, and Δ is absolute delay measurements.
9. method according to claim 7, is characterized in that, described step S5, when carrying out Digital Down Convert to described digital signal, also carries out high-frequency signal filtering to described digital signal.
10. method according to claim 7, is characterized in that, carries out signal transacting after described step S3 radio frequency down-conversion at intermediate frequency, adopts intermediate frequency to measure the Amplitude-phase relation of radio frequency.
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| CN108650048A (en) * | 2018-04-03 | 2018-10-12 | 广州大学 | A kind of high accuracy number arrayed multi-channel delay compensation method |
| CN109001729A (en) * | 2018-06-15 | 2018-12-14 | 中国电子科技集团公司第四十研究所 | CW with frequency modulation linearity real-time calibration method and its system in terahertz imaging |
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| CN107124204A (en) * | 2017-05-26 | 2017-09-01 | 北京理工大学 | A kind of ultra wide band synchronization method of numerical model analysis |
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| CN107222274B (en) * | 2017-07-11 | 2020-07-07 | 成都德芯数字科技股份有限公司 | Delay detection method and system |
| CN108650048A (en) * | 2018-04-03 | 2018-10-12 | 广州大学 | A kind of high accuracy number arrayed multi-channel delay compensation method |
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