CN104917466A - Pulsed power amplifier using drain electrode modulation mode - Google Patents
Pulsed power amplifier using drain electrode modulation mode Download PDFInfo
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- CN104917466A CN104917466A CN201510320586.4A CN201510320586A CN104917466A CN 104917466 A CN104917466 A CN 104917466A CN 201510320586 A CN201510320586 A CN 201510320586A CN 104917466 A CN104917466 A CN 104917466A
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Abstract
The invention relates to a pulsed power amplifier using a drain electrode modulation mode. A pulse modulation circuit is reused as a part of a power amplification circuit, so that the problem of reduction of output power and efficiency caused by great voltage drop resulting from the use of a single transistor as a control tube in a traditional pulse modulation circuit is solved. The pulsed power amplifier comprises an inductance laser diode (LD) with a center tap, a driving stage amplification circuit, an output stage amplification circuit, a biasing circuit 1 and a biasing circuit 2 which respectively provide direct current bias for the output stage amplification circuit and the driving stage amplification circuit. A radio frequency difference input signal is connected with a non-inverting input end and an inverted input end of the driving stage amplification circuit. An output end of the driving stage amplification circuit couples the amplified radio frequency signal to an input end of the output stage amplification circuit through capacitance, and finally, the output stage amplification circuit outputs a same-phase differential signal and a reverse phase differential signal.
Description
Technical field
The present invention relates to the pulse power amplifier in radar system, especially a kind of pulse power amplifier adopting drain modulation mode.
Background technology
At present, radar system has been widely used in national defence and the product for civilian use, produces far-reaching influence to people's daily life.Pulse power amplifier (Pulsed Power Amplifier, PPA) is the key modules of radar system, determines the performance of whole system.Pulse power amplifier refers to the power amplifier exporting under the effect of control signal and be interrupted radiofrequency signal.Along with the performance of radar system is become better and better, the development trend that volume is more and more less, small size, low-loss, high performance pulse power amplifier chip become study hotspot in recent years.
In pulse power amplifier circuit, the input pulse signal of pulse modulator circuit comprises high level (significant level) and low level (inactive level), and when pulse signal is high level, pulse power amplifier is in emission state; When pulse signal is low level, pulse power amplifier is in accepting state.Power amplifier is simplified to a field effect transistor, and the implementation of pulse modulator comprises grid modulation and drain modulation two kinds.
As shown in Figure 1, traditional drain modulation pulse power amplifier generally comprises pulse modulator circuit and the relatively independent module of power amplifier circuit two.Pulse modulated circuit is realized by single-transistor, and pulse signal controls conducting and the shutoff of transistor, thus controls the operating state of power amplifier.Power amplifier circuit generally adopts E power-like amplifier structure.The advantage of drain modulation pulse power amplifier is: 1) realize signal and launch the isolation with Signal reception, the interference do not transmitted when wait-receiving mode signal; 2) guaranteed output amplifier circuit not consumed power in receive state.But the main Problems existing of this traditional pulse modulated circuit has:
First is the existence due to transistor Mctrl conducting resistance, and pulse power amplifier exists extra pressure drop and loss.As shown in Figure 1, the node voltage V of circuit
dD1voltage amplitude comparatively supply voltage V
dDdecline a lot, particularly power supply Injection Current I
dtime larger.And voltage V
dD1directly can affect the size of power output.
Second is that power amplifier circuit exists DC bias circuit.Traditional pulse power amplifier generally all ignores the control to biasing circuit, there is extra loss.
3rd is to obtain high delivery efficiency, and power amplifier generally adopts E power-like amplifier structure.May be there is power output not in the E class power amplifier of single-stage, parasitic parameter is larger on Designing power amplifier impact.
4th is that drain electrode needs to use high frequency choke coil in E power-like amplifier circuit.High frequency choke coil generally adopts sheet external inductance to realize, and this will bring chip pin to increase, the problems such as application cost rising
Summary of the invention
The present invention is the deficiency in order to overcome pulse power amplifier of the prior art, proposes a kind of pulse power amplifier circuit adopting drain modulation mode.Pulse signal can be realized control power amplifier output under the prerequisite that there is not additional voltage drop and loss, there is higher power output and power added efficiency.
Summary of the invention
For realizing object of the present invention, the technical scheme adopted is as follows: a kind of pulse power amplifier adopting drain modulation mode, comprise pulse modulated circuit and power amplification circuit two circuit modules, the conducting of transistor and shutoff in pulse signal control impuls modulation circuit, thus control the operating state of power amplification circuit, it is characterized in that: part pulse modulated circuit being multiplexed with power amplification circuit, to solve in traditional pulse modulation circuit device the large pressure drop using single transistor to cause as control valve, thus cause the reduction of power output and efficiency; Comprise and there is centre tapped inductance L D, driving stage amplifying circuit, output stage amplifier circuit and be respectively biasing circuit 1 and the biasing circuit 2 that output stage amplifier circuit and driving stage amplifying circuit provide direct current biasing, radio-frequency differential input signal connects in-phase input end and the inverting input of driving stage amplifying circuit, radiofrequency signal after amplification is capacitively coupled to the input of output stage amplifier circuit by driving stage amplification circuit output end, final output stage amplifier circuit exports homophase and anti-phase two paths of differential signals, wherein:
Biasing circuit 1 comprises NMOS tube M1, M2, M3 and M4, resistance R2, R3, R7 and R8; The source ground of NMOS tube M1, the grid of NMOS tube M1 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M3, and NMOS tube M3 is as the control valve of biasing circuit 1, and its grid connects pulse control signal V
cTRL, one end of drain electrode contact resistance R3 of NMOS tube M3 and one end of resistance R8, the other end of resistance R3 connects one end of inductance L D, and inductance L D tap connects power vd D; Similarly, the source ground of NMOS tube M2, the grid of NMOS tube M2 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M4, and NMOS tube M4 is also as the control valve of biasing circuit 1, and its grid also connects pulse control signal V
cTRL, one end of drain electrode contact resistance R2 of NMOS tube M4 and one end of resistance R7, the other end of resistance R2 is connected with the other end of resistance R3;
Biasing circuit 2 comprises NMOS tube M5, M6, M7 and M8, resistance R1, R4, R5 and R6; The source class ground connection of NMOS tube M6, the grid of NMOS tube M6 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M8, and NMOS tube M8 is as the control valve of biasing circuit 2, and its grid connects pulse control signal V
cTRL, one end of drain electrode contact resistance R1 of NMOS tube M8 and one end of resistance R5, the other end of resistance R1 connects the other end of resistance R2 and R3 in biasing circuit 1; Similarly, the source ground of NMOS tube M5, the grid of NMOS tube M5 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M7, and NMOS tube M7 is also as the control valve of biasing circuit 2, and its grid also connects pulse control signal V
cTRL, one end of drain electrode contact resistance R4 of NMOS tube M7 and one end of resistance R6, the other end of the other end contact resistance R1 of resistance R4;
Driving stage amplifying circuit comprises NMOS tube M9, M10, M11 and M12, electric capacity C1, C2, C3 and C4; The source class ground connection of NMOS tube M9, the grid of NMOS tube M9 connects the other end of resistance R6 in one end of electric capacity C2 and biasing circuit 2, and the other end of electric capacity C2 connects radio frequency homophase differential input signal IN as the in-phase end of differential signal
r, the drain electrode of NMOS tube M9 and the source electrode of NMOS tube M11 link together formation cascodes, and NMOS tube M11 is as the control valve of driving stage amplifying circuit, and its grid meets pulse control signal V
cTRL, the drain electrode of NMOS tube M11 connects the other end of resistance R4 in one end of electric capacity C4 and biasing circuit 2, and the other end of electric capacity C4 connects the other end of resistance R8 in biasing circuit 1; Similarly, the source class ground connection of NMOS tube M10, the grid of NMOS tube M10 connects the other end of resistance R5 in one end of electric capacity C1 and biasing circuit 2, and the other end of electric capacity C1 connects the anti-phase differential input signal IN of radio frequency as the end of oppisite phase of differential signal
l, the drain electrode of NMOS tube M10 and the source electrode of NMOS tube M12 link together formation cascodes, and NMOS tube M12 is also as the control valve of driving stage amplifying circuit, and its grid also connects pulse control signal V
cTRLthe drain electrode of NMOS tube M12 connects one end of electric capacity C3 and the other end being connected inductance L D, inductance L D tap connects power vd D, and the other end of electric capacity C3 connects the other end of resistance R7 in biasing circuit 1, and NMOS tube M9 and M11 and NMOS tube M10 and M12 forms differential configuration;
Output stage amplifier circuit comprises NMOS tube M13, M14, M15 and M16, electric capacity C5, C6, C7, C8, C9 and C10, inductance L 1, L2, high frequency choke coil LRFC1 and LRFC2; The source class ground connection of NMOS tube M13, the grid of NMOS tube M13 connects the link of resistance R8 in electric capacity C4 and biasing circuit 1 in driving stage amplifying circuit, the drain electrode of NMOS tube M13 connects the link of electric capacity C6 and C8 and the source class of NMOS tube M15, NMOS tube M13 and M15 forms cascodes, NMOS tube M15 is as the control valve of output stage amplifier circuit, and its grid connects pulse control signal V
cTRL,the drain electrode of NMOS tube M15 connects the other end of one end of inductance L 1, one end of high frequency choke coil LRFC1 and electric capacity C8, the other end ground connection of electric capacity C6, the other end of high frequency choke coil LRFC1 connects power vd D, and the other end of inductance L 1 exports radio frequency homophase differential signal OUTR by electric capacity C10; Similarly, the source class ground connection of NMOS tube M14, the grid of NMOS tube M14 connects the link of resistance R7 in electric capacity C3 and biasing circuit 1 in driving stage amplifying circuit, the drain electrode of NMOS tube M14 connects the link of electric capacity C5 and C7 and the source class of NMOS tube M16, NMOS tube M14 and M16 forms cascodes, NMOS tube M16 is also as the control valve of output stage amplifier circuit, and its grid connects pulse control signal V
cTRL,the other end of one end of the drain electrode inductance L 2 of NMOS tube M16, one end of high frequency choke coil LRFC2 and electric capacity C7, the other end ground connection of electric capacity C5, the other end of high frequency choke coil LRFC2 connects power vd D, and the other end of inductance L 2 exports the anti-phase differential signal OUTL of radio frequency by electric capacity C9; NMOS tube M13 and M15 and NMOS tube M14 and M16 forms differential configuration, and the in-phase input end of output stage amplifier circuit is the grid of NMOS tube M13, and inverting input is the grid of NMOS tube M14.
For avoiding the chip pin owing to adopting sheet external inductance to bring to increase, high frequency choke coil LRFC1 and LRFC2 in foregoing circuit adopts bonding line on sheet to realize.
Advantage of the present invention and remarkable result:
(1) present invention employs the technology that metal-oxide-semiconductor is multiplexing, the common bank tube of the cascodes of driving stage amplifying circuit and output stage amplifier circuit is multiplexed with the control valve of pulse power amplifier circuit, efficiently solves in traditional pulse power amplifier circuit the large pressure drop that uses single transistor to cause as control valve thus cause the problem that power output and efficiency reduce.The present invention makes full use of common bank tube not to be needed as control valve additionally to increase pipe, does not produce extra pressure drop and loss.For biasing circuit 1 and biasing circuit 2, the structure of MOS diode and electric resistance partial pressure adds a control valve.By such design, when making pulse control signal be low level, turn off biasing circuit 1, biasing circuit 2, driving stage amplifying circuit, output stage amplifier circuit simultaneously, greatly reduce the power loss of pulse power amplifier.
(2) the driving stage circuit of pulse power amplifier and output-stage circuit all adopt cascodes, isolation is good, and utilization is total to bank tube as pulse signal control valve, save the quantity of transistor and do not produce extra pressure drop, effectively solving in traditional pulse power amplifier circuit owing to there is the problem of power loss that independent pulse modulator brings and additional voltage drop.
(3) a kind of impulse control scheme is devised.As can be seen from complete pulse power amplifier circuit, pulse signal carries out Synchronization Control to driving stage circuit, output-stage circuit and biasing circuit.When pulse signal is low level, turn off driving stage circuit, output-stage circuit and biasing circuit simultaneously, reduce power consumption, solve the problem of biasing circuit power loss in traditional circuit unit.
(4) high frequency choke coil LRFC1 and LRFC2 adopts bonding line to realize, to obtain high q-factor and good high frequency performance.In order to obtain high delivery efficiency, power amplifier generally adopts E power-like amplifier structure.In E power-like amplifier circuit, drain electrode needs to use high frequency choke coil, and traditional design medium-high frequency choke generally adopts sheet external inductance to realize.In the present invention, high frequency choke coil adopts bonding line on sheet to realize, and the chip pin avoided owing to adopting sheet external inductance to bring increases, the problems such as application cost rising.
Accompanying drawing illustrates:
Fig. 1 is the pulse power amplifier block diagram of traditional drains modulation system;
Fig. 2 is the block diagram of pulse power amplifier of the present invention;
Fig. 3 is the schematic diagram of pulse power amplifier of the present invention.
Embodiment
Referring to Fig. 2, the present invention is provided with biasing circuit 1, biasing circuit 2, driving stage amplifying circuit and output stage amplifier circuit.Radio frequency homophase differential input signal INR and rp input signal INL is connected on in-phase input end and the inverting input of driving stage amplifying circuit respectively.The output of driving stage amplifying circuit is connected on the input of output stage amplifier circuit, and it is OUTR and OUTL that the output of output stage amplifier circuit exports the differential radio frequency output signal after two-stage is amplified.Biasing circuit 1 is connected on for it provides static direct current to be biased on output stage amplifier circuit, and biasing circuit 2 is connected on driving stage amplifier circuit as it provides static direct current to be biased.Pulse control signal V
cTRLbe added in control biasing circuit 1, biasing circuit 2, driving stage amplifying circuit and output stage amplifier circuit realizing paired pulses power amplification circuit operating state by pulse modulator simultaneously.
Referring to Fig. 3, biasing circuit 1 and biasing circuit 2 are by NMOS diode and resistance composition.The grid drain electrode of the NMOS tube M1 of biasing circuit 1, M2 is connected together respectively and forms MOS diode, realizes dividing potential drop respectively by series connection control valve M3 and M4 and resistance R3 and R2.DC offset voltage is added in the grid of cascodes common source pipe M13 and the M14 of output stage amplifier circuit respectively by resistance R8 and R7, for common source pipe provides direct current biasing.The NMOS tube M5 of biasing circuit 2 and M6 grid drain electrode are connected together respectively and form MOS diode, realize dividing potential drop respectively by series connection control valve M7 and M8 and resistance R4 and R1.DC offset voltage is added in the grid of cascodes common source pipe M9 and the M10 of driving stage amplifier circuit respectively by resistance R6 and R5, for common source pipe provides direct current biasing.Driving stage amplifying circuit is made up of NMOS tube and electric capacity, inductance.Adopt cascodes, improve isolation and voltage endurance capability.Differential radio frequency input signal is added in in-phase input end and the inverting input of driving stage amplifier circuit unit respectively.Driving stage amplified current is a kind of nonlinear amplifier.The equivalent capacity that its load is total to bank tube M11 and M12 drain electrode place by inductance L D and cascodes is formed, and the two resonance is in operating frequency.Therefore the AC load of this driving stage amplifying circuit is very large, thus less input radio frequency signal can be amplified to the higher AC signal of Amplitude Ratio by driving stage amplifier circuit.The grid of common bank tube M11 and the M12 of cascodes connects control signal, as the control valve of driving stage amplifying circuit, realizes the control to driving stage amplifying circuit.Output signal sends into the input of output stage amplifier circuit after electric capacity C4 and C3 elimination direct current.Output stage amplifier circuit is made up of NMOS tube, electric capacity, inductance, adopts cascodes.The grid of common bank tube M15 and the M16 of cascodes connects control signal, as the control valve of output stage amplifier circuit, realizes the control to output stage amplifier circuit.Output stage amplifier circuit is operated in E class operating state, has high power output and power added efficiency.The difference radio-frequency signal amplified through driving stage amplifier circuit is added in the input of output stage amplifier circuit.The output of output stage amplifier exports homophase and anti-phase two paths of differential signals.Whole output stage amplifier circuit adopts capacitance partial pressure mode being assigned to drain voltage equilibrium common source pipe M13 and M14 and being total to bank tube M15 and M16, thus farthest reduces the breakdown risk of transistor.
As shown in Fig. 2, Fig. 3, the pulse modulator of pulse power amplifier design of the present invention is multiplexed with a part for power amplifier.Compared with traditional circuit, one of innovative point of the design is the control valve of pulse modulator to be multiplexed in power amplifier circuit, efficiently solves in traditional pulse power amplifier circuit the large pressure drop that uses single transistor to cause as control valve thus causes the problem that power output and efficiency reduce.The common bank tube making full use of cascodes in the design does not need as control valve additionally to increase pipe, does not produce extra pressure drop and loss.For biasing circuit 1 and biasing circuit 2, the structure of MOS diode and electric resistance partial pressure adds a control valve.By such design, when making pulse control signal be low level, turn off biasing circuit 1, biasing circuit 2, driving stage amplifying circuit, output stage amplifier circuit simultaneously, greatly reduce the power loss of pulse power amplifier.
The present invention, under the requirement meeting power output and power added efficiency, has advantages such as affecting little, saving transistor by parasitic parameter.Pulse control signal is added in biasing circuit 1 simultaneously, biasing circuit 2, the control valve of driving stage amplifying circuit and output stage amplifier circuit realizes the working state control of paired pulses power amplifier.Driving stage amplifying circuit and output stage amplifier circuit all adopt cascodes to increase isolation, all adopt differential configuration to effectively reduce the impact of parasitic parameter paired pulses power amplifier circuit simultaneously.Input signal is added in the input of driving stage amplifying circuit, radiofrequency signal after amplification is capacitively coupled to the input of output stage amplifier circuit by driving stage amplification circuit output end, and final output stage amplifier circuit exports the homophase after amplifying and anti-phase two paths of differential signals.
Claims (2)
1. one kind adopts the pulse power amplifier of drain modulation mode, comprise pulse modulated circuit and power amplification circuit two circuit modules, the conducting of transistor and shutoff in pulse signal control impuls modulation circuit, thus control the operating state of power amplification circuit, it is characterized in that: part pulse modulated circuit being multiplexed with power amplification circuit, to solve in traditional pulse modulation circuit device the large pressure drop using single transistor to cause as control valve, thus cause the reduction of power output and efficiency; Comprise and there is centre tapped inductance L D, driving stage amplifying circuit, output stage amplifier circuit and be respectively biasing circuit 1 and the biasing circuit 2 that output stage amplifier circuit and driving stage amplifying circuit provide direct current biasing, radio-frequency differential input signal connects in-phase input end and the inverting input of driving stage amplifying circuit, radiofrequency signal after amplification is capacitively coupled to the input of output stage amplifier circuit by driving stage amplification circuit output end, final output stage amplifier circuit exports homophase and anti-phase two paths of differential signals, wherein:
Biasing circuit 1 comprises NMOS tube M1, M2, M3 and M4, resistance R2, R3, R7 and R8; The source ground of NMOS tube M1, the grid of NMOS tube M1 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M3, and NMOS tube M3 is as the control valve of biasing circuit 1, and its grid connects pulse control signal V
cTRL, one end of drain electrode contact resistance R3 of NMOS tube M3 and one end of resistance R8, the other end of resistance R3 connects one end of inductance L D, and inductance L D tap connects power vd D; Similarly, the source ground of NMOS tube M2, the grid of NMOS tube M2 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M4, and NMOS tube M4 is also as the control valve of biasing circuit 1, and its grid also connects pulse control signal V
cTRL, one end of drain electrode contact resistance R2 of NMOS tube M4 and one end of resistance R7, the other end of resistance R2 is connected with the other end of resistance R3;
Biasing circuit 2 comprises NMOS tube M5, M6, M7 and M8, resistance R1, R4, R5 and R6; The source class ground connection of NMOS tube M6, the grid of NMOS tube M6 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M8, and NMOS tube M8 is as the control valve of biasing circuit 2, and its grid connects pulse control signal V
cTRL, one end of drain electrode contact resistance R1 of NMOS tube M8 and one end of resistance R5, the other end of resistance R1 connects the other end of resistance R2 and R3 in biasing circuit 1; Similarly, the source ground of NMOS tube M5, the grid of NMOS tube M5 links together with drain electrode and forms MOS diode and be connected with the source electrode of NMOS tube M7, and NMOS tube M7 is also as the control valve of biasing circuit 2, and its grid also connects pulse control signal V
cTRL, one end of drain electrode contact resistance R4 of NMOS tube M7 and one end of resistance R6, the other end of the other end contact resistance R1 of resistance R4;
Driving stage amplifying circuit comprises NMOS tube M9, M10, M11 and M12, electric capacity C1, C2, C3 and C4; The source class ground connection of NMOS tube M9, the grid of NMOS tube M9 connects the other end of resistance R6 in one end of electric capacity C2 and biasing circuit 2, and the other end of electric capacity C2 connects radio frequency homophase differential input signal IN as the in-phase end of differential signal
r, the drain electrode of NMOS tube M9 and the source electrode of NMOS tube M11 link together formation cascodes, and NMOS tube M11 is as the control valve of driving stage amplifying circuit, and its grid meets pulse control signal V
cTRL, the drain electrode of NMOS tube M11 connects the other end of resistance R4 in one end of electric capacity C4 and biasing circuit 2, and the other end of electric capacity C4 connects the other end of resistance R8 in biasing circuit 1; Similarly, the source class ground connection of NMOS tube M10, the grid of NMOS tube M10 connects the other end of resistance R5 in one end of electric capacity C1 and biasing circuit 2, and the other end of electric capacity C1 connects the anti-phase differential input signal IN of radio frequency as the end of oppisite phase of differential signal
l, the drain electrode of NMOS tube M10 and the source electrode of NMOS tube M12 link together formation cascodes, and NMOS tube M12 is also as the control valve of driving stage amplifying circuit, and its grid also connects pulse control signal V
cTRLthe drain electrode of NMOS tube M12 connects one end of electric capacity C3 and the other end being connected inductance L D, inductance L D tap connects power vd D, and the other end of electric capacity C3 connects the other end of resistance R7 in biasing circuit 1, and NMOS tube M9 and M11 and NMOS tube M10 and M12 forms differential configuration;
Output stage amplifier circuit comprises NMOS tube M13, M14, M15 and M16, electric capacity C5, C6, C7, C8, C9 and C10, inductance L 1, L2, high frequency choke coil LRFC1 and LRFC2; The source class ground connection of NMOS tube M13, the grid of NMOS tube M13 connects the link of resistance R8 in electric capacity C4 and biasing circuit 1 in driving stage amplifying circuit, the drain electrode of NMOS tube M13 connects the link of electric capacity C6 and C8 and the source class of NMOS tube M15, NMOS tube M13 and M15 forms cascodes, NMOS tube M15 is as the control valve of output stage amplifier circuit, and its grid connects pulse control signal V
cTRLthe drain electrode of NMOS tube M15 connects the other end of one end of inductance L 1, one end of high frequency choke coil LRFC1 and electric capacity C8, the other end ground connection of electric capacity C6, the other end of high frequency choke coil LRFC1 connects power vd D, and the other end of inductance L 1 exports radio frequency homophase differential signal OUTR by electric capacity C10; Similarly, the source class ground connection of NMOS tube M14, the grid of NMOS tube M14 connects the link of resistance R7 in electric capacity C3 and biasing circuit 1 in driving stage amplifying circuit, the drain electrode of NMOS tube M14 connects the link of electric capacity C5 and C7 and the source class of NMOS tube M16, NMOS tube M14 and M16 forms cascodes, NMOS tube M16 is also as the control valve of output stage amplifier circuit, and its grid connects pulse control signal V
cTRLthe other end of one end of the drain electrode inductance L 2 of NMOS tube M16, one end of high frequency choke coil LRFC2 and electric capacity C7, the other end ground connection of electric capacity C5, the other end of high frequency choke coil LRFC2 connects power vd D, and the other end of inductance L 2 exports the anti-phase differential signal OUTL of radio frequency by electric capacity C9; NMOS tube M13 and M15 and NMOS tube M14 and M16 forms differential configuration, and the in-phase input end of output stage amplifier circuit is the grid of NMOS tube M13, and inverting input is the grid of NMOS tube M14.
2. the pulse power amplifier of employing drain modulation mode according to claim 1, is characterized in that: for avoiding the chip pin owing to adopting sheet external inductance to bring to increase, and high frequency choke coil LRFC1 and LRFC2 adopts bonding line on sheet to realize.
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| Publication number | Publication date |
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| CN104917466B (en) | 2017-08-11 |
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