CN104916771A - Substrate-replaced normally-mounted GaN-based light-emitting diode chip and preparation method thereof - Google Patents
Substrate-replaced normally-mounted GaN-based light-emitting diode chip and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 28
- 229910052594 sapphire Inorganic materials 0.000 claims description 21
- 239000010980 sapphire Substances 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910017750 AgSn Inorganic materials 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000012634 fragment Substances 0.000 abstract description 3
- 239000010931 gold Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 241001062009 Indigofera Species 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006664 bond formation reaction Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000004038 photonic crystal Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Led Devices (AREA)
Abstract
The invention provides a substrate-replaced normally-mounted GaN-based light-emitting diode chip which comprises a high-thermal-conductivity substrate, a solder layer, a GaN buffer layer, an n-type GaN layer, a quantum well layer, a p-type GaN layer and a transparent conductive film layer which are arranged from the bottom up, or the high-thermal-conductivity substrate, the solder layer, a metal reflection layer, the GaN buffer layer, the n-type GaN layer, the quantum well layer, the p-type GaN layer and the transparent conductive film layer which are arranged from the bottom up. The transparent conductive film layer and the n-type GaN layer are provided with a p electrode and an n electrode respectively; and the exposed upper surface of the transparent conductive film layer and the exposed upper surface of the n-type GaN layer as well as the marginal areas of the p and n electrodes are respectively provided with a passivation layer. The substrate-replaced normally-mounted GaN-based light-emitting diode chip is good in heat dissipation performance, high in luminous efficiency and long in service life; and the utilization of a temporary substrate reduces fragment rate in the production process and improves output capacity.
Description
Technical field
The present invention relates to formal dress GaN base light-emitting diode at the bottom of a kind of rebush and preparation method thereof, belong to photoelectron technical field.
Background technology
In recent years, light-emitting diode (LED) becomes one of the most valued light source technology gradually.LED has the little feature of volume on the one hand; LED possesses the electricity-saving characteristic of low current, low voltage drive on the other hand; It also has sound construction, shock resistance and shock resistance by force simultaneously, the many merits such as extra long life.Wherein, as one of the main application of optoelectronic areas, GaN base material obtains the concern of more and more people, utilizes GaN base semi-conducting material can produce super brightness indigo plant, green, white light emitting diode.How LED-based important function, improve the luminous power of high-power GaN base blue LED die and the focus having become concern of dispelling the heat.
Along with the development of growth technology and multi-quantum pit structure, the internal quantum efficiency of superhigh brightness LED there has been very large improvement, and the internal quantum efficiency of current blue light GaN base LED reaches 90%.Along with the development of the technology such as growth distribution Bragg reflecting layer (DBR) structure, surface coarsening and photonic crystal, the external quantum efficiency of blue light GaN base LED have also been obtained very large lifting.Heat dissipation problem becomes the technical barrier that high-power GaN base blue LED die needs emphasis to solve, and the quality of radiating effect is directly connected to life-span and the energy-saving effect of LED.LED band-to-band transition producing light, does not contain infrared part in its spectrum, so the heat of LED can not distribute by radiation by electronics.If the heat in LED chip can not distribute in time, the aging of device can be accelerated.Once the temperature of LED exceedes most high-critical temperature (with according to not homepitaxy and technique, chip temperature is probably 150 DEG C), often cause LED eventual failure.
Effectively solve the heat dissipation problem of LED chip, to the reliability and life-span improving high-power GaN base blue LED die, there is important function.Accomplish this point, the most direct method sheds from knot by heat outward no more than providing a good passage of heat.Technical in extension, compared with the sapphire (conductive coefficient is about 20W/mK) of poor thermal conductivity, SiC substrate (conductive coefficient is about 490W/mK) and Si substrate (conductive coefficient is about 150W/mK) well have very large advantage because of heat conductivility.In the rank of chip, with the positive assembling structure of tradition using Sapphire Substrate as heat dissipation channel compared with, vertical and upside-down mounting welding core structure has preferably heat-sinking capability.Thin-film LED directly adopts copper alloy as substrate, effectively improves the heat-sinking capability of chip.Flip chip bonding (Flip-Chip) technology is welded LED chip upside-down mounting on the silicon substrate with more high thermal conductivity by eutectic, au bump between chip and substrate and silicon substrate improve the heat-sinking capability of LED chip simultaneously, ensure that the heat of LED can be derived fast from chip.
Chinese patent CN100499189C discloses the preparation method of the alloy bonding LED flip-chip of a kind of proof gold AU, this patent carries out face-down bonding formation high power LED flip-chip by P-N electrode epitaxial wafer with the silicon substrate in reflector by filling proof gold and the pure heating bonding of other alloy, the heat that LED is produced reduces, and improves the reliability of chip.But the method need carry out particular design, complex process to chip P-N electrode and silicon substrate figure.
Chinese patent CN101919610A discloses and the present invention relates to a kind of large-power forward LED chip structure, this large-power forward LED chip described in invention, by adopting the combination of heat conducting base and DBR optical reflectance coating, solves high-power LED chip in little the run into heat radiation of high current density and the problem improving light extraction efficiency.In the invention, need to reducing thin of sapphire substrate to less than 50 microns, badly influence the fragment rate of the work steps such as follow-up cleaning, DBR plated film, bonding on the one hand, the remaining Sapphire Substrate of another side still has influence on the heat-sinking capability of LED chip.
Chinese patent CN101465401B discloses a kind of method for preparing film GaN LED based on plane bonding and temporality substrate transfer technology, by the mode of separative element device again on first plane bonding to support base, namely first realize GaN LED to engage with the gapless of support base, realize the absolute separation between each unit GaN LED component again, with the extension of the generation and crack that reduce laser lift-off process crack, after laser lift-off, chip manufacturing is carried out by temporary substrate, ensure that large-area laser is peeled off and remove the high finished product rate that Sapphire Substrate manufactures film GaN LED.But the method by P type GaN layer bonding on a si substrate, therefore can cause in processing procedure that chip voltage is high, electric leakage etc.
In sum, although the heat conductivility of SiC substrate is fine, due to its high cost, make the production cost of device very high; Although Si substrate cost is very low, because GaN epitaxial layer and Si crystal exist larger lattice mismatch, makes epitaxial loayer occur a large amount of dislocations, affect the parameter of chip.Vertical and upside-down mounting welding core structure also there is complex process and yield is low waits deficiency.
Summary of the invention
For the deficiencies in the prior art, the invention provides the formal dress GaN base light-emitting diode at the bottom of a kind of rebush, this invention substrate used cost is low, heat conduction good, has that technique is simple, yield advantages of higher.
The present invention also provides a kind of preparation method of above-mentioned light-emitting diode.
Terminological interpretation:
ITO:Indium Tin Oxide, tin indium oxide is a kind of transparent conductive film;
PECVD:Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition.
Technical scheme of the present invention is as follows:
According to the present invention, one of preferred version:
A formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, comprises the high thermal conductive substrate, solder layer, GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer and the transparent conductive film layer that from bottom to top arrange; Described transparent conductive film layer and n-type GaN layer are respectively arranged with p-electrode, n-electrode; Passivation layer is provided with at the exposed upper surface of described transparent conductive film layer and the exposed upper surface of n-type GaN layer and p, n-electrode fringe region.
According to the present invention, one of preferred version:
A formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, comprises the high thermal conductive substrate, solder layer, metallic reflector, GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer and the transparent conductive film layer that from bottom to top arrange; Described transparent conductive film layer and n-type GaN layer are respectively arranged with p-electrode, n-electrode; Passivation layer is provided with at the exposed upper surface of described transparent conductive film layer and the exposed upper surface of n-type GaN layer and metal electrode fringe region.
Described high thermal conductive substrate is silicon, copper, aluminium or copper alloy;
Described transparent conductive film layer is ito thin film;
Described metallic reflector is Ni/Pt/Au or Rh/W/Au/W.
A preparation method for formal dress GaN base light-emitting diode chip for backlight unit at the bottom of above-mentioned rebush, comprises step as follows:
(1) growing GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer successively on a sapphire substrate;
(2) utilize existing ICP dry etching method, the p-type GaN layer along GaN base epitaxial wafer etches mesa structure to n-type GaN layer, after completing etching, to remove photoresist cleaning to GaN base epitaxial wafer;
(3) at surface deposition one deck ITO nesa coating of described p-type GaN layer as current extending, then on described current extending, carry out photoetching, only retain ITO nesa coating corresponding in p-type GaN layer;
(4) on described ITO transparent conductive film layer and n-type GaN layer, prepare p-electrode and n-electrode respectively, described p-electrode and n-electrode material are all Cr/Pt/Au;
(5) chip surface completed in described step (4) uses the method silicon oxide film of PECVD as passivation layer;
(6) wafer after completing described step (5), through photoetching, etching process, erodes the passivation layer film on p-electrode and n-electrode surface, as shown in Figure 1;
(7) apply one deck photoresist above the wafer completed in described step (6), wafer and temporary base are bonded together, as shown in Figure 2;
(8) the former Sapphire Substrate of the wafer adopting the method for laser lift-off will complete through step (7) is removed;
(9) surface deposition one deck solder of substrate is removed in step (8), as shown in Figure 3; Wafer and high thermal conductive substrate are bonded together, as shown in Figure 4; Or,
Remove the surface deposition layer of metal reflector of substrate in step (8), then deposit one deck solder, wafer and high thermal conductive substrate are bonded together, as shown in Figure 6;
(10) remove the temporary base of above-mentioned wafer, cleaning of then removing photoresist, obtains structure shown in Fig. 5 or Fig. 7;
(11) above-mentioned wafer is drawn split and obtain a grain chip.
Preferred according to the present invention, in described step (7), temporary base is Sapphire Substrate, glass or quartz.
Preferred according to the present invention, in described step (9), solder is AuSn, AuIn or AgSn.
Preferred according to the present invention, in described step (9), bonding temperature is 250-300 DEG C, and pressure 0.3-0.6MPa, pressing time is 3-6 minute.
Not elaborate in technique scheme of the present invention and to limit, all with reference to the prior art that light-emitting diode makes.
Beneficial effect of the present invention:
1, in GaN base LED structure of the present invention, due to Sapphire Substrate is changed to high thermal conductive substrate, therefore gained LED chip luminous efficiency is high, and the life-span is long.At normal temperatures, 45mil great power LED can realize 350mA electric current lower 5000 hours bad lights, and luminous efficiency can reach 140-160lm/W.
2, of the present inventionly substrate approach is changed, owing to not changing the electrode of chip, therefore low than voltage that is vertical and upside-down mounting welding core structure.
3, of the present inventionly change substrate approach, the material needed for use common LED can complete, and therefore technique is simple, and cost is low.
4, the use of temporary base of the present invention, reduces the fragment rate in production process, improves output capacity.
Accompanying drawing explanation
Fig. 1 is common GaN base LED structure schematic diagram.
Fig. 2 is the structural representation after temporary base and LED wafer being bonded.
Fig. 3 peels off the structural representation after Sapphire Substrate with the LED wafer of temporary base.
Fig. 4 is by high thermal conductive substrate and with the structural representation after the LED wafer bonding of temporary base.
Fig. 5 is the LED schematic diagram after removing temporary base.
Fig. 6 is by high thermal conductive substrate and with the structural representation after the wafer bonding of reflective metal layer.
Fig. 7 is the LED structure schematic diagram with metallic reflector after removing temporary base.
In figure, 1, Sapphire Substrate, 2, GaN resilient coating, 3, n-type GaN layer, 4, quantum well layer, 5, p-type GaN layer, 6, transparent conductive film layer, 7, p-electrode, 8, n-electrode, 9, passivation layer, 10, temporary base, 11, photoresist, 12, solder layer, 13, high thermal conductive substrate, 14, metallic reflector.
Embodiment
Below in conjunction with Figure of description, by specific embodiment, the present invention will be further described, and the example provided is preferred embodiment of the present invention, but is not limited thereto.
Embodiment 1, prepare the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush of silicon high thermal conductive substrate
A formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, as shown in Figure 5, comprises the high thermal conductive substrate silicon 13, solder layer AuSn 12, GaN resilient coating 2, n-type GaN layer 3, quantum well layer 4, p-type GaN layer 5 and the ITO transparent conductive film layer 6 that from bottom to top arrange; P-electrode Cr/Pt/Au 7, n-electrode Cr/Pt/Au 8 is respectively arranged with transparent the leading in film electric layer 6 and n-type GaN layer of described ITO; Passivation layer 9 is provided with at the exposed upper surface of described ITO transparency conducting layer and the exposed upper surface of n-type GaN layer 3 and p, n-electrode fringe region.
Preparation method's step is as follows:
(1) growing GaN resilient coating 2, n-type GaN layer 3, quantum well layer 4, p-type GaN layer 5 successively in Sapphire Substrate 1;
(2) utilize existing ICP dry etching method, the p-type GaN layer 5 along GaN base epitaxial wafer etches mesa structure to n-type GaN layer 3, after completing etching, to remove photoresist cleaning to GaN base epitaxial wafer;
(3) at surface deposition one deck ITO nesa coating 6 of described p-type GaN layer 5 as current extending, then on described current extending, carry out photoetching, only retain ITO nesa coating 6 corresponding in p-type GaN layer 5;
(4) on described ITO transparent conductive film layer 6 and n-type GaN layer 3, prepare p-electrode 7 and n-electrode 8 respectively, described p-electrode and n-electrode material are all Cr/Pt/Au;
(5) chip surface completed in described step (4) uses the method silicon oxide film of PECVD as passivation layer 9;
(6) wafer after completing described step (5), through photoetching, etching process, erodes the passivation layer film 9 on p-electrode 7 and n-electrode 8 surface, as shown in Figure 1;
(7) apply one deck photoresist above the wafer completed in described step (6), wafer and temporary base Sapphire Substrate 10 are bonded together, as shown in Figure 2;
(8) method of laser lift-off is adopted the former Sapphire Substrate 1 of the wafer completed through step (7) to be removed;
(9) surface deposition one deck solder layer AuSn12 of substrate is removed in step (8), as shown in Figure 3; Bonding temperature 300 DEG C, under pressure 0.5MPa condition, pressurize and wafer and high thermal conductive substrate silicon 13 were bonded together in 4 minutes, as shown in Figure 4;
(10) remove the temporary base Sapphire Substrate 10 of above-mentioned wafer, cleaning of then removing photoresist, obtains structure shown in Fig. 5;
(11) above-mentioned wafer is drawn split and obtain a grain chip.
Embodiment 2, prepare the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush of copper high thermal conductive substrate
A formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, comprises the high thermal conductive substrate copper 13, solder layer AuIn12, metallic reflector Ni/Pt/Au14, GaN resilient coating 2, n-type GaN layer 3, quantum well layer 4, p-type GaN layer 5 and the transparent conductive film layer 6 that from bottom to top arrange; Described transparent conductive film layer 6 and n-type GaN layer 3 are respectively arranged with p-electrode 7Cr/Pt/Au, n-electrode 8Cr/Pt/Au; Passivation layer 9 is provided with at the exposed upper surface of described transparent conductive film layer 6 and the exposed upper surface of n-type GaN layer 3 and p, n-electrode fringe region.
Preparation method's step is as follows:
(1) growing GaN resilient coating 2, n-type GaN layer 3, quantum well layer 4, p-type GaN layer 5 successively in Sapphire Substrate 1;
(2) utilize existing ICP dry etching method, the p-type GaN layer 5 along GaN base epitaxial wafer etches mesa structure to n-type GaN layer 3, after completing etching, to remove photoresist cleaning to GaN base epitaxial wafer;
(3) at surface deposition one deck ITO nesa coating 6 of described p-type GaN layer 5 as current extending, then on described current extending, carry out photoetching, only retain ITO nesa coating 6 corresponding in p-type GaN layer 5;
(4) on described ITO transparent conductive film layer 6 and n-type GaN layer 3, prepare p-electrode 7 and n-electrode 8 respectively, described p-electrode and n-electrode material are all Cr/Pt/Au;
(5) chip surface completed in described step (4) uses the method silicon oxide film of PECVD as passivation layer 9;
(6) wafer after completing described step (5), through photoetching, etching process, erodes the passivation layer film 9 on p-electrode 7 and n-electrode 8 surface, as shown in Figure 1;
(7) apply one deck photoresist above the wafer completed in described step (6), wafer and temporary base quartz substrate 10 are bonded together, as shown in Figure 2;
(8) method of laser lift-off is adopted the former Sapphire Substrate 1 of the wafer completed through step (7) to be removed;
(9) the surface deposition layer of metal reflector Ni/Pt/Au14 of substrate is removed in step (8), deposit one deck solder AuIn12 again, bonding temperature 250 DEG C, under pressure 0.3MPa condition, pressurize and wafer and high thermal conductive substrate copper 13 were bonded together in 3 minutes, as shown in Figure 6;
(10) remove the temporary base Sapphire Substrate 10 of above-mentioned wafer, cleaning of then removing photoresist, obtains structure shown in Fig. 7;
(11) above-mentioned wafer is drawn split and obtain a grain chip.
Embodiment 3, prepare the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush of aluminium high thermal conductive substrate
The formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as described in Example 1, its difference is,
Described high thermal conductive substrate 13 is aluminium, and solder layer 12 is AgSn.
As described in Example 1, its difference is preparation method,
In described step (9), remove surface deposition one deck solder layer AgSn12 of substrate in step (8), as shown in Figure 3; Bonding temperature 280 DEG C, under pressure 0.6MPa condition, pressurize and wafer and high thermal conductive substrate aluminium 13 were bonded together in 4 minutes, as shown in Figure 4.
Embodiment 4, prepare the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush of copper alloy high thermal conductive substrate
The formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as described in Example 2, its difference is,
Described high thermal conductive substrate 13 is copper alloy.
As described in Example 2, its difference is preparation method,
In described step (9), the surface deposition layer of metal reflector Rh/W/Au/W14 of substrate is removed in step (8), deposit one deck solder AuIn12 again, bonding temperature 250 DEG C, under pressure 0.3MPa condition, pressurize and wafer and high thermal conductive substrate copper alloy 13 were bonded together in 6 minutes, as shown in Figure 6.
Claims (9)
1. the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, is characterized in that, comprises the high thermal conductive substrate, solder layer, GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer and the transparent conductive film layer that from bottom to top arrange; Described transparent conductive film layer and n-type GaN layer are respectively arranged with p-electrode, n-electrode; Passivation layer is provided with at the exposed upper surface of described transparent conductive film layer and the exposed upper surface of n-type GaN layer and p, n-electrode fringe region.
2. the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of rebush, comprises the high thermal conductive substrate, solder layer, metallic reflector, GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer and the transparent conductive film layer that from bottom to top arrange; Described transparent conductive film layer and n-type GaN layer are respectively arranged with p-electrode, n-electrode; Passivation layer is provided with at the exposed upper surface of described transparent conductive film layer and the exposed upper surface of n-type GaN layer and metal electrode fringe region.
3. the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as claimed in claim 1 or 2, is characterized in that, described high thermal conductive substrate is silicon, copper, aluminium or copper alloy.
4. the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as claimed in claim 1 or 2, is characterized in that, described transparent conductive film layer is ito thin film.
5. the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as claimed in claim 1 or 2, is characterized in that, described metallic reflector is Ni/Pt/Au or Rh/W/Au/W.
6. the preparation method of the formal dress GaN base light-emitting diode chip for backlight unit at the bottom of a kind of rebush as described in any one of claim 1-5, comprises step as follows:
(1) growing GaN resilient coating, n-type GaN layer, quantum well layer, p-type GaN layer successively on a sapphire substrate;
(2) utilize existing ICP dry etching method, the p-type GaN layer along GaN base epitaxial wafer etches mesa structure to n-type GaN layer, after completing etching, to remove photoresist cleaning to GaN base epitaxial wafer;
(3) at surface deposition one deck ITO nesa coating of described p-type GaN layer as current extending, then on described current extending, carry out photoetching, only retain ITO nesa coating corresponding in p-type GaN layer;
(4) on described ITO transparent conductive film layer and n-type GaN layer, prepare p-electrode and n-electrode respectively, described p-electrode and n-electrode material are all Cr/Pt/Au;
(5) chip surface completed in described step (4) uses the method silicon oxide film of PECVD as passivation layer;
(6) wafer after completing described step (5), through photoetching, etching process, erodes the passivation layer film on p-electrode and n-electrode surface;
(7) apply one deck photoresist above the wafer completed in described step (6), wafer and temporary base are bonded together;
(8) the former Sapphire Substrate of the wafer adopting the method for laser lift-off will complete through step (7) is removed;
(9) remove surface deposition one deck solder of substrate in step (8), wafer and high thermal conductive substrate are bonded together; Or,
Remove the surface deposition layer of metal reflector solder of substrate in step (8), then deposit one deck solder, wafer and high thermal conductive substrate are bonded together;
(10) temporary base of above-mentioned wafer is removed, cleaning of then removing photoresist;
(11) above-mentioned wafer is drawn split and obtain a grain chip.
7. preparation method as claimed in claim 6, is characterized in that, in described step (7), temporary base is Sapphire Substrate, glass or quartz.
8. preparation method as claimed in claim 6, is characterized in that, in described step (9), solder is AuSn, AuIn or AgSn.
9. preparation method as claimed in claim 6, is characterized in that, in described step (9), bonding temperature is 250-300 DEG C, and pressure 0.3-0.6MPa, pressing time is 3-6 minute.
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