CN104916638B - One-time programming memory - Google Patents
One-time programming memory Download PDFInfo
- Publication number
- CN104916638B CN104916638B CN201410164447.2A CN201410164447A CN104916638B CN 104916638 B CN104916638 B CN 104916638B CN 201410164447 A CN201410164447 A CN 201410164447A CN 104916638 B CN104916638 B CN 104916638B
- Authority
- CN
- China
- Prior art keywords
- grid
- doped region
- memory cell
- type
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims abstract description 312
- 238000003860 storage Methods 0.000 claims abstract description 122
- 239000000758 substrate Substances 0.000 claims description 46
- 239000000725 suspension Substances 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 42
- 229920005591 polysilicon Polymers 0.000 description 14
- 238000002955 isolation Methods 0.000 description 12
- 101001128819 Tityus serrulatus Bradykinin-potentiating peptide T Proteins 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000001427 coherent effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 101001008616 Tityus serrulatus Potassium channel toxin epsilon-KTx 1.1 Proteins 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A one-time programmable memory includes a first memory cell and a second memory cell. The first memory cell includes a first storage transistor, and the second memory cell includes a second storage transistor. The distance between the gate structure in the first storage transistor and the gate structure in the second storage transistor is short, and the spacers thereof overlap each other. Thus, a high-capacity one-time-programming memory can be manufactured.
Description
Technical field
The present invention relates to a kind of memory, and more particularly to one-time programming memory.
Background technology
It is well known that non-volatility memorizer can still preserve its data content after power is turned off.In general, when non-
After volatile storage manufacture is completed and dispatched from the factory, user can program (program) non-volatility memorizer, and then will money
Material is recorded in non-volatility memorizer.And according to the number of programming, non-volatility memorizer can be further discriminated between repeatedly to compile
Journey memory (multi-time programming memory, abbreviation MTP memory), or one-time programming memory (one
Time programming memory, abbreviation otp memory).
Substantially, user can carry out the multiple modification that stores data to MTP memories.On the contrary, user only may be used
To program an otp memory.After once otp memory programming is completed, its data stored will be unable to change.
It refer to 1A figures with 1B to scheme, its depicted memory cell and its schematic equivalent circuit for otp memory.The
1A schemes to include two memory cells 110,120 with 1B figures, has two transistors in each memory cell 110,120, can be described as
2T memory cells.
As shown in figure 1A figures, p-type substrate (P-sub) 100 is divided into two using shallow slot isolation structure (STI) 130
Individual part is to define the region of two memory cells 110,120.In the first memory cell 110, two N doped regions 111,112
Between the surface of p-type substrate 100 on there is first grid structure 113, it includes a grid oxic horizon (gate oxide
Layer), polycrystalline silicon gate layer (poly gate layer) and clearance wall (spacer).Furthermore N doped regions 112 with it is shallow
There is second grid structure 114 on the surface of p-type substrate 100 between channel isolating structure (STI) 130.Furthermore N doped regions
111 are connected to bit line BL0, first grid structure 113 is connected to word-line WL0, second grid structure 114 is connected to control line
CL0。
Similarly, in the second memory cell 120, have on the surface of p-type substrate 100 between two N doped regions 121,122
First grid structure 123.Furthermore the surface of p-type substrate 100 between N doped regions 122 and shallow slot isolation structure (STI) 130
It is upper that there is second grid structure 124.Furthermore N doped regions 121 are connected to bit line BL1, first grid structure 123 is connected to
Word-line WL1, second grid structure 124 are connected to control line CL1.
As shown in Figure 1B, the first memory cell 110 includes an a switching transistor T01 and storage transistor T00, opens
Close transistor T01 grids and be connected to word-line WL0, its first source/drain terminal (drain/source terminal) is connected to bit
Line BL0；Storage transistor T00 grids are connected to control line CL0, and its first source/drain terminal is connected to the second of switching transistor T01
Source/drain terminal, its second source/drain terminal are suspension joint (floating).
Similarly, the second memory cell 120 includes an a switching transistor T11 and storage transistor T10, switching transistor
T11 grids are connected to word-line WL1, and its first source/drain terminal is connected to bit line BL1；Storage transistor T10 grids are connected to control
Line CL1 processed, its first source/drain terminal are connected to switching transistor T11 the second source/drain terminal, and its second source/drain terminal is suspension joint.
For example, when the first memory cell 110 is programmed, there is provided 0V signals to bit line BL0,3.3V signal to word-line
WL0,6.5V signal are to control line CL0.Then switching transistor T01 opens (turnon), and causes storage transistor T00 grid
Oxide layer is corrupted such that low-resistance characteristic that short circuit is presented between storage transistor T00 grid and the first source/drain terminal.
Therefore, the first memory cell 110 can be considered one first storing state.
In addition, when the second memory cell 120 is programmed, there is provided 0V signals to bit line BL1,3.3V signal to word-line WL1,
0V signals are to control line CL1.Then switching transistor T11 opens (turn on), and storage transistor T10 grid oxic horizon is not
The high-resistance characteristic that open circuit is presented between storage transistor T10 grid and the first source/drain terminal can be corrupted such that.Therefore,
Second memory cell 120 can be considered one second storing state.
1C figures are refer to, the memory cell schematic equivalent circuit after its depicted programming for existing otp memory.Via
After above-mentioned mode programs, the storage transistor T00 in the first memory cell 110 can be equivalent to a resistance, and it has low-resistance
Characteristic, it can be considered the first storing state.And the storage transistor T10 in the second memory cell 120 can be equivalent to an electric capacity, it has
High-resistance characteristic, it can be considered the second storing state.
It refer to 2A figures with 2B to scheme, its depicted memory cell and its equivalent circuit signal for another otp memory
Figure.2A schemes to include two memory cells 210,220 with 2B figures, has a transistor in each memory cell 210,220, can
Referred to as 1T memory cells.
As shown in 2A figures, p-type substrate (P-sub) 200 is divided into two using shallow slot isolation structure (STI) 230
Part is to define the region of two memory cells 210,220.In the first memory cell 210, N doped regions 212 and shallow trench every
From formation first grid structure 214 on the surface of p-type substrate 200 between structure 230.Furthermore N doped regions 212 are connected to position
First line BL0, first grid structure 214 are connected to word-line WL0.
Similarly, in the second memory cell 220, the p-type substrate between N doped regions 222 and shallow slot isolation structure 230
Second grid structure 224 is formed on 200 surfaces.Furthermore N doped regions 222 are connected to bit line BL1, second grid structure 224
It is connected to word-line WL1.
Schemed from 2A, first grid structure 214 all includes a grid oxic horizon, polycrystalline with second grid structure 224
Polysilicon gate layer and clearance wall.Wherein, grid oxic horizon is divided into two parts, close to the Part I of N doped regions 222
The thickness of grid oxic horizon is thicker, close to the thinner thickness of the Part II grid oxic horizon of shallow slot isolation structure 230.
As illustrated in fig. 2b, the transistor in the first memory cell 210 can be equivalent to the son storages of a sub switch transistor T01 and one
Transistor T00 is deposited, sub switch transistor T01 grid is connected to word-line WL0, and its first source/drain terminal is connected to bit line
BL0；Sub- storage transistor T00 grids are connected to word-line WL0, and its first source/drain terminal is connected to the of sub switch transistor T01
Two source/drain terminal, its second source/drain terminal are suspension joint.
Similarly, the transistor in the second memory cell 220 can be equivalent to a sub switch transistor T11 and a sub- storage transistor
T10, sub switch transistor T11 grid are connected to word-line WL1, and its first source/drain terminal is connected to bit line BL1；Son storage
Transistor T10 grids are connected to word-line WL1, and its first source/drain terminal is connected to sub switch transistor T11 the second source/drain terminal,
Its second source/drain terminal is suspension joint.
For example, when the first memory cell 210 is programmed, there is provided 0V signals to bit line BL0,5V signal to word-line
WL0.Then sub switch transistor T01 opens (turn on), and causes grid oxic horizon quilt relatively thin in sub- storage transistor T00
Destroy so that low-resistance characteristic of short circuit is presented between storage transistor T00 grid and the first source/drain terminal.Therefore, first
Memory cell 210 can be considered one first storing state.
In addition, when the second memory cell 220 is programmed, there is provided 0V signals to bit line BL1,3.3V signal to word-line WL1.
Then switching transistor T11 opens (turn on), and grid oxic horizon relatively thin in storage transistor T10 will not be also destroyed, and be made
Obtain the high-resistance characteristic that open circuit is presented between storage transistor T10 grid and the first source/drain terminal.Therefore, the second memory cell
220 can be considered one second storing state.
2C figures are refer to, the memory cell schematic equivalent circuit after its depicted programming for existing otp memory.Via
After above-mentioned mode programs, the storage transistor T00 in the first memory cell 210 can be equivalent to a resistance, and it has low-resistance
Characteristic, it can be considered the first storing state.And the storage transistor T10 in the second memory cell 220 can be equivalent to an electric capacity, it has
High-resistance characteristic, it can be considered the second storing state.
It is well known that shallow slot isolation structure (STI) is for completely cutting off two transistors so that between two transistors not
Passage (channel) can be formed and produced and leaked electricity and interact.
In other words, it is for preventing from forming N-type between two memory cells shallow slot isolation structure to be used in into otp memory
Doped region, generation when memory cell programs is avoided to leak off to adjacent memory cell and cause program fail.
Furthermore in memory cell, the grid structure of storage transistor needs to be covered on shallow slot isolation structure.And in order to
Deviation of the alignment (misalignment) is prevented, in the manufacturing process of memory cell, it is desirable to provide some reservation regions (margin).Institute
Can be larger with the size of memory cell.
On the other hand, because the size of shallow slot isolation structure is very big, the distance between memory cell can be also caused to become big.
Therefore, the size of existing otp memory can not further reduce.
The content of the invention
The purpose of the present invention is to propose to a kind of one-time programming memory, shallow slot isolation structure is had no between its memory cell.
To reduce the distance between memory cell, and effectively reduce the size of otp memory.
The present invention is a kind of one-time programming memory, including：One first type region, a surface in the first type region have one
First Second-Type doped region, one second Second-Type doped region, one the 3rd Second-Type doped region are mixed with one the 4th Second-Type
Miscellaneous region；One first grid structure, it is formed between the first Second-Type doped region and the second Second-Type doped region
The surface；One second grid structure；One the 3rd grid structure, it is formed at the 3rd Second-Type doped region and the four the
The surface between two type doped regions；One the 4th grid structure；Wherein the second grid structure and the 4th grid knot
The surface being configured between the second Second-Type doped region and the 4th Second-Type doped region；Wherein, this
One type region, the first Second-Type doped region, the second Second-Type doped region and the first grid structure form one first
A first switch transistor in memory cell；The first type region, the second Second-Type doped region and the second grid structure
One first storage transistor formed in first memory cell, the gate terminal of the first switch transistor are connected to one first character
Line, the first source/drain terminal of the first switch transistor are connected to one first bit line, and the second source of the first switch transistor/
Drain terminal is connected to the first source/drain terminal of first storage transistor, and the second source/drain terminal of first storage transistor is suspension joint,
The gate terminal of first storage transistor is connected to one first control line；Wherein, the first type region, the doping of the 3rd Second-Type
The second switch crystal that region, the 4th Second-Type doped region are formed in one second memory cell with the 3rd grid structure
Pipe；The first type region, the 4th Second-Type doped region and the 4th grid structure formed in second memory cell one the
Two storage transistors, the gate terminal of the second switch transistor are connected to one second word-line, and the of the second switch transistor
One source/drain terminal is connected to first bit line, and the second source/drain terminal of the second switch transistor is connected to the second storage crystal
First source/drain terminal of pipe, the second source/drain terminal of second storage transistor are suspension joint, the gate terminal of second storage transistor
It is connected to one second control line；Wherein, table between the second Second-Type doped region and the 4th Second-Type doped region
It is one first type semiconductor below face；And wherein, when a calculation by program, open the first switch transistor and this
One first program voltage is provided between one control line and first bit line, to destroy the second gate of first storage transistor
Pole structure so that first memory cell records one first storing state；Or open the first switch transistor and this first
One second program voltage is provided between control line and first bit line, to maintain the second grid of first storage transistor
Structure so that first memory cell records one second storing state.
The present invention is a kind of one-time programming memory, including：One first type region, a surface in the first type region have one
First Second-Type doped region and one second Second-Type doped region；One first grid structure, including a first grid oxide layer
Be covered on the surface, a first grid layer is covered in the first grid oxide layer, with one first clearance wall surround this first
Grid oxic horizon and the first grid layer, wherein the first grid oxide layer include a Part I first grid oxide layer and one
Part II first grid oxide layer, and the Part II first grid oxide layer is thinner than Part I first grid oxidation
Layer；One second grid structure, including a second grid oxide layer is covered on the surface, a second grid layer be covered in this second
The second grid oxide layer and the second grid layer, the wherein second grid are surrounded on grid oxic horizon, with one second clearance wall
Oxide layer includes a Part I second grid oxide layer and a Part II second grid oxide layer, and the Part II second
Grid oxic horizon is thinner than the Part I second grid oxide layer；Wherein the first grid structure is formed with the second grid structure
The surface between the first Second-Type doped region and the second Second-Type doped region；Wherein, the first type area
Domain, the first Second-Type doped region, the Part I first grid oxide layer and the first grid layer form one first memory
A first switch transistor in born of the same parents；The first type region, the Part II first grid oxide layer and the first grid layer shape
Into one first storage transistor in first memory cell, the gate terminal of the first switch transistor is connected to one first character
Line, the first source/drain terminal of the first switch transistor are connected to one first bit line, and the second source of the first switch transistor/
Drain terminal is connected to the first source/drain terminal of first storage transistor, and the second source/drain terminal of first storage transistor is suspension joint,
The gate terminal of first storage transistor is connected to one first word-line；Wherein, the first type region, second Second-Type doping
The second switch crystal that region, the Part I second grid oxide layer are formed in one second memory cell with the second grid layer
Pipe；The first type region, the Part II second grid oxide layer and the second grid layer formed in second memory cell one
Second storage transistor, the gate terminal of the second switch transistor are connected to one second word-line, the second switch transistor
First source/drain terminal is connected to first bit line, and the second source/drain terminal of the second switch transistor is connected to the second storage crystalline substance
First source/drain terminal of body pipe, the second source/drain terminal of second storage transistor are suspension joint, the grid of second storage transistor
End is connected to one second word-line；Wherein, being somebody's turn to do between the first Second-Type doped region and the second Second-Type doped region
Lower face is one first type semiconductor；And wherein, when a calculation by program, in first bit line and first character
One first program voltage is provided between line, to destroy the Part II first grid oxide layer so that first memory cell records
One first storing state；Or one second program voltage is provided between first bit line and first word-line, to maintain
The Part II first grid oxide layer so that first memory cell records one second storing state.
The present invention be it is a kind of in order to have and more preferably understand to the above-mentioned and other aspect of the present invention, it is cited below particularly preferably to implement
Example, and coordinate institute's accompanying drawings, it is described in detail below：
Brief description of the drawings
The depicted memory cells and its schematic equivalent circuit for otp memory of Figure 1A and Figure 1B.
Memory cell schematic equivalent circuit after the depicted programmings for existing otp memory of Fig. 1 C.
The depicted memory cells and its schematic equivalent circuit for another otp memory of Fig. 2A and Fig. 2 B.
Memory cell schematic equivalent circuit after the depicted programmings for existing otp memory of Fig. 2 C.
It is the memory cell of otp memory of first embodiment of the invention depicted in Fig. 3 A to Fig. 3 C, top view and equivalent
Circuit.
Fig. 4 A and Fig. 4 B are depicted to be shown for the memory array and equivalent circuit of first embodiment of the invention otp memory
It is intended to.
Programming running is listed in reading coherent signal schematic diagram when operating for memory array depicted in Fig. 5 A to Fig. 5 D.
The depicted memory cell second embodiment schematic diagrames for otp memory of the present invention of Fig. 6.
It is memory cell, top view and the equivalent electric of third embodiment of the invention otp memory depicted in Fig. 7 A to Fig. 7 C
Road.
Fig. 8 A and Fig. 8 B are depicted to be shown for the memory array and equivalent circuit of third embodiment of the invention otp memory
It is intended to.
Programming running is listed in reading coherent signal schematic diagram when operating for memory array depicted in Fig. 9 A to Fig. 9 D.
The depicted memory cell fourth embodiment schematic diagrames for otp memory of the present invention of Figure 10.
Description of reference numerals：
100、200：P-type substrate
110、120、210、220：Memory cell
111、112、121、122、212、222：N-type doping region
113、114、123、124、214、224：Grid structure
130、230：Shallow slot isolation structure
300、400：P-type substrate
310、320、370、390、410、420、460、480：Memory cell
311、312、321、322、412、422：N-type doping region
365、366、375、376、462、482：N-type doping region
330、340、350、360、430、440：Grid structure
367、371、377、381、470、490：Grid structure
331、341、351、361、431、441：Grid oxic horizon
368、372、378、382、471、491：Grid oxic horizon
332、342、352、362、432、442：Polycrystalline silicon gate layer
369、373、379、383、472、492：Polycrystalline silicon gate layer
333、343、353、363、433、443：Clearance wall
370、374、377、384、473、493：Clearance wall
399、499：P-type heavily doped region
431a、441a、471a、491a：Part I grid oxic horizon
431b、441b、471b、491b：Part II grid oxic horizon
510、520、530、540：Memory cell
Embodiment
It refer to 3A figures to 3C to scheme, the memory cell of its depicted otp memory for first embodiment of the invention, bow
View and equivalent circuit.3A figures include two memory cells 310,320, have two crystalline substances in each memory cell 310,320
Body pipe, it can be described as 2T memory cells.
In the first memory cell 310, have first on the surface of p-type substrate 300 between two N doped regions 311,312
Grid structure 330, it includes grid oxic horizon 331, polycrystalline silicon gate layer 332 and clearance wall 333.Furthermore in N doped regions
There is second grid structure 340, it includes grid oxic horizon 341, polysilicon gate on the surface of p-type substrate 300 of 312 opposite sides
Layer 342 and clearance wall 343.Furthermore N doped regions 311 are connected to bit line BL0, the polysilicon gate of first grid structure 330
Pole layer 332 is connected to word-line WL0, the polycrystalline silicon gate layer 342 of second grid structure 340 is connected to control line CL0.
Similarly, in the second memory cell 320, have on the surface of p-type substrate 300 between two N doped regions 321,322
First grid structure 350, it includes grid oxic horizon 351, polycrystalline silicon gate layer 352 and clearance wall 353.Furthermore adulterated in N
There is second grid structure 360, it includes grid oxic horizon 361, polysilicon on the surface of p-type substrate 300 of the opposite side of region 322
Grid layer 362 and clearance wall 363.Furthermore N doped regions 321 are connected to bit line BL0, the polycrystalline of first grid structure 350
Polysilicon gate layer 352 is connected to word-line WL1, the polycrystalline silicon gate layer 362 of second grid structure 360 is connected to control line CL1.
300, two N doped regions 311,312 of p-type substrate and the shape of first grid structure 330 in first memory cell 310
Into a switching transistor；P-type substrate 300, N doped regions 312 and second grid structure 340 form a storage transistor.Together
Manage, 300, two N doped regions 321,322 of p-type substrate and first grid structure 350 in the second memory cell 320 form one
Switching transistor；P-type substrate 300, N doped regions 322 and second grid structure 360 are to form a storage transistor.
Otp memory top view as seen in figure 3b, it is first direction (horizontal direction) configuration that bit line BL0, which is presented,
And it is second direction (vertical direction) that word-line WL0, WL1 and control line CL0, CL1, which are presentations,.In addition, on word-line BL0, point
There is not via (via) to be connected to N doped regions 311,321.Furthermore bit line BL0 is not electrically connected to word-line WL0, WL1
With control line CL0, CL1.
Equivalent circuit as shown in 3C figures, the first memory cell 310 include the storages of a switching transistor Ts00 and one
Transistor Td00, switching transistor Ts00 grids are connected to word-line WL0, and its first source/drain terminal is connected to bit line BL0；Storage
Deposit transistor Td00 grids and be connected to control line CL0, its first source/drain terminal is connected to switching transistor Ts00 the second source/drain
End, its second source/drain terminal is suspension joint.Second memory cell 120 includes a switching transistor Ts10 and a storage transistor
Td10, switching transistor Ts10 grids are connected to word-line WL1, and its first source/drain terminal is connected to bit line BL0；Store crystal
Pipe Td10 grids are connected to control line CL1, and its first source/drain terminal is connected to switching transistor Ts10 the second source/drain terminal, and it
Two source/drain terminal are suspension joint.
It refer to 4A figures with 4B to scheme, its depicted memory array for first embodiment of the invention otp memory
(memory array) and schematic equivalent circuit.
As shown in figure 4, by it is multiple combined with first embodiment structure identical memory cell after form memory array
Row.As shown in figure 4, memory array includes four memory cells 310,320,510,520.Wherein, the first memory cell 310 connects
It is connected to word-line WL0, control line CL0, bit line BL0；Second memory cell 320 is connected to word-line WL1, control line CL1, bit
Line BL0；3rd memory cell 510 is connected to word-line WL0, control line CL0, bit line BL1；4th memory cell 520 is connected to word
First line WL1, control line CL1, bit line BL1.
As shown in 4B figures, the first memory cell 310 includes an a switching transistor Ts00 and storage transistor Td00；
Second memory cell 320 includes an a switching transistor Ts10 and storage transistor Td10；3rd memory cell 510 includes one
A switching transistor Ts01 and storage transistor Td01；4th memory cell 520 includes a switching transistor Ts11 and one
Storage transistor Td11.Its annexation repeats no more.
It refer to 5A figures to 5D to scheme, its depicted is listed in for memory array programs running (program
Operation) with reading coherent signal schematic diagram during running (read operation).5A figures are refer to 5B to scheme,
When the first memory cell 310 is programmed, there is provided 0V signals to bit line BL0,1.2V signal to word-line WL0,4V signal to control
Line CL0.In other words, the voltage between control line CL0 and bit line BL0 (4V) can be considered the first program voltage.Meanwhile in volume
During the second memory cell 320 of journey, there is provided 0V signals to bit line BL0,1.2V signal to word-line WL1,0V signal to control line
CL1.In other words, the voltage between control line CL1 and bit line BL0 (0V) furthermore can be considered the second program voltage, p-type substrate
300 voltage can be the 0V voltages of p type wellses area (PW).
Schemed from 5B, when the switching transistor of the first memory cell 310 is opened, the voltage of N doped regions 312 is about
The voltage of 0V and polycrystalline silicon gate layer 342 is about 4V.Therefore, can quilt closest to the grid oxic horizon 341 at N doped regions 312
Destroy (rupture), and low-resistance characteristic of short circuit is presented.That is, first storage transistor Td00 be destroyed.Therefore,
One memory cell 310 can be considered the first storing state.
Meanwhile when the switching transistor of the second memory cell 320 is opened, the voltage of N doped regions 322 is about 0V and polycrystalline
The voltage of polysilicon gate layer 362 is about 0V.Therefore, grid oxic horizon 361 will not be destroyed, and the high-resistance spy of open circuit is presented
Property.That is, second storage transistor Td10 maintain as former state without being destroyed.Therefore, the second memory cell 320 can be considered the second storage
Deposit state.
5C figures are refer to, as word-line WL0, WL1 1.2V, control line CL0 is 1.2V, and control line CL1 is 0V, bit
Line BL0 is 0V, and when bit line BL1 is suspension joint (F), the 3rd memory cell 510 and the 4th memory cell 520 are non-selection memory cell
(non-selected cell)；First memory cell 310 and the second memory cell 320 are selection memory cell (selected cell),
And first memory cell 310 be programmed to the first storing state, and the second memory cell 320 is programmed to the second storing state.
Furthermore as shown in 5D figures, explained exemplified by reading the first memory cell 310.When running is read, word-line
WL0 is 0.85V, and word-line WL1 is 0V, and control line CL0 is 1.5V, and control line CL1 is 0V, and bit line BL0 is 0V, bit line
BL1 is suspension joint.So the second memory cell 320, the 3rd memory cell 510 and the 4th memory cell 520 are non-selection memory cell；First
Memory cell 310 is selection memory cell.
As shown in 5D figures, when the first memory cell 310 is read, it is brilliant that the voltage (0.85V) on word-line WL0 opens switch
Body pipe Ts00, and the voltage difference (1.5V) between control line CL0 and bit line BL0 so that storage transistor Td00 produces a note
Recall born of the same parents' electric current (Icell) and bit line BL0 is flowed to by control line CL0.Therefore, can be on control line CL0 or bit line BL0, profit
Sensed memory cell electric current Icell size with induction amplifier (sense amplifier) and confirmed the first memory cell 310
Storing state.In other words, voltage (1.5V) can be considered reading voltage between control line CL0 and bit line BL0.
Similarly, when the second memory cell 320 is read, word-line WL0 is 0V, and word-line WL1 is 0.85V, and control line CL0 is
0V, control line CL1 are 1.5V, and bit line BL0 is 0V, and bit line BL1 is suspension joint.Afterwards, you can in control line CL1 or bit
The memory cell electric current of the second memory cell 320 is induced on line BL0.
Explanation more than, as shown in the first embodiment of the present invention, in two memory cells 310,320, store
Grid structure 340,360 in transistor manufacture very close to so that clearance wall 343,363 overlaps each other.As long as storage is brilliant
Polycrystalline silicon gate layer 342,362 in body pipe does not contact with each other, can't be affected between two memory cells 310,320.Also
That is, two memory cells 340,360 all smoothly can be programmed and read.And memory cell 310,320 is each other in first embodiment
Very close, its distance can be less than two times of clearance wall width.
Furthermore the width of clearance wall is relevant to the width of grid structure.Assuming that the width of grid structure is 100nm, then between
The width of gap wall is about 0.25~1.5 times of grid structure width, that is, the width of clearance wall is between 25nm~150nm.
Therefore, two maximum width of clearance wall are 300nm.In other words, when the grid structure 360 of second grid structure 340 and the 4th
Width when being all 100nm, memory cell 310, the distance between 320 can be less than two clearance wall Breadth Maximums (300nm), or
Less than the width (300nm) of three grid structures.
According to the first embodiment of the present invention, as long as the material of two memory cells 310,320 is identical with p-type substrate 300
P-type semiconductor, you can effectively prevent interacting between two memory cells 310,320.Therefore, do not considering that OTP is deposited
Under the size of reservoir, when distance is more than the width of two clearance walls between two memory cells 310,320, naturally it is also possible to effectively
Ground prevents from forming passage (channel) between two storage transistors and producing and leak electricity and interact.
Refer to the and refer to Fig. 6, it is depicted be otp memory of the present invention memory cell second embodiment schematic diagram.
Wherein, there are two transistors in each memory cell 370,390.
In the first memory cell 370, have first on the surface of p-type substrate 395 between two N doped regions 365,366
Grid structure 367, it includes grid oxic horizon 368, polycrystalline silicon gate layer 369 and clearance wall 370.Furthermore in N doped regions
There is second grid structure 371, it includes grid oxic horizon 372, polysilicon gate on the surface of p-type substrate 395 of 366 opposite sides
Layer 373 and clearance wall 374.Furthermore N doped regions 365 are connected to bit line BL0, the polysilicon gate of first grid structure 367
Pole layer 369 is connected to word-line WL0, the polycrystalline silicon gate layer 373 of second grid structure 371 is connected to control line CL0.
Similarly, in the second memory cell 390, have on the surface of p-type substrate 395 between two N doped regions 375,376
First grid structure 377, it includes grid oxic horizon 378, polycrystalline silicon gate layer 379 and clearance wall 380.Furthermore adulterated in N
There is second grid structure 381, it includes grid oxic horizon 382, polysilicon on the surface of p-type substrate 395 of the opposite side of region 376
Grid layer 383 and clearance wall 384.Furthermore N doped regions 375 are connected to bit line BL1, the polycrystalline of first grid structure 377
Polysilicon gate layer 379 is connected to word-line WL1, the polycrystalline silicon gate layer 383 of second grid structure 381 is connected to control line CL1.
395, two N doped regions 365,366 of p-type substrate and the shape of first grid structure 367 in first memory cell 370
Into a switching transistor；P-type substrate 395, N doped regions 366 and second grid structure 371 form a storage transistor.Together
Manage, 395, two N doped regions 375,376 of p-type substrate and first grid structure 377 in the second memory cell 390 form one
Switching transistor；P-type substrate 395, N doped regions 376 and second grid structure 381 are to form a storage transistor.
According to the second embodiment of the present invention, between the second grid structure 371,381 in two memory cells 370,390
Lower face is p-type heavy doping (P+) region 399.It can more efficiently prevent from mutual shadow between two memory cells 370,390
Ring.
Similarly, the memory cell of second embodiment can also be combined into memory array, its program running with read running with
First embodiment is identical, and here is omitted.
It refer to 7A figures to 7C to scheme, it is the memory cell of third embodiment of the invention otp memory that it is depicted, is overlooked
Figure and equivalent circuit.7A figures include two memory cells 410,420, have a crystal in each memory cell 410,420
Pipe, can be described as 1T memory cells.
There is first grid structure 430 and the on the surface of p-type substrate 400 between two N doped regions 412,422
Two grid structures 440, it is belonging respectively to the first memory cell 410 and the second memory cell 420.First grid structure 430 includes grid oxygen
Change layer 431, polycrystalline silicon gate layer 432 and clearance wall 433；Second grid structure 440 includes grid oxic horizon 441, polysilicon
Grid layer 442 and clearance wall 443.
Furthermore in the first memory cell 410, N doped regions 412 be connected to bit line BL0, first grid structure 430 it is more
Polysilicon gate layer 432 is connected to word-line WL0；In second memory cell 420, N doped regions 422 are connected to bit line BL1, second
The polycrystalline silicon gate layer 442 of grid structure 440 is connected to word-line WL1.
According to the third embodiment of the invention, the grid oxic horizon 431 of first grid structure 430 can be distinguished according to its thickness
For two parts, the grid oxic horizon 431a of Part I is thicker, and the grid oxic horizon 431b of Part II is relatively thin.Furthermore the
The grid oxic horizon 441 of two grid structures 440 can divide into two parts, the grid oxic horizon of Part I according to its thickness
441a is thicker, and the grid oxic horizon 441b of Part II is relatively thin.
Therefore, the transistor in the first memory cell 410 can divide into sub switch transistor and sub- storage transistor.Its
In, p-type substrate 400, N doped regions 412, Part I grid oxic horizon 431a and polycrystalline silicon gate layer 432 are to form son to open
Close transistor；P-type substrate 400, Part II grid oxic horizon 431b and polycrystalline silicon gate layer 432 are to form sub- storage crystal
Pipe.Similarly, the transistor area in the second memory cell 420 is divided into sub switch transistor and sub- storage transistor.Wherein, p-type base
Plate 400, N doped regions 422, Part I grid oxic horizon 441a and polycrystalline silicon gate layer 442 are to form sub switch transistor；
P-type substrate 400, Part II grid oxic horizon 441b and polycrystalline silicon gate layer 442 are to form sub- storage transistor.
Otp memory top view as shown in 7B figures, it is first direction (horizontal direction) configuration that bit line BL0, which is presented,
And it is second direction (vertical direction) that word-line WL0, WL1 and control line CL0, CL1, which are presentations,.In addition, on word-line BL0, point
There is not via (via) to be connected to N doped regions 412,422.Furthermore bit line BL0 be not electrically connected to word-line WL0,
WL1。
Equivalent circuit as shown in 7C figures, the first memory cell 410 include of a sub switch transistor Ts00 and one
Storage transistor Td00, sub switch transistor Ts00 and sub- storage transistor Td00 grid are all connected to word-line WL0, and son is opened
The first end for closing transistor Ts00 is connected to bit line BL0, and sub switch transistor Ts00 the second end is connected to sub- storage crystal
Pipe Td00 first end, sub- storage transistor Td00 the second end is suspension joint.Similarly, the second memory cell 420 includes a son and opened
Close transistor Ts10 and one sub- storage transistor Td10, sub switch transistor Ts10 and sub- storage transistor Td10 grid all
It is connected to word-line WL1, sub switch transistor Ts10 first end is connected to bit line BL0, and the of sub switch transistor Ts10
Two ends are connected to sub- storage transistor Td10 first end, and sub- storage transistor Td10 the second end is suspension joint.
It refer to 8A figures with 8B to scheme, its depicted memory array for third embodiment of the invention otp memory
And schematic equivalent circuit.
As shown in 8A figures, by it is multiple combined with 3rd embodiment structure identical memory cell after form memory array
Row.As shown in 8A figures, memory array includes four memory cells 410,420,530,540.Wherein, the first memory cell 410 connects
It is connected to word-line WL0, bit line BL0；Second memory cell 420 is connected to word-line WL1, bit line BL0；3rd memory cell 530
It is connected to word-line WL0, bit line BL1；4th memory cell 540 is connected to word-line WL1, bit line BL1.
As shown in 8B figures, the first memory cell 410 includes a sub switch transistor Ts00 and a sub- storage transistor
Td00；Second memory cell 420 includes the sub- storage transistor Td10 of a sub switch transistor Ts10 and one；3rd memory cell
530 include the sub- storage transistor Td01 of a sub switch transistor Ts01 and one；4th memory cell 540 includes a sub switch
The sub- storage transistor Td11 of transistor Ts11 and one.Its annexation repeats no more.
It refer to 9A figures to 9D to scheme, be related when memory array is listed in programming running to reading running depicted in it
Signal schematic representation.It refer to 9A figures with 9B to scheme, when the first memory cell 410 is programmed, there is provided 0V signals to bit line BL0,
5V signals are to word-line WL0.In other words, the voltage between word-line WL0 and bit line BL0 (5) can be considered the first program voltage.
Meanwhile when the second memory cell 420 is programmed, there is provided 0V signals to bit line BL0,3.3V signal to word-line WL1.
Furthermore the voltage of p-type substrate 300 can be the 0V voltages of p type wellses area (PW).In other words, between word-line WL1 and bit line BL0
Voltage (3.3V) can be considered the second program voltage.
Schemed from 9B, when the first memory cell 410 is programmed, there is provided 0V signals to bit line BL0,5V signal to character
Line WL0.Then sub switch transistor is opened, and causes the Part II grid oxic horizon 431b of sub- storage transistor to be destroyed, and is made
Sub- storage transistor polycrystalline silicon gate layer 432 and p-type substrate 400 between present short circuit low-resistance characteristic.Therefore,
One memory cell 410 can be considered the first storing state.
Schemed from 9B, when group switching transistor is opened, the passage below Part I grid oxic horizon 431a
(channel) voltage is about 0V and the voltage of polycrystalline silicon gate layer 432 is about 5V.Therefore, the Part II most connected at road
Grid oxic horizon 431b can be destroyed, and low-resistance characteristic of short circuit is presented.Therefore, the first memory cell 410 can be considered first
Storing state.
In addition, when the second memory cell 420 is programmed, there is provided 0V signals to bit line BL1,3.3V signal to word-line WL1.
Then sub switch transistor is opened, and the Part II grid oxic horizon 441b of sub- storage transistor will not be corrupted such that sub- storage
Deposit the high-resistance characteristic that open circuit is presented between the polycrystalline silicon gate layer 442 of transistor and p-type substrate 400.Therefore, the second memory
Born of the same parents 420 can be considered one second storing state.
9C figures are refer to, when word-line WL0 is 5V, word-line WL1 is 3.3V, and bit line BL0 is 0V, bit line BL1
For suspension joint (F) when, the 3rd memory cell 530 and the 4th memory cell 540 are non-selection memory cell；First memory cell 410 and the second note
Born of the same parents 420 are recalled for selection memory cell (selectedcell), and the first memory cell 410 is programmed to the first storing state, Yi Ji
Two memory cells 420 are programmed to the second storing state.
Furthermore as shown in 9D figures, explained exemplified by reading the first memory cell 410.When running is read, word-line
WL0 is 2.5V, and word-line WL1 is 0V, and bit line BL0 is 0V, and bit line BL1 is suspension joint.So the second memory cell the 420, the 3rd
The memory cell 540 of memory cell 530 and the 4th is non-selection memory cell；First memory cell 410 is selection memory cell.
As shown in 9D figures, when the first memory cell 410 is read, the voltage (2.5V) on word-line WL0 opens sub switch
Transistor Ts00, and the voltage difference (2.5V) between word-line WL0 and bit line BL0 so that sub- storage transistor Td00 is produced
One memory cell electric current (Icell) flows to bit line BL0 by word-line WL0.Therefore, can be amplified on bit line BL0 using sensing
Device come sense memory cell electric current Icell size and confirm the first memory cell 410 storing state.In other words, word-line WL0 with
Voltage (2.5V) between bit line BL0 can be considered reading voltage.
Similarly, when the second memory cell 420 is read, word-line WL0 is 0V, and word-line WL1 is 2.5V, and bit line BL0 is
0V, bit line BL1 are suspension joint.Afterwards, you can the memory cell electric current of the second memory cell 420 is induced on bit line BL0.
According to the third embodiment of the invention, formed between two memory cells 410,420 of the invention it is other every
It is used for isolating two memory cells 410,420 from structure.410,420 merely with original p-type substrate between two memory cells of the present invention
P-type semiconductor can be effectively isolated two memory cells 410,420.Therefore, can be by the grid in two memory cells 410,420
Pole structure 430,440 make very close to and will not also being interacted between two memory cells 410,420.
Explanation more than, the present invention can allow memory cell 410,420 very close each other, and its distance can be with small
In two times of clearance wall width.
In general, the width of clearance wall is relevant to the width of grid structure.Assuming that the width of grid structure is 200nm,
Then the width of clearance wall is about 0.25~1.5 times of grid structure width, that is, the width of clearance wall 50nm~300nm it
Between.Therefore, two maximum width of clearance wall are 600nm.In other words, when first grid structure 430 and second grid structure
When 440 width is all 200nm, memory cell 410, the distance between 420 can be less than two clearance wall Breadth Maximums (600nm),
Or the width (300nm) less than three grid structures.
According to the third embodiment of the invention, as long as the material of two memory cells 410,420 is identical with p-type substrate 400
P-type semiconductor, you can effectively prevent from interacting between two memory cells 410,420.Therefore, OTP storages are not being considered
Under the size of device, when distance is more than the width of two clearance walls between two memory cells 410,420, naturally it is also possible to effectively
Prevent from forming passage (channel) between two storage transistors and producing and leak electricity and interact.
Figure 10 is refer to, its depicted memory cell fourth embodiment schematic diagram for otp memory of the present invention.Wherein, often
There is a transistor in individual memory cell 460,480.
There is first grid structure 470 and the on the surface of p-type substrate 495 between two N doped regions 462,482
Two grid structures 490, it is belonging respectively to the first memory cell 460 and the second memory cell 480.First grid structure 470 includes grid oxygen
Change layer 471, polycrystalline silicon gate layer 472 and clearance wall 473；Second grid structure 490 includes grid oxic horizon 491, polysilicon
Grid layer 492 and clearance wall 493.
Furthermore in the first memory cell 460, N doped regions 462 be connected to bit line BL0, first grid structure 470 it is more
Polysilicon gate layer 472 is connected to word-line WL0；In second memory cell 490, N doped regions 482 are connected to bit line BL1, second
The polycrystalline silicon gate layer 492 of grid structure 490 is connected to word-line WL1.
According to the fourth embodiment of the invention, the grid oxic horizon 471 of first grid structure 470 can be distinguished according to its thickness
For two parts, the grid oxic horizon 471a of Part I is thicker, and the grid oxic horizon 471b of Part II is relatively thin.Furthermore the
The grid oxic horizon 491 of two grid structures 490 can divide into two parts, the grid oxic horizon of Part I according to its thickness
491a is thicker, and the grid oxic horizon 491b of Part II is relatively thin.
Therefore, the transistor in the first memory cell 460 can divide into sub switch transistor and sub- storage transistor.Its
In, p-type substrate 495, N doped regions 462, Part I grid oxic horizon 471a and polycrystalline silicon gate layer 472 are to form son to open
Close transistor；P-type substrate 495, Part II grid oxic horizon 471b and polycrystalline silicon gate layer 472 are to form sub- storage crystal
Pipe.Similarly, the transistor area in the second memory cell 480 is divided into sub switch transistor and sub- storage transistor.Wherein, p-type base
Plate 495, N doped regions 482, Part I grid oxic horizon 491a and polycrystalline silicon gate layer 492 are to form sub switch transistor；
P-type substrate 495, Part II grid oxic horizon 491b and polycrystalline silicon gate layer 492 are to form sub- storage transistor.
According to the fourth embodiment of the invention, the lower face between first grid structure 470 and second grid structure 490
For p-type heavy doping (P+) region 499.It can more efficiently prevent from interacting between two memory cells 460,480.
Similarly, the memory cell of fourth embodiment can also be combined into memory array, its program running with read running with
3rd embodiment is identical, and here is omitted.
Explanation more than, the present invention is thin to propose otp memory.Completely without the situation of shallow slot isolation structure
Under, two memory cells make very close to and still can be with normal operating memory cell.
Furthermore because distance is very short between the memory cell of otp memory of the present invention, it can effectively improve memory cell
Density, increase the capacity of otp memory.
Furthermore the N-type transistor that is all formed in above-described embodiment with p-type substrate and n-type doping region is said
It is bright, can certainly be using the P-type transistor that N-type substrate and p-type doped region are formed come real in those skilled in the art
The existing present invention.Furthermore in the utilization of reality, p-type substrate can be substituted by p type wellses region (P-well region), equally
The effect of invention can also be reached.
In summary, although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the invention, when various changes can be made
With retouching.Therefore, the protection domain of the present invention is worked as and is defined by claim limited range.
Claims (16)
1. a kind of one-time programming memory, including：
There are one first Second-Type doped region, the doping of one second Second-Type in one first type region, a surface in the first type region
Region, one the 3rd Second-Type doped region and one the 4th Second-Type doped region；
One first grid structure, the table being formed between the first Second-Type doped region and the second Second-Type doped region
Above face；
One second grid structure；
One the 3rd grid structure, the table being formed between the 3rd Second-Type doped region and the 4th Second-Type doped region
Above face；
One the 4th grid structure；Wherein the second grid structure is formed at the second Second-Type doped region with the 4th grid structure
The surface between domain and the 4th Second-Type doped region；
Wherein, the first type region, the first Second-Type doped region, the second Second-Type doped region and the first grid knot
The first switch transistor being configured in one first memory cell；The first type region, the second Second-Type doped region are with being somebody's turn to do
One first storage transistor that second grid structure is formed in first memory cell, the gate terminal connection of the first switch transistor
To one first word-line, the first source/drain terminal of the first switch transistor is connected to one first bit line, the first switch crystal
Second source/drain terminal of pipe is connected to the first source/drain terminal of first storage transistor, and the second source of first storage transistor/
Drain terminal is suspension joint, and the gate terminal of first storage transistor is connected to one first control line；
Wherein, the first type region, the 3rd Second-Type doped region, the 4th Second-Type doped region and the 3rd grid knot
The second switch transistor being configured in one second memory cell；The first type region, the 4th Second-Type doped region are with being somebody's turn to do
One second storage transistor that 4th grid structure is formed in second memory cell, the gate terminal connection of the second switch transistor
To one second word-line, the first source/drain terminal of the second switch transistor is connected to first bit line, the second switch crystal
Second source/drain terminal of pipe is connected to the first source/drain terminal of second storage transistor, and the second source of second storage transistor/
Drain terminal is suspension joint, and the gate terminal of second storage transistor is connected to one second control line；
Wherein, the lower face between the second Second-Type doped region and the 4th Second-Type doped region is one first type
Semiconductor；And
Wherein, when a calculation by program, open the first switch transistor and first control line and first bit line it
Between provide one first program voltage, to destroy the second grid structure of first storage transistor so that first memory cell
Record one first storing state；Or open the first switch transistor and first control line and first bit line it
Between provide one second program voltage, to maintain the second grid structure of first storage transistor so that first memory cell
Record one second storing state.
2. one-time programming memory as claimed in claim 1, wherein when one reads computing, open the first switch transistor
And provide one between first control line and first bit line and read voltage so that first memory cell produces a memory cell
Electric current, to judge first memory cell for first storing state or second storing state.
3. one-time programming memory as claimed in claim 1, is further included：
There are one the 5th Second-Type doped region, one the 6th Second-Type doped region, one the seven the second in the first type region surface
Type doped region and one the 8th Second-Type doped region；
One the 5th grid structure, the table being formed between the 5th Second-Type doped region and the 6th Second-Type doped region
Above face；
One the 6th grid structure；
One the 7th grid structure, the table being formed between the 7th Second-Type doped region and the 8th Second-Type doped region
Above face；
One the 8th grid structure；Wherein the 6th grid structure is formed at the 6th Second-Type doped region with the 8th grid structure
The surface between domain and the 8th Second-Type doped region；
Wherein, the first type region, the 5th Second-Type doped region, the 6th Second-Type doped region and the 5th grid knot
One the 3rd switching transistor being configured in one the 3rd memory cell；The first type region, the 6th Second-Type doped region are with being somebody's turn to do
One the 3rd storage transistor that 6th grid structure is formed in the 3rd memory cell, the gate terminal connection of the 3rd switching transistor
To first word-line, the first source/drain terminal of the 3rd switching transistor is connected to a second bit line, the 3rd switch crystal
Second source/drain terminal of pipe is connected to the first source/drain terminal of the 3rd storage transistor, and the second source of the 3rd storage transistor/
Drain terminal is suspension joint, and the gate terminal of the 3rd storage transistor is connected to first control line；
Wherein, the first type region, the 7th Second-Type doped region, the 8th Second-Type doped region and the 7th grid knot
One the 4th switching transistor being configured in one the 4th memory cell；The first type region, the 8th Second-Type doped region are with being somebody's turn to do
One the 4th storage transistor that 8th grid structure is formed in the 4th memory cell, the gate terminal connection of the 4th switching transistor
To second word-line, the first source/drain terminal of the 4th switching transistor is connected to the second bit line, the 4th switch crystal
Second source/drain terminal of pipe is connected to the first source/drain terminal of the 4th storage transistor, and the second source of the 4th storage transistor/
Drain terminal is suspension joint, and the gate terminal of the 4th storage transistor is connected to second control line；And
Wherein, the lower face between the 6th Second-Type doped region and the 8th Second-Type doped region is first type
Semiconductor.
4. one-time programming memory as claimed in claim 1, wherein between the second grid structure and the 4th grid structure
The lower face be one first type heavily doped region.
5. one-time programming memory as claimed in claim 1, wherein the first type region are one first type substrate or one
One type well area.
6. one-time programming memory as claimed in claim 1, wherein the first grid structure, including a first grid oxide layer
Be covered on the surface, a first grid layer is covered in the first grid oxide layer, with one first clearance wall surround this first
Grid oxic horizon and the first grid layer；The second grid structure, including a second grid oxide layer is covered on the surface, one
Second grid layer is covered in the second grid oxide layer, the second grid oxide layer is surrounded with one second clearance wall and this second
Grid layer；3rd grid structure, including one the 3rd grid oxic horizon is covered on the surface, one the 3rd grid layer is covered in this
The 3rd grid oxic horizon and the 3rd grid layer are surrounded on 3rd grid oxic horizon, with a third space wall；And the 4th
Grid structure, including one the 4th grid oxic horizon is covered on the surface, one the 4th grid layer is covered in the 4th gate oxidation
The 4th grid oxic horizon and the 4th grid layer are surrounded on layer, with one the 4th clearance wall.
7. one-time programming memory as claimed in claim 6, wherein second clearance wall overlap each other with the 4th clearance wall.
8. one-time programming memory as claimed in claim 7, wherein overlapping second clearance wall and the 4th clearance wall
Width is less than the width of the three times second grid structure.
9. one-time programming memory as claimed in claim 6, it is optionally to destroy wherein when first memory cell is programmed
The second grid oxide layer；It is optionally to destroy the 4th grid oxic horizon when second memory cell is programmed.
10. a kind of one-time programming memory, including：
One first type region, a surface in the first type region have one first Second-Type doped region and one second Second-Type to adulterate
Region；
One first grid structure, including a first grid oxide layer is covered on the surface, a first grid layer be covered in this
The first grid oxide layer and the first grid layer, the wherein first grid are surrounded on one grid oxic horizon, with one first clearance wall
Pole oxide layer includes a Part I first grid oxide layer and a Part II first grid oxide layer, and the Part II the
One grid oxic horizon is thinner than the Part I first grid oxide layer；
One second grid structure, including a second grid oxide layer is covered on the surface, a second grid layer be covered in this
The second grid oxide layer and the second grid layer, the wherein second gate are surrounded on two grid oxic horizons, with one second clearance wall
Pole oxide layer includes a Part I second grid oxide layer and a Part II second grid oxide layer, and the Part II the
Two grid oxic horizons are thinner than the Part I second grid oxide layer；Wherein the first grid structure and the second grid structure shape
Into the surface between the first Second-Type doped region and the second Second-Type doped region；
Wherein, the first type region, the first Second-Type doped region, the Part I first grid oxide layer and the first grid
The first switch transistor that pole layer is formed in one first memory cell；The first type region, Part II first grid oxidation
One first storage transistor that layer is formed in first memory cell with the first grid layer, the gate terminal of the first switch transistor
One first word-line is connected to, the first source/drain terminal of the first switch transistor is connected to one first bit line, the first switch
Second source/drain terminal of transistor is connected to the first source/drain terminal of first storage transistor, and the second of first storage transistor
Source/drain terminal is suspension joint, and the gate terminal of first storage transistor is connected to first word-line；
Wherein, the first type region, the second Second-Type doped region, the Part I second grid oxide layer and the second gate
The second switch transistor that pole layer is formed in one second memory cell；The first type region, Part II second grid oxidation
One second storage transistor that layer is formed in second memory cell with the second grid layer, the gate terminal of the second switch transistor
One second word-line is connected to, the first source/drain terminal of the second switch transistor is connected to first bit line, the second switch
Second source/drain terminal of transistor is connected to the first source/drain terminal of second storage transistor, and the second of second storage transistor
Source/drain terminal is suspension joint, and the gate terminal of second storage transistor is connected to second word-line；
Wherein, the lower face between the first Second-Type doped region and the second Second-Type doped region is one first type
Semiconductor；And
Wherein, when a calculation by program, one first program voltage is provided between first bit line and first word-line, with
Destroy the Part II first grid oxide layer so that first memory cell records one first storing state；Or this first
One second program voltage is provided between bit line and first word-line, to maintain the Part II first grid oxide layer,
So that first memory cell records one second storing state.
11. one-time programming memory as claimed in claim 10, wherein when one reads computing, in first word-line with being somebody's turn to do
Between first bit line provide one read voltage so that first memory cell produce a memory cell electric current, to judge this first
Memory cell is first storing state or second storing state.
12. one-time programming memory as claimed in claim 10, is further included：
There are one the 3rd Second-Type doped region and one the 4th Second-Type doped region in the surface in the first type region；
One the 3rd grid structure, including one the 3rd grid oxic horizon is covered on the surface, one the 3rd grid layer be covered in this
The 3rd grid oxic horizon and the 3rd grid layer, wherein the 3rd grid are surrounded on three grid oxic horizons, with a third space wall
Pole oxide layer includes the grid oxic horizon of a Part I the 3rd and the grid oxic horizon of a Part II the 3rd, and the Part II
Three grid oxic horizons are thinner than the grid oxic horizon of Part I the 3rd；
One the 4th grid structure, including one the 4th grid oxic horizon is covered on the surface, one the 4th grid layer be covered in this
The 4th grid oxic horizon and the 4th grid layer, wherein the 4th grid are surrounded on four grid oxic horizons, with one the 4th clearance wall
Pole oxide layer includes the grid oxic horizon of a Part I the 4th and the grid oxic horizon of a Part II the 4th, and the Part II
Four grid oxic horizons are thinner than the grid oxic horizon of Part I the 4th；
Wherein the 3rd grid structure and the 4th grid structure are formed at the 3rd Second-Type doped region and the four the second
The surface between type doped region；
Wherein, the first type region, the 3rd Second-Type doped region, the grid oxic horizon of Part I the 3rd and the 3rd grid
One the 3rd switching transistor that pole layer is formed in one the 3rd memory cell；The first type region, the gate oxidation of Part II the 3rd
One the 3rd storage transistor that layer is formed in the 3rd memory cell with the 3rd grid layer, the gate terminal of the 3rd switching transistor
First word-line is connected to, the first source/drain terminal of the 3rd switching transistor is connected to a second bit line, the 3rd switch
Second source/drain terminal of transistor is connected to the first source/drain terminal of the 3rd storage transistor, and the second of the 3rd storage transistor
Source/drain terminal is suspension joint, and the gate terminal of the 3rd storage transistor is connected to first word-line；
Wherein, the first type region, the 4th Second-Type doped region, the grid oxic horizon of Part I the 4th and the 4th grid
One the 4th switching transistor that pole layer is formed in one the 4th memory cell；The first type region, the gate oxidation of Part II the 4th
One the 4th storage transistor that layer is formed in the 4th memory cell with the 4th grid layer, the gate terminal of the 4th switching transistor
Second word-line is connected to, the first source/drain terminal of the 4th switching transistor is connected to the second bit line, the 4th switch
Second source/drain terminal of transistor is connected to the first source/drain terminal of the 4th storage transistor, and the second of the 4th storage transistor
Source/drain terminal is suspension joint, and the gate terminal of the 4th storage transistor is connected to second word-line；
Wherein, the lower face between the 3rd Second-Type doped region and the 4th Second-Type doped region is one first type
Semiconductor.
13. one-time programming memory as claimed in claim 10, wherein the first grid structure and the second grid structure it
Between the lower face be one first type heavily doped region.
14. one-time programming memory as claimed in claim 10, wherein the first type region are one first type substrate or one
First type well area.
15. one-time programming memory as claimed in claim 10, wherein first clearance wall weigh each other with second clearance wall
It is folded.
16. one-time programming memory as claimed in claim 15, wherein overlapping first clearance wall and second clearance wall
Width be less than the width of the three times second grid structures.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103109339 | 2014-03-14 | ||
| TW103109339A TWI543302B (en) | 2014-03-14 | 2014-03-14 | One time programming memory and associated memory cell structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104916638A CN104916638A (en) | 2015-09-16 |
| CN104916638B true CN104916638B (en) | 2017-11-28 |
Family
ID=54085574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410164447.2A Expired - Fee Related CN104916638B (en) | 2014-03-14 | 2014-04-22 | One-time programming memory |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104916638B (en) |
| TW (1) | TWI543302B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230327671A1 (en) * | 2022-04-11 | 2023-10-12 | Ememory Technology Inc. | Voltage level shifter and operation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
| CN101361139A (en) * | 2005-08-05 | 2009-02-04 | 飞思卡尔半导体公司 | One time programmable memory and method of operation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7045425B2 (en) * | 2004-06-30 | 2006-05-16 | Texas Instruments Incorporated | Bird's beak-less or STI-less OTP EPROM |
| US8482952B2 (en) * | 2011-02-17 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | One time programming bit cell |
-
2014
- 2014-03-14 TW TW103109339A patent/TWI543302B/en not_active IP Right Cessation
- 2014-04-22 CN CN201410164447.2A patent/CN104916638B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101361139A (en) * | 2005-08-05 | 2009-02-04 | 飞思卡尔半导体公司 | One time programmable memory and method of operation |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI543302B (en) | 2016-07-21 |
| TW201535611A (en) | 2015-09-16 |
| CN104916638A (en) | 2015-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9401209B2 (en) | Three-dimensional semiconductor memory device | |
| TW475267B (en) | Semiconductor memory | |
| US20170365340A1 (en) | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating | |
| CN108807388A (en) | The non-volatile memory cells of write-in efficiency can be improved | |
| CN103811496B (en) | For the method and apparatus with the non-volatile memory cells improving programming efficiency | |
| CN100456479C (en) | Anti-fuse once-programmable nonvolatile memory unit and method for manufacture and programming thereof | |
| US9224743B2 (en) | Nonvolatile memory device | |
| EP0915479A2 (en) | Nonvolatile semiconductor memory device and method of reading data therefrom | |
| CN102315174B (en) | SONOS flash memories containing separate gate structures and preparation method thereof, operational approach | |
| CN106340517B (en) | One-time programming non-volatile holographic storage born of the same parents | |
| CN102386188A (en) | Memory architecture of 3D array with diode in memory string | |
| CN109817624A (en) | Memory and its operating method | |
| TW201401489A (en) | Memory cell comprising first and second transistors and methods of operating | |
| CN110137173A (en) | Memory and its operating method | |
| CN104091801B (en) | Storage cell array, formation method of storage cell array and drive method of storage cell array | |
| CN208752963U (en) | Electrically erasable nonvolatile memory device and electronic equipment | |
| CN104916638B (en) | One-time programming memory | |
| CN207852676U (en) | Storage component part | |
| CN103377700A (en) | Methods and apparatus for non-volatile memory cells | |
| JP2008118040A (en) | Nonvolatile semiconductor storage device, manufacturing method thereof, and information writing method using the same | |
| US10797063B2 (en) | Single-poly nonvolatile memory unit | |
| CN100423272C (en) | Semiconductor storage device and its operating method,semiconductordevice and portable electronic device | |
| CN106205715B (en) | The operating method of flash memory | |
| CN104037174B (en) | memory array of mixed structure and preparation method thereof | |
| CN104778977B (en) | One-time programming memory and related memory cell structure thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171128 Termination date: 20190422 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |