CN104901692B - Phaselocked loop with protection circuit - Google Patents
Phaselocked loop with protection circuit Download PDFInfo
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Abstract
The present invention proposes a kind of phaselocked loop with protection circuit, including the first programmable feedback frequency divider and voltage controlled oscillator, and protection circuit includes frequency divider, the second programmable feedback frequency divider, phase inverter, counter, trigger and automatic controller；Fraction frequency device input end is electrically connected with the first programmable frequency divider input terminal；Output terminal is electrically connected with the second programmable feedback fraction frequency device input end；Second programmable feedback frequency divider output terminal is electrically connected with inverter input and trigger clock end respectively；Inverter output is electrically connected with counter resets end, and counter clock end is electrically connected with the second programmable frequency divider output terminal；Counter output is electrically connected with trigger input terminal；Trigger output terminal is electrically connected with the automatic controller input terminal；Automatic controller output terminal is electrically connected with voltage controlled oscillator control terminal.The present invention uses digital protection circuit, reduces phaselocked loop power consumption, has saved circuit manufacture cost.
Description
Technical field
The present invention relates to phaselocked loop application field, specifically, is related to a kind of phaselocked loop with protection circuit.
Background technology
Phaselocked loop utilizes the frequency of external input signal control loop internal signal as a kind of typical feedback control circuit
Rate and phase, and then realize output signal frequency to frequency input signal from motion tracking.Therefore, phaselocked loop it is more and more by with
Do the frequency synthesizer of field of video monitoring and the composition device of clock generator.Fig. 1 is a kind of knot of existing phaselocked loop
Structure schematic diagram.In the phaselocked loop, two input terminals of phase frequency detector 11 receive reference clock signal INCLK and feedback letter respectively
Number FBCLK, is added to charge pump 12 after calculating difference and controls to adjust wave filter 13 and voltage controlled oscillator 14 by charge pump 12.Pressure
Control oscillator 14 is according to the frequency signal VCOCLK corresponding with the voltage output that the adjusting of wave filter 13 obtains of charge pump 12, the signal
Preposition feedback divider 15 is passed sequentially through, generation PREFBCLK signals are loaded by programmable feedback frequency divider 16 and finally afterwards
To 11 input terminal of phase frequency detector.
It is immediate in the prior art, phaselocked loop protection circuit include edge detection unit, timer, delay unit and
Voltage clamp unit.Wherein, edge detection unit is by using seven NOT gates and a NAND gate connection composition；Timer uses
One PMOS tube, four NMOS tubes and a capacitance composition；Delay unit is made of a Schmidt trigger；Voltage clamp list
Member is made of two NMOS tubes.
But the prior art is there is also a degree of deficiency, since phaselocked loop protection circuit is mainly using extensive simulation electricity
Road is realized, thus causes circuit area big, and power consumption is high；And with the increase of number of devices, the manufacture cost of the protection circuit
Also it is higher and higher.
The content of the invention
The deficiency for more than, the present invention propose a kind of phaselocked loop with protection circuit, solve original protection circuit
In, it is high that analog circuit area in turn results in greatly protection circuit power consumption, it is of high cost the problem of.
In order to realize above-mentioned technical proposal, the present invention provides a kind of phaselocked loop with protection circuit, including, first can
Feedback divider and voltage controlled oscillator are programmed, wherein the protection circuit includes frequency divider, the second programmable feedback frequency divider, anti-
Phase device, counter, trigger and automatic controller；
Wherein, the input terminal of the frequency divider is electrically connected electrical connection with the input terminal of first programmable frequency divider, uses
In the output signal for receiving preposition feedback divider；
The output terminal of the frequency divider is electrically connected with the input terminal of the second programmable feedback frequency divider；
The output terminal of the second programmable feedback frequency divider input terminal with the phase inverter and the trigger respectively
Clock end electricity be electrically connected；
The output terminal of the phase inverter is electrically connected with the reset terminal of the counter, and the clock end of the counter with
The first programmable feedback frequency divider output terminal is electrically connected；
The output terminal of the counter is electrically connected with the input terminal of the trigger；
The output terminal of the trigger is electrically connected with the input terminal of the automatic controller；
The output terminal of the automatic controller is electrically connected with the control terminal of voltage controlled oscillator, for adjusting the voltage controlled oscillation
The output signal of device.
Further, the phaselocked loop further includes phase frequency detector, charge pump, wave filter and preposition feedback divider；
The phase frequency detector includes first input end and the second input terminal, wherein the first input end and external crystal-controlled oscillation
It is electrically connected, second input terminal is electrically connected with the output terminal of the first programmable feedback frequency divider；
The output terminal of the phase frequency detector is electrically connected with the input terminal of the charge pump；
Input terminal of the output terminal of the charge pump respectively with the wave filter and voltage controlled oscillator is electrically connected；
The output terminal of the voltage controlled oscillator is electrically connected with the preposition feedback divider input terminal；
Input terminal of the output terminal of the preposition feedback divider respectively with the first programmable feedback frequency divider is electrically connected
Connect；
The output terminal of the first programmable feedback frequency divider is electrically connected with the second input terminal of the phase frequency detector.
Further, the first input end of the phase frequency detector is electrically connected with external crystal-controlled oscillation, for receiving reference clock
Signal；Second input terminal is electrically connected with the output terminal of the first programmable feedback frequency divider, for receiving feedback signal；
The output terminal of the phase frequency detector is reference clock signal and the phase difference value signal of feedback signal.
Further, the charge pump receives the phase difference value signal, and is adjusted jointly with the wave filter, described
When phase difference value signal is zero, control voltage signal is exported to the input terminal of the voltage controlled oscillator.
Further, the phase inverter is delay phase inverter.
Further, the delay phase inverter is used to receive the signal after frequency dividing, and passes through after reverse operating, as multiple
Reset terminal of the position signal loading to the counter.
Further, the trigger is d type flip flop.
Further, the wave filter is low-pass filter.
The present invention avoids phase-locked loop circuit and is absorbed in and collapse by adding digital protection circuit to existing phase-locked loop circuit
The pattern of bursting, simultaneously because the composition of protection circuit is digital circuit device, thus reduces the quantity of device, reduces circuit
Power consumption, while reduce the cost of circuit manufacture.
Brief description of the drawings
Fig. 1 is a kind of structure diagram of phaselocked loop in the prior art.
Fig. 2 is a kind of structural representation with protection circuit in the phaselocked loop for protecting circuit provided in an embodiment of the present invention
Figure.
Fig. 3 is a kind of phase-locked loop structures schematic diagram with protection circuit provided in an embodiment of the present invention.
Fig. 4 is a kind of phaselocked loop voltage controlled oscillator curve map with protection circuit provided in an embodiment of the present invention.
Fig. 5 is a kind of phaselocked loop wave simulation figure with protection circuit provided in an embodiment of the present invention.
Fig. 6 is a kind of phaselocked loop protection circuit waveform analogous diagram with protection circuit provided in an embodiment of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
It illustrate only part related to the present invention rather than full content in description, attached drawing.
Embodiment one
Fig. 2 is a kind of structural representation with protection circuit in the phaselocked loop for protecting circuit provided in an embodiment of the present invention
Figure.
Fig. 3 is a kind of phase-locked loop structures schematic diagram with protection circuit provided in an embodiment of the present invention.
As described in Fig. 2 and Fig. 3, a kind of phaselocked loop with protection circuit, it is characterised in that the phaselocked loop includes first
Programmable feedback frequency divider 110 and voltage controlled oscillator 120, protection circuit 130 include frequency divider 131, the second programmable feedback point
Frequency device 132, phase inverter 133, counter 134, trigger 135 and automatic controller 136；
Wherein, the input terminal of frequency divider 131 is electrically connected electrical connection with the input terminal of first programmable frequency divider 110,
For receiving the output signal PREFBCLK of preposition feedback divider 170；
The output terminal of frequency divider 131 is electrically connected with the input terminal of the second programmable feedback frequency divider 132；
The output terminal of second programmable feedback frequency divider 132 respectively with the input terminals of 133 phase inverters and trigger 135 when
Zhong Duan electricity is electrically connected；
The output terminal of phase inverter 133 is electrically connected with the reset terminal of counter 134, and the clock end of counter 134 and the
One programmable feedback frequency divider, 110 output terminal is electrically connected；
The output terminal of counter 134 is electrically connected with the input terminal of trigger 135；
The output terminal of trigger 135 is electrically connected with the input terminal of automatic controller 136；
The output terminal of automatic controller 136 is electrically connected with the control terminal of voltage controlled oscillator 120, for adjusting described voltage-controlled shake
Swing the output signal of device.
When 120 output voltages of voltage controlled oscillator-frequency signal is to circuit is protected, since signal frequency is excessive, first
Need to carry out frequency reducing to signal.It is to be herein pointed out preposition feedback divider 170 only exists in off position at this time, and
It is not to disconnect.After signal PREFBCLK is exported by frequency divider 131, frequency can drop to the half of original frequency.Believe afterwards
Number can be by the second programmable feedback frequency divider 132, and export as the signal of protection circuit normal operating frequency range.
It is worth noting that, the second programmable feedback frequency divider 132 is adjusted by external, programmable controller, into
And required frequency signal can be exported.
Two strands are classified into from the signal DIVCLK of the second programmable feedback frequency divider 132 output：
The input terminal of one access phase inverter 133, since the phase inverter 133 is delay phase inverter, can export one
Slightly postpone on clock and the reverse signal opposite with original signal, the reverse signal can access the reset terminal of counter 134
Reset signal as counter 134；
Another burst of clock end that can access trigger 135 and then as the clock signal of trigger.
It is worth noting that, the signal DIVCLK of the second programmable feedback frequency divider 132 output believes for low duty ratio clock
Number.So-called low duty ratio refers in clock signal period that the clock cycle is shorter shared by high level.It is, therefore, to be understood that access is touched
The clock signal for sending out the clock end of device 135 is low duty ratio signal, and is loaded into 134 reset terminal of counter by phase inverter 133
Reset signal for slightly postpone high duty ratio signal.
134 reset terminal of counter is effective for low level, and clock end is effective for high level.It is 0 when reset terminal inputs, output terminal
COUT is 0；When reset terminal is 1, clock end 0, output terminal COUT is 0；When reset terminal be 1, clock end 1, output terminal COUT
For 1.
Trigger 135 is d type flip flop, and rising edge is effective.When clock is in rising edge, d type flip flop output signal is
COUT signal values.
Therefore, the course of work between phase inverter 133, counter 134 and trigger three is such：
When the signal DIVCLK of the second programmable feedback frequency divider 132 output is in rising edge, trigger 135, which is in, to be touched
Hair-like state, at this time, the reset terminal received signal of counter 134 are then the signals after 133 revertive delay of phase inverter
DIVCLK, therefore, the signal of reset terminal is in high level and will enter lower jump edge at this time.
If phaselocked loop does not collapse at this time, i.e. the first programmable feedback frequency divider 110 output signal FBCLK outputs are being counted
In the collectable scope of number 134 clock end of device, when the signal of reset terminal is in high level, then counter 134 exports signal COUT
For 1.And the state will be maintained to the upper jump edge of signal DIVCLK following clock cycles always.
When signal DIVCLK following clock cycles upper jump along when, trigger output signal DET_SIGNAL be high level.
If phaselocked loop collapses at this time, i.e. the first programmable feedback frequency divider 110 output signal FBCLK output frequencies are not
In the collectable scope of 134 clock end of counter, when the signal of reset terminal is in high level, then counter 134 exports signal
COUT is 0.
When signal DIVCLK following clock cycles upper jump along when, trigger 135 export signal DET_SIGNAL be low electricity
It is flat.
Since automatic controller 136 is low level triggering, when signal DET_SIGNAL is low level, signal triggering is opened
Dynamic automatic controller 136 and then adjusting voltage controlled oscillator output frequency.
The present embodiment by using frequency divider, the second programmable feedback frequency divider, phase inverter, counter, trigger and from
Movement controller forms protection circuit devcie, effectively inhibits phaselocked loop collapse pattern occur, while reduces the power consumption of device,
Cost is saved.
Embodiment two
The present embodiment analyzes the phase-locked loop operation state with protection circuit on the basis of embodiment one.
As described in Fig. 3, the first programmable feedback frequency divider 110 and voltage controlled oscillation that phaselocked loop is mentioned except embodiment is a kind of
Device 120, protection circuit 130 further include phase frequency detector 140, charge pump 150, wave filter 160 and preposition feedback divider 170；
Phase frequency detector 140 includes first input end and the second input terminal, wherein first input end and the electricity of external crystal-controlled oscillation 180
Connection, the second input terminal are electrically connected with the output terminal of the first programmable feedback frequency divider 110；
The output terminal of phase frequency detector 140 is electrically connected with the input terminal of charge pump 150；
Input terminal of the output terminal of charge pump 150 respectively with wave filter 160 and voltage controlled oscillator 20 is electrically connected；
The output terminal of voltage controlled oscillator 120 is electrically connected with preposition 170 input terminal of feedback divider；
Input terminal of the output terminal of preposition feedback divider 170 respectively with the first programmable feedback frequency divider 110 is electrically connected；
The output terminal of first programmable feedback frequency divider 110 is electrically connected with the second input terminal of phase frequency detector 140.
And then the course of work of phaselocked loop is as follows：
The first input end of phase frequency detector 140 is electrically connected with external crystal-controlled oscillation 180, for receiving reference clock signal
INCLK；Second input terminal is electrically connected with the output terminal of the first programmable feedback frequency divider 110, for receiving feedback signal.
The feedback signal exports signal FBCLK for the first programmable feedback frequency divider 110, and output signal FBCLK is accessed at the same time
Counter 134.
The effect of phase frequency detector 140 is by reference clock signal INCLK compared with exporting signal FBCLK, and
And the output terminal of phase frequency detector 140 is reference clock signal INCLK and the phase difference value signal for exporting signal FBCLK.The phase
Potential difference value signal is used for the working status for adjusting charge pump 150 and wave filter 160.
It is worth noting that, wave filter 160 is low-pass filter, which allows the signal less than cutoff frequency to lead to
Cross, and there is energy storage.
When phase frequency detector 140 detects reference clock signal INCLK phases prior to output signal FBCLK, charge pump
150, which output current to wave filter 160, charges it；
When phase frequency detector 140 detects reference clock signal INCLK phases when signal FBCLK is exported, wave filter
160 pairs of charge pumps 150 discharge.
When reference clock signal INCLK phases with output signal FBCLK phases it is consistent when, just produce voltage signal export to
The input terminal of voltage controlled oscillator 120.
Voltage controlled oscillator 120 is an oscillating circuit with input voltage and output frequency correspondence, therefore, to defeated
The change of output frequency can be caused by entering the adjusting of magnitude of voltage.
The output signal of voltage controlled oscillator 120 is the output signal VCOCLK of phaselocked loop.The output signal at the same time
VCOCLK is also sequentially ingressed into preposition feedback divider 170, produces signal PREFBCLK, then pass through the first programmable feedback frequency divider
110, and finally access the second input terminal of phase frequency detector 140.
The effect of preposition 170 and first programmable feedback frequency divider 110 of feedback divider is the output letter to phaselocked loop
Number carry out frequency reducing, to meet the needs of some devices in phaselocked loop.
But it is related to a problem at this time, frequency reducing is carried out in the high frequency output signal to 120 initialization of voltage controlled oscillator
When, it may be desirable to preposition feedback divider 170 is closed, but this mode can influence the first programmable feedback frequency divider 110 to high frequency
The processing of signal is exported, because the frequency values of high frequency output signal at this time are beyond the first programmable feedback frequency divider 110
Disposal ability.Therefore, the output of the first programmable feedback frequency divider 110 is DC level, and thus causes phase frequency detector
140th, charge pump 150 and the processing of low-pass filter 160 and output HIGH voltage value is to improve the output frequency of voltage controlled oscillator 120.
Such result has resulted in the endless loop of phaselocked loop, and is absorbed in collapse pattern.
The effect for adding protection circuit is exactly to be when the output signal of voltage controlled oscillator 120 passes through preposition feedback divider
Output is PREFBCLK signals after 170, if preposition feedback divider 170 is closed at this time, protects the frequency dividing in circuit
131 and second programmable feedback frequency divider 132 of device can ensure the output signal of voltage controlled oscillator 120 being down to protection circuit
130 frequency ranges that can be worked.Description has been made in the working status embodiment one of other devices in protection circuit 130,
It is not repeated herein.
When phaselocked loop enters collapse pattern, protect in circuit 130 d type flip flop output signal DET_SIGNAL for low level simultaneously
Automatic controller (AOC) 136 is triggered to start.The frequency range of the signal of the output of voltage controlled oscillator 120 at this time is as shown in Figure 4.
As shown in Figure 4,120 output frequency of voltage controlled oscillator can be combined to 8 curves (Curve1-Curve8), and 8
Curve has lap, and then ensures the continuity of whole frequency range, and the frequency of Curve1 is minimum, if entering collapse shape
State, DET_SIGNAL can be by 120 forced workings of voltage controlled oscillator in Curve1, until jumping out collapse conditions, DET_SIGNAL is returned
Multiple high potential state.
Fig. 5 is a kind of phaselocked loop wave simulation figure with protection circuit provided in an embodiment of the present invention.Left side is in figure
The voltage axis of waveform, right side are time shaft.As shown in Figure 5, when preposition feedback divider 170 is closed, due to voltage-controlled
The signal frequency that oscillator 120 exports is excessive, more than the disposal ability of the first programmable feedback frequency divider 110, exports signal
FBCLK is continuously DC level, and phaselocked loop enters collapse pattern.
Fig. 6 is a kind of phaselocked loop protection circuit waveform analogous diagram with protection circuit provided in an embodiment of the present invention.Figure
Middle left side is the voltage axis of waveform, and right side is time shaft.And AOC<2>For AOC<1>Two divided-frequency signal, AOC<1>For AOC<
0>Two divided-frequency signal.Thus, the 136 low level working time of automatic controller is increasingly longer, until phaselocked loop jumps out collapse
State.
Under collapse conditions, after being resetted due to counter 134, the saltus step less than output signal FBCLK, counter are counted
134 output signal COUT are continuously low level in DIVCLK high level sections, and it is low that trigger 135 exports signal DET_SIGNAL appearance
Level signal, 120 output frequency of voltage controlled oscillator is forced to be withdrawn into first curve Curve1 of low-limit frequency scope, until
DET_SIGNAL returns high level signal, and phaselocked loop reenters normal operating conditions.By simulation waveform it can be seen that, it is only necessary to
Two FBCLK clock cycle, phaselocked loop can jump out collapse conditions, restart to lock.
The present invention protects circuit by using digital circuit device as phaselocked loop, and then avoids phase-locked loop circuit and be absorbed in
Collapse pattern, simultaneously because the composition of protection circuit is digital circuit device, thus reduces the quantity of device, reduces circuit
Power consumption, while reduce circuit manufacture cost.
It is worth noting that, the above is only the preferred embodiment of the present invention, it is noted that for the art
Those of ordinary skill for, the equivalent variations made on the premise of the design of the principle of the invention and principle is not departed from, modification
With combination, it is within the scope of protection of the invention.
Claims (8)
1. a kind of phaselocked loop with protection circuit, it is characterised in that the phaselocked loop includes the first programmable feedback frequency divider
And voltage controlled oscillator, protection circuit include frequency divider, the second programmable feedback frequency divider, phase inverter, counter, trigger and from
Movement controller；
Wherein, the input terminal of the frequency divider is electrically connected with the input terminal of first programmable frequency divider, preposition for receiving
The output signal of feedback divider；
The output terminal of the frequency divider is electrically connected with the input terminal of the second programmable feedback frequency divider；
The output terminal of the second programmable feedback frequency divider respectively with the input terminal of the phase inverter and the trigger when
Clock end is electrically connected；
The output terminal of the phase inverter is electrically connected with the reset terminal of the counter, and the clock end of the counter with it is described
First programmable feedback frequency divider output terminal is electrically connected；
The output terminal of the counter is electrically connected with the input terminal of the trigger；
The output terminal of the trigger is electrically connected with the input terminal of the automatic controller；
The output terminal of the automatic controller is electrically connected with the control terminal of voltage controlled oscillator, for adjusting preposition feedback divider
Export signal.
2. the phaselocked loop with protection circuit according to claim 1, it is characterised in that the phaselocked loop further includes phase frequency
Detector, charge pump, wave filter and preposition feedback divider；
The phase frequency detector includes first input end and the second input terminal, wherein the first input end is electrically connected with external crystal-controlled oscillation
Connect, second input terminal is electrically connected with the output terminal of the first programmable feedback frequency divider；
The output terminal of the phase frequency detector is electrically connected with the input terminal of the charge pump；
Input terminal of the output terminal of the charge pump respectively with the wave filter and voltage controlled oscillator is electrically connected；
The output terminal of the voltage controlled oscillator is electrically connected with the preposition feedback divider input terminal；
The output terminal of the preposition feedback divider is electrically connected with the input terminal of the first programmable feedback frequency divider；
The output terminal of the first programmable feedback frequency divider is electrically connected with the second input terminal of the phase frequency detector.
3. the phaselocked loop with protection circuit according to claim 2, it is characterised in that the first of the phase frequency detector
Input terminal is electrically connected with external crystal-controlled oscillation, for receiving reference clock signal；Second input terminal and first programmable feedback point
The output terminal of frequency device is electrically connected, for receiving feedback signal；
The output terminal of the phase frequency detector is reference clock signal and the phase difference value signal of feedback signal.
4. the phaselocked loop with protection circuit according to claim 3, it is characterised in that the charge pump receives the phase
Potential difference value signal, and adjusted jointly with the wave filter, when the phase difference value signal is zero, control voltage signal is exported
To the input terminal of the voltage controlled oscillator.
5. the phaselocked loop with protection circuit according to claim 1, it is characterised in that the phase inverter is anti-phase to postpone
Device.
6. the phaselocked loop with protection circuit according to claim 5, it is characterised in that the delay phase inverter is used to connect
Signal after contracture frequency, and by after reverse operating, the reset terminal of the counter is loaded into as reset signal.
7. the phaselocked loop with protection circuit according to claim 1, it is characterised in that the trigger is d type flip flop.
8. the phaselocked loop with protection circuit according to claim 4, it is characterised in that the wave filter is low-pass filtering
Device.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577544A (en) * | 2009-06-15 | 2009-11-11 | 华亚微电子（上海）有限公司 | Phase-locked loop with collapse protection mechanism |
| CN102361456A (en) * | 2011-10-26 | 2012-02-22 | 华亚微电子（上海）有限公司 | Clock phase alignment and adjustment circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7023250B2 (en) * | 2004-01-14 | 2006-04-04 | Intersil Americas Inc. | Programmable bandwidth during start-up for phase-lock loop |
| US9766649B2 (en) * | 2013-07-22 | 2017-09-19 | Nvidia Corporation | Closed loop dynamic voltage and frequency scaling |
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- 2015-06-17 CN CN201510338707.8A patent/CN104901692B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577544A (en) * | 2009-06-15 | 2009-11-11 | 华亚微电子（上海）有限公司 | Phase-locked loop with collapse protection mechanism |
| CN102361456A (en) * | 2011-10-26 | 2012-02-22 | 华亚微电子（上海）有限公司 | Clock phase alignment and adjustment circuit |
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Effective date of registration: 20200401 Address after: 215634 north side of Chengang road and west side of Ganghua Road, Jiangsu environmental protection new material industrial park, Zhangjiagang City, Suzhou City, Jiangsu Province Patentee after: ZHANGJIAGANG KANGDE XIN OPTRONICS MATERIAL Co.,Ltd. Address before: 201203, room 5, building 690, No. 202 blue wave road, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: WZ TECHNOLOGY Inc. |