CN104901656B - The method and its device of digital filtering Key dithering - Google Patents
The method and its device of digital filtering Key dithering Download PDFInfo
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Abstract
The present invention provides a kind of method and its device of digital filtering Key dithering, the method includes：The burr in clock input signal is filtered out, corresponding initial clock output signal is generated, wherein the clock input signal includes the first clock input signal and second clock input signal；By the initial clock output signal reverse phase operation, the first clock output signal and second clock output signal are generated；According to first clock output signal of feedback and second clock output signal level height, be turned on or off corresponding switch, it is connected to the corresponding clock input signal of trigger, filters out the shake in first clock input signal or/and the second clock input signal.The present invention realizes filtering and the Key dithering of clock input signal, and during digital filtering, can also filter out the burr of input signal generation；The structure of the present apparatus is simple, low in energy consumption, and is easily achieved, and can not only realize filtering and Key dithering, also increase the load capacity of device.
Description
Technical field
The present invention relates to the technical fields that integrated circuit intersects with interface, and debounce is realized more particularly to using digital filtering
Dynamic method and its device.
Background technology
In integrated circuits, not only crystal oscillator can generate clock signal, can also be generated using digital oscillator
Clock signal, still, the clock signal generated using oscillator will produce the non-ideal waves such as burr, shake in some cases
Shape.In physical interface application, due to mechanical and physical property, for example, during the opening and closing of physical switch, can all it generate
Nonideal shake or burr need to dispose specific circuit, and eliminating above-mentioned nonideal burr influences.
In the prior art, generally use analogue filter circuit eliminates burr or shake.However, analogue filter circuit reaches
Said effect is bad.The reason is that：Analogue filter circuit not only designs complex, but also power consumption and area are all larger.
Therefore, it is necessary to a kind of new filter circuits to eliminate shake and burr to reach.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of sides of digital filtering Key dithering
Method and its device use analogue filter circuit Key dithering or burr in the prior art for solving, because design difficulty is big, power consumption
High, area reaches greatly ineffective problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of method of digital filtering Key dithering, including：
The burr in clock input signal is filtered out, corresponding initial clock output signal is generated, wherein the clock input letter
Number include the first clock input signal and second clock input signal；
By the initial clock output signal reverse phase operation, generates the first clock output signal and believe with second clock output
Number；
According to first clock output signal of feedback and second clock output signal level height, on-off is led
Open corresponding switch, the corresponding clock input signal of connection trigger filters out first clock input signal or/and described the
Shake in two clock input signals.
Preferably, the filtering device of the burr uses trigger.
Preferably, described by the initial clock output signal reverse phase operation, generate the first clock output signal and second
Clock output signal specifically includes：
The initial clock output signal generated is handled using phase inverter, wherein the phase inverter includes the second reverse phase
Device and the first phase inverter, the initial clock output signal circulation second phase inverter, generate second clock output signal；Institute
Second clock output signal circulation first phase inverter is stated, first clock output signal is generated.
Preferably, first clock output signal according to feedback and the second clock output signal level are high
Low, be turned on or off corresponding switch, filters out trembling in first clock output signal or the second clock output signal
It is dynamic, it specifically includes：
First clock output signal and the second clock output signal are the opposite clock output signal of level, institute
State the clock signal that second clock input signal is the first clock input signal inverse delayed output；
When first clock output signal is high level, the second clock output signal is low level, conducting pair
Connecting valve is answered, the second clock input signal is connected to, filters out the shake in the second clock input signal；
When the second clock output signal is high level, first clock output signal is low level, conducting pair
Answer connecting valve, and calculate first clock input signal and the second clock input signal, using the result of calculation as when
Clock input signal filters out the shake in the clock input signal.
Another object of the present invention is to provide a kind of devices of digital filtering Key dithering, including：
Clock input signal generator, for generating clock input signal；
Trigger, input terminal connect the clock input signal, filter out the burr of the clock input signal, and generate just
Beginning clock output signal；
Negative circuit, input terminal connect the output end of the trigger, and initial clock output signal reverse phase is generated clock
Output signal；
Feedback control circuit, input terminal connect the output end of the negative circuit, and output end connects the defeated of the trigger
Enter end, according to the clock input signal for controlling the trigger reset end, circulate the trigger and the negative circuit, to disappear
Except the shake in the clock output signal.
Preferably, the trigger is rest-set flip-flop.
Preferably, the clock input signal includes the first clock input signal and second clock input signal, wherein institute
It states and is provided with delay cell between the first clock input signal and the second clock input signal, and the second clock inputs
Signal is the clock signal of the first clock input signal inverse delayed output.
Preferably, first clock input signal be separately connected trigger keep end, NAND gate an input terminal,
The input terminal of second clock input signal connection third phase inverter, the output end connection of the third phase inverter it is described with it is non-
The output end of another input terminal of door, the NAND gate connects the feedback control circuit.
Preferably, the negative circuit includes the first phase inverter and the second phase inverter, wherein the clock output signal packet
Include the first clock output signal and second clock output signal, the input of the output end of the trigger and second phase inverter
End is connected, and exports second clock output signal, and the second defeated clock output signal connects the input terminal of first phase inverter,
Export the first clock output signal.
Preferably, the feedback control circuit includes that the first control switch is switched with the second control, and first control is opened
One end of pass connects the second clock input signal, and the other end of the first control switch connects the reset of the trigger
The control terminal at end, the first control switch connects first clock output signal；One end of the second control switch connects
Connecing the output end of the NAND gate, the other end of the second control switch connects the reset terminal of the trigger, and described second
The control terminal of control switch connects the second clock output signal.
As described above, the method and its device of the digital filtering Key dithering of the present invention, have the advantages that：
By using dagital clock signal as input signal in the present invention, and by inverted logic control trigger, will export
Clock output signal as control signal, corresponding switch is connected, realizes filtering and the Key dithering of clock input signal, and
During digital filtering, the burr of input signal generation can be also filtered out；The structure of the present apparatus is simple, low in energy consumption, and is easy to
It realizes, can not only realize filtering and Key dithering, also increase the load capacity of device.
Description of the drawings
Fig. 1 is shown as a kind of method flow diagram of digital filtering Key dithering in the embodiment of the present invention；
Fig. 2 is shown as a kind of structure diagram of digital filtering Key dithering device in the embodiment of the present invention；
Fig. 3 is shown as in the embodiment of the present invention delay cell sequence diagram in a kind of digital filtering Key dithering device；
Fig. 4 is shown as in the embodiment of the present invention output timing diagram in a kind of digital filtering Key dithering device.
Component label instructions：
1, trigger, 2, negative circuit, 3, feedback control circuit, 4, delay cell.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this explanations by particular specific embodiment below
Content disclosed by book understands other advantages and effect of the present invention easily.
It please refers to Fig.1 to Fig.4.It should be clear that structure, ratio, size etc. depicted in this specification institute accompanying drawings, only to
Coordinate the revealed content of specification, so that those skilled in the art understands and reads, being not limited to the present invention can be real
The qualifications applied, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
It is whole, in the case where not influencing the effect of present invention can be generated and the purpose that can reach, should all fall in disclosed technology
In the range of content can cover.Meanwhile in this specification it is cited as "upper", "lower", "left", "right", " centre " and
The term of " one " etc. is merely convenient to being illustrated for narration, rather than to limit the scope of the invention, relativeness
It is altered or modified, in the case where changing technology contents without essence, when being also considered as the enforceable scope of the present invention.
As shown in Figure 1, for a kind of method flow diagram of digital filtering Key dithering in the embodiment of the present invention, including：
In step S101, the burr in clock input signal is filtered out, generates corresponding initial clock output signal, wherein institute
It includes the first clock input signal and second clock input signal to state clock input signal；
Wherein, the device for filtering out the burr in clock input signal is trigger 1, preferably rest-set flip-flop, is Fig. 1
The Trigger of middle mark.
In step S102, by the initial clock output signal reverse phase operation, the first clock output signal and second is generated
Clock output signal；
Wherein, the initial clock output signal of the generation of the rest-set flip-flop 1 is handled using phase inverter, wherein described
Phase inverter includes the second phase inverter A2 and the first phase inverter A1, the initial clock output signal circulation the second phase inverter A2
Generate second clock output signal Vout_b；The second clock output signal Vout_b circulations the first phase inverter A1 is generated
The first clock output signal Vout.
In step S103, according to the first clock output signal Vout of feedback and the second clock output signal
Vout_b level height, be turned on or off corresponding switch, is connected to 1 corresponding clock input signal of trigger, filters out described the
Shake in the one clock input signal Vout or/and second clock input signal Vout_b.
Wherein, the first clock output signal Vout is that level is opposite with the second clock output signal Vout_b
Clock output signal, the second clock input signal CLK_DB export for the first clock input signal CLK inverse delayeds
Clock signal；
When the first clock output signal Vout is high level, the second clock output signal Vout_b is low electricity
Flat, conducting is correspondingly connected with switch, is connected to the second clock input signal CLK_DB, filters out the second clock input signal
Shake in CLK_DB；
When the second clock output signal Vout_b is high level, the first clock output signal Vout is low electricity
Flat, conducting is correspondingly connected with switch, with calculating the first clock input signal CLK and second clock input signal CLK_
DB filters out the shake in the clock input signal using the result of calculation as clock input signal.
Embodiment 1：
The present invention is using 1 operation principle of trigger, according to trigger 1 to the reset signal and holding end S of its reset terminal R
Holding signal low and high level it is different, the clock input signal to flowing into the trigger 1 is filtered and Key dithering.Specific packet
It includes：
When 1 reset terminal R of the trigger is low level, the initial clock output signal of the trigger 1 is high level,
And the first clock output signal Vout is high level, the second clock output signal Vout_b is low level；Work as institute
State 1 reset terminal R of trigger be high level when, keep end S be low level when, the trigger 1 overturn so that when described first
Clock output signal Vout is low level, and the second clock output signal Vout_b is high level.
Meanwhile when the clock output signal of feedback is input to feedback control circuit 3, controlled by the level height of feedback
The closure of respective switch and disconnection realize that feedback logic carrys out 1 reset terminal of control trigger and keeps end input signal, when described the
Two clock output signal Vout_b are high level, and when the first clock output signal Vout is low level, Vout_b is high electricity
Flat, then switch Vout_b should be connected, connection the first NAND gate Nand1 outputs are 1 reset terminal R input signals of trigger, (its
In, the output signal of the first NAND gate Nand1 is that second clock input signal is after the processing of third phase inverter, then incites somebody to action
Handling result carries out the structure of NAND gate operation with the first clock input signal.)；As the second clock output signal Vout_b
For low level, when the first clock output signal Vout is high level, the second clock input signal CLK_DB is selected to believe
Number it is 1 reset terminal R input signals of trigger, to 1 reset terminal R input signals of control trigger, and then controls output signal, reach
To filtering and shake removal function.
As shown in Fig. 2, for a kind of structure diagram of digital filtering Key dithering device in the embodiment of the present invention, including：
Clock input signal generator, for generating clock input signal；
Trigger 1, input terminal connect the clock input signal, filter out the burr of the clock input signal, and generate
Initial clock output signal；
Wherein, the trigger 1 is rest-set flip-flop 1, and the trigger 1 is second and non-device Nand2 and third and non-device
Nand3 is formed.
Negative circuit 2, input terminal connect the output end of the trigger 1, when initial clock output signal reverse phase is generated
Clock output signal；
Wherein, the negative circuit 2 includes the second phase inverter A2 and the first phase inverter A1, wherein the clock output letter
Number include the first clock output signal Vout and second clock output signal Vout_b, the output end of the trigger 1 with it is described
The input terminal of second phase inverter A2 is connected, and exports second clock output signal Vout_b, the second defeated clock output signal
Vout_b connects the input terminal of the first phase inverter A1, exports the first clock output signal Vout.
Feedback control circuit 3, input terminal connect the output end of the negative circuit 2, and output end connects the trigger 1
Input terminal, according to the clock input signal for controlling 1 reset terminal of trigger, circulate the trigger 1 and the negative circuit
2, to eliminate the shake in the clock output signal.
Wherein, the feedback control circuit 3 includes the first control switch Vout and second controls switch Vout_b, and described the
One end of one control switch Vout connects the second clock input signal, the other end connection of the first control switch Vout
The control terminal of the reset terminal of the trigger 1, the first control switch Vout connects the first clock output signal Vout；
One end of the second control switch Vout_b connects the output end of the NAND gate, and the second control switch Vout_b's is another
One end connects the reset terminal of the trigger 1, and the control terminal connection second clock of the second control switch Vout_b is defeated
Go out signal Vout_b.
As shown in figure 3, for delay cell 4Delay_Cell in a kind of digital filtering Key dithering device in the embodiment of the present invention
Sequence diagram figure,
The clock input signal includes the first clock input signal CLK and second clock input signal CLK_DB, wherein
It is provided with delay cell 4Delay_ between the first clock input signal CLK and the second clock input signal CLK_DB
Cell, and the clock that the second clock input signal CLK_DB is the first clock input signal CLK inverse delayeds output
Signal.
Specifically, the first clock input signal CLK be separately connected trigger 1 keep end, NAND gate Nand1 one
A input terminal, the input terminal of the second clock input signal CLK_DB connection third phase inverters A3, the first phase inverter A1
Output end connect another input terminal of the NAND gate Nand1, the output end of the NAND gate Nand1 connects the feedback
Control circuit 3.
Embodiment 2：
The second clock input signal CLK_DB is the clock of the first clock input signal CLK inverse delayeds output
Signal, the burr Δ t between wherein second clock input signal CLK_DB and the first clock input signal CLK, it is described must
Δ t must be met and be more than zero, and so that second clock input signal CLK_DB is the burr of the first clock input signal CLK
It does not overlap each other.
As shown in figure 4, for output timing diagram in a kind of digital filtering Key dithering device in the embodiment of the present invention,
Embodiment 3：
When it is logic high to input the first clock input signal CLK, delay cell 4Delay_Cell output the
Two clock input signal CLK_DB are logic low, and the first clock output signal Vout is the output letter for filtering out shake
Number.
Assuming that 1 initial output state of the trigger is logical zero, the second phase inverter A2 outputs are logic high,
The first NAND gate Nand1 outputs are connected with the input of trigger 1, and the first NAND gate Nand1 is logic low at this time,
To which the output of forced-triggered device 1 is logic high, it is to patrol to make the second clock output signal of the second phase inverter A2 outputs
Low level is collected, the first clock output signal of the first phase inverter A1 outputs is logic high, and then disconnects described first
The delay cell 4Delay_Cell is exported clock signal by the connection of NAND gate Nand1 and the trigger 1TRIGGER
CLK_DB is connect with the trigger 1TRIGGER so that the output of trigger 1 is maintained logic high；
Assuming that 1 initial output state of the trigger is logic high, at this point, the of the first phase inverter A1 outputs
One clock output signal Vout is logic high, and the delay cell 4Delay_Cell outputs clock CLK_DB is made to be connected to
1 input terminal of trigger, the output of trigger 1 are maintained logic high, to realize when the delay cell 4Delay_Cell is defeated
When to go out clock be logical zero, the first clock output signal Vout of the first phase inverter A1 output is always logic high.
When input clock signal CLK occurs shaking or when burr, the delay cell 4Delay_Cell exports clock
CLK_DB the burr of logic high will occur, since input clock CLK is also logic high at this time so that described first is anti-
Phase device A1 the first clock output signals of output Vout keeps the value before burr, is still logic high, until described first
Clock input signal CLK overturnings are logic low, the second clock input signal of the delay cell 4Delay_Cell outputs
When clock CLK_DB overturnings are logic 1, the first clock output signal Vout overturnings of the first phase inverter A1 outputs are logic
Low level.
In conclusion by using dagital clock signal as input signal in the present invention, and pass through inverted logic control triggering
Corresponding switch is connected using the clock output signal of output as control signal in device 1, realize clock input signal filtering and
Key dithering, and during digital filtering, can also filter out the burr of input signal generation；The structure of the present apparatus is simple, work(
It consumes low, and is easily achieved, can not only realize filtering and Key dithering, also increase the load capacity of device.So effective gram of the present invention
It has taken various shortcoming in the prior art and has had high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of method of digital filtering Key dithering, which is characterized in that including：
The burr in clock input signal is filtered out, corresponding initial clock output signal is generated, wherein the clock input signal packet
The first clock input signal and second clock input signal are included, the second clock input signal is that the first clock input signal is anti-
Phase retardation processing gained；The initial clock output signal reverse phase operation generates second clock output signal, the second clock
The processing of output signal reverse phase generates the first clock output signal；According to first clock output signal and described second of feedback
Clock output signal level height conducting the first control switch or the second control switch；It is touched when the first control switch conduction
The reset terminal for sending out device connects second clock input signal；When the second control switch conduction, the reset terminal of the trigger connects
Output signal of first and second clock input signal through NAND operation is connect, is controlled by the input signal of control trigger reset terminal
The output signal of the trigger is to filter out the shake of the clock input signal.
2. the method for digital filtering Key dithering according to claim 1, which is characterized in that the filtering device of the burr is adopted
Use trigger.
3. the method for digital filtering Key dithering according to claim 1, which is characterized in that the initial clock output signal
Reverse phase operation generates second clock output signal, and the second clock output signal reverse phase processing generates the first clock output signal
The step of, it specifically includes：
Using phase inverter handle generate the initial clock output signal, wherein the phase inverter include the first phase inverter with
Second phase inverter, the initial clock output signal circulation second phase inverter, generates second clock output signal；Described
Two clock output signals circulation, first phase inverter, generates first clock output signal.
4. the method for digital filtering Key dithering according to claim 1, which is characterized in that described according to described the of feedback
One clock output signal is switched with second clock output signal level height conducting the first control switch or the second control；When
The reset terminal of the trigger connects second clock input signal when the first control switch conduction；When second control is opened
The reset terminal for closing trigger when conducting connects output signal of first and second clock input signal through NAND operation, passes through control
The input signal at trigger reset end processed controls the output signal of the trigger to filter out the shake of the clock input signal
The step of, it specifically includes：
First clock output signal and the second clock output signal are the opposite clock output signal of level, described the
Two clock input signals are the clock signal of the first clock input signal inverse delayed output；
When first clock output signal is high level, the second clock output signal is low level, and corresponding connect is connected
The first control switch is connect, the second clock input signal is connected to, filters out the shake in the second clock input signal；
When the second clock output signal is high level, first clock output signal is low level, and corresponding connect is connected
The second control switch is connect, and calculates first clock input signal and the second clock input signal, with the result of calculation
For clock input signal, the shake in the clock input signal is filtered out.
5. a kind of device of digital filtering Key dithering, which is characterized in that including
Clock input signal generator, for generating clock input signal；
One rest-set flip-flop, input terminal connect the clock input signal, filter out the burr of the clock input signal, and raw
At initial clock output signal；
Negative circuit, input terminal connect the output end of the trigger, and it is defeated that initial clock output signal reverse phase is generated clock
Go out signal；
Feedback control circuit, input terminal connect the output end of the negative circuit, and output end connects the input of the trigger
End, according to the first clock output signal of feedback and second clock output signal level height conducting the first control switch or second
Control switch；When the first control switch conduction, the reset terminal of the rest-set flip-flop connects second clock input signal；When
The reset terminal of the rest-set flip-flop connects the first and second clock input signal through NAND operation when the second control switch conduction
Output signal eliminates the clock input come control trigger reset terminal by controlling feedback logic with the input signal at end is kept
Shake in signal.
6. the device of digital filtering Key dithering according to claim 5, which is characterized in that the clock input signal includes
First clock input signal and second clock input signal, wherein first clock input signal and the second clock are defeated
Enter and be provided with delay cell between signal, and the second clock input signal is the first clock input signal inverse delayed
The clock signal of output.
7. the device of digital filtering Key dithering according to claim 6, which is characterized in that first clock input signal
It is separately connected the holding end of trigger, an input terminal of NAND gate, the second clock input signal connects third phase inverter
Input terminal, the output end of the third phase inverter connects another input terminal of the NAND gate, the output of the NAND gate
End connects the feedback control circuit.
8. the device of digital filtering Key dithering according to claim 5, which is characterized in that the negative circuit includes first
Phase inverter and the second phase inverter, wherein the clock output signal includes that the first clock output signal is believed with second clock output
Number, the input terminal of second phase inverter is connected with the output end of trigger, second clock output signal is exported, when described second
Clock output signal connects the input terminal of first phase inverter, exports the first clock output signal.
9. the device of the digital filtering Key dithering according to any one of claim 5 to 8, which is characterized in that described anti-
It includes that the first control switch and the second control switch to present control circuit, when one end of the first control switch connects described second
The other end of clock input signal, the first control switch connects the reset terminal of the trigger, the first control switch
Control terminal connects first clock output signal；One end of the second control switch connects the output end of the NAND gate,
The other end of the second control switch connects the reset terminal of the trigger, and the control terminal of the second control switch connects institute
State second clock output signal.
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| CN105978532B (en) * | 2016-05-19 | 2018-08-24 | 深圳市纳芯威科技有限公司 | A kind of digital filter |
| CN106773974B (en) * | 2016-12-27 | 2019-03-26 | 河南理工大学 | Method for processing jitter switch signal |
| TWI638521B (en) * | 2017-09-19 | 2018-10-11 | 新唐科技股份有限公司 | Clock filter circuit and filtering method |
| CN112688670A (en) * | 2019-10-18 | 2021-04-20 | 意法半导体国际有限公司 | De-jitter circuit with noise immunity and spur event tracking |
| CN112291120B (en) * | 2020-12-29 | 2021-06-15 | 苏州裕太微电子有限公司 | Delay line structure and correction method of delay jitter thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025265A (en) * | 2010-11-16 | 2011-04-20 | 灿芯半导体(上海)有限公司 | Frequency jittering circuit |
| CN102931944A (en) * | 2011-08-12 | 2013-02-13 | 飞思卡尔半导体公司 | Digital burr filter |
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| JP5082574B2 (en) * | 2007-05-07 | 2012-11-28 | 三菱電機株式会社 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025265A (en) * | 2010-11-16 | 2011-04-20 | 灿芯半导体(上海)有限公司 | Frequency jittering circuit |
| CN102931944A (en) * | 2011-08-12 | 2013-02-13 | 飞思卡尔半导体公司 | Digital burr filter |
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