CN104900631B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104900631B CN104900631B CN201410076994.5A CN201410076994A CN104900631B CN 104900631 B CN104900631 B CN 104900631B CN 201410076994 A CN201410076994 A CN 201410076994A CN 104900631 B CN104900631 B CN 104900631B
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Abstract
The forming method of a kind of semiconductor structure and forming method thereof, wherein semiconductor structure includes：Substrate is provided；Buried regions area, the conductive energy in buried regions area are formed in substrate；Etching removes the substrate of segment thickness, and first groove, second groove and the 3rd groove of annular are formed in substrate, and first groove and the 3rd groove are located at the both sides of second groove respectively, and second groove bottom is at least to expose at the top of buried regions area；Form the barrier layer of the full first groove of filling and the 3rd groove；The conductive layer of the full second groove of filling is formed, conductive layer is connected with buried regions area, and the doping type of conductive layer is identical with the doping type in buried regions area；Dopant well is formed in the substrate that conductive layer and buried regions area surround.The present invention stops the diffusion of Doped ions in conductive layer, Doped ions is avoided too close to dopant well, so as to improve the electric property of semiconductor structure and reliability while semiconductor structure noise resisting ability is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture technology, more particularly to semiconductor structure and forming method thereof.
Background technology
, can be high-speed digital circuit with the rapid development of semiconductor technology（DC：Digital Circuit）With high property
Can analog circuit（AC：Analog Circuit）Integrate to form composite signal integrated circuits（IC：Integrated
Circuit）.
But in hydrid integrated circuit, because the switching transient electric current of digital state circuit is larger, disturbance electric charge is formed,
These disturbance electric charges can be coupled into by Semiconductor substrate in the analog circuit of sensitivity, substrate noise is formed, to analog circuit
Semiconductor structure interfere.
Particularly, with semiconductor structure physical dimension continuous diminution, the noise coupling of Semiconductor substrate turned into
The problem of must not thinking little of.
Therefore, the problem of noise resisting ability how research improves semiconductor structure turns into urgent need to resolve.
The content of the invention
The present invention is solved the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, half-and-half led reducing substrate noise
While body structural behaviour influences, the Doped ions of substrate inner conducting layer are avoided to diffuse to undesirable region.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；Institute
State and buried regions area is formed in substrate, the conductive energy in buried regions area, and there are Doped ions in the buried regions area；Etching removes
The substrate of segment thickness, first groove, second groove and the 3rd groove of annular, first ditch are formed in the substrate
Groove and the 3rd groove are located at the both sides of second groove respectively, and second groove bottom is at least exposed at the top of buried regions area；Formation is filled out
Barrier layer full of the first groove and the 3rd groove；Form the conductive layer of the full second groove of filling, the conductive layer
It is connected with buried regions area, and the doping type of the conductive layer is identical with the doping type in buried regions area；In the conductive layer and bury
Dopant well is formed in the substrate that floor area surrounds；Grid structure is formed on the dopant well surface；In the grid structure both sides
Doped region is formed in dopant well, doped region is made annealing treatment.
Optionally, the distance between the distance between the first groove and second groove, the 3rd groove and second groove is
10 angstroms to 1000 angstroms.
Optionally, the second groove bottom is at least to expose to include at the top of buried regions area：Second groove bottom-exposed goes out
At the top of buried regions area；Second groove bottom is located in buried regions area.
Optionally, the second groove bottom is located at buried regions area border.
Optionally, the width of the first groove and the 3rd groove is less than the width of second groove.
Optionally, in addition to step：While the barrier layer for filling the full first groove and the 3rd groove is formed,
Second groove bottom and side wall form separation layer；The separation layer positioned at second groove bottom is removed, exposes second groove bottom
Buried regions area.
Optionally, the material on the barrier layer is silica, silicon nitride or silicon oxynitride.
Optionally, the barrier layer is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.
Optionally, the technological parameter of the chemical vapor deposition method is：Reacting gas includes silicon source gas and oxygen source gas
Body, wherein, silicon source gas is TEOS or SiH4, oxygen source gas O2Or O3, silicon source gas flow is 10sccm to 100sccm, oxygen
Source gas flow is 50sccm to 100sccm, and radio-frequency power is 2000 watts to 4000 watts, and bias power is 1000 watts to 2500
Watt.
Optionally, the bottom of the first groove and the 3rd groove is less than at the top of buried regions area.
Optionally, the first groove, second groove are formed with the 3rd groove in the processing step with along with.
Optionally, the material of the conductive layer is the polysilicon of doping.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate；Buried regions area in substrate, it is described to bury
The conductive energy in floor area, and there are Doped ions in the buried regions area；Annular first groove, the second ditch in substrate
Groove and the 3rd groove, and the first groove and the 3rd groove are located at second groove both sides, and the second groove bottom respectively
At least expose at the top of buried regions area；The barrier layer of the full first groove of filling and the 3rd groove；The full second groove of filling
Conductive layer, the conductive layer is connected with buried regions area, and the doping type of the conductive layer and the doping type phase in buried regions area
Together；The dopant well in substrate surrounded positioned at conductive layer and buried regions area；Grid structure positioned at dopant well surface；Positioned at grid knot
Doped region in the dopant well of structure both sides.
Optionally, the distance between the distance between the first groove and second groove, the 3rd groove and second groove is
10 angstroms to 1000 angstroms.
Optionally, the second groove bottom is at least to expose to include at the top of buried regions area：Second groove bottom-exposed goes out
At the top of buried regions area；Second groove bottom is located in buried regions area.
Optionally, the second groove bottom is located at buried regions area border.
Optionally, the width of the second groove is more than the width of first groove and the 3rd groove.
Optionally, the side wall of the second groove has separation layer.
Optionally, the bottom of the first groove and the 3rd groove is less than at the top of buried regions area.
Optionally, the material on the barrier layer is silica, silicon nitride or silicon oxynitride.
Compared with prior art, technical scheme has advantages below：
The present invention provides a kind of forming method of semiconductor structure, wherein, formed in substrate after buried regions area, etching is gone
Except the substrate of segment thickness, first groove, second groove and the 3rd groove, first groove and the 3rd groove point are formed in substrate
Not Wei Yu second groove both sides, second groove bottom is at least exposed at the top of buried regions area；Conductive layer is formed in second groove
It is connected with buried regions area；Also, the barrier layer of the full first groove of filling and the 3rd groove is formed, the barrier layer stops conductive layer
The Doped ions of bottom are spread to dopant well, and the diffusion zone using conductive layer bottom as the center of circle is strapped within the scope of very little
（Doped ions are only capable of diffusing to barrier layer side-walls）, the Doped ions in conductive layer are prevented too close to dopant well, so as to anti-
Breakdown or punchthrough issues only occur, improve the reliability of semiconductor structure.
Meanwhile the buried regions area of conductive energy is formed in substrate, by applying voltage to buried regions area, improve buried regions area
The potential barrier of carrier in the range of surrounding to substrate so that the noise coupling in substrate, which is difficult to cross the potential barrier to enter, to be mixed
Miscellaneous trap, so as to prevent noise coupling from being had undesirable effect to dopant well, improve the noise resisting ability of semiconductor structure.
Further, the width of second groove is more than the width of first groove and the 3rd groove so that forms filling full first
While the barrier layer of groove and the 3rd groove, separation layer, second groove side-walls are formed in the side wall of second groove and bottom
Separation layer can play the diffusion for stopping conductive layer side-walls Doped ions, so as to further prevent doping in conductive layer from
Son diffuses to undesirable region.
Meanwhile the width of first groove and the 3rd groove be less than second groove width, make barrier layer account for chip area compared with
It is small, meet the development trend of semiconductor miniaturization and miniaturization.
The present invention also provides a kind of structural behaviour superior semiconductor structure, wherein, including the buried regions area in substrate,
First groove, second groove and the 3rd groove in substrate, and first groove and the 3rd groove are located at second groove respectively
Both sides, second groove bottom are at least exposed at the top of buried regions area；The conductive layer of the full second groove of filling, conductive layer and buried regions area phase
Connection, there is dopant well in the substrate that conductive layer and buried regions area surround；When semiconductor structure is in running order, by leading
Electric layer applies voltage to buried regions area, and carrier is described to the potential barrier of buried regions area outer-lining bottom in the range of increase buried regions area surrounds
The increase of potential barrier causes noise diffusion to the ability of dopant well in substrate to reduce, so as to improve the anti-noise acoustic energy of semiconductor structure
Power；Also, first groove and the 3rd groove are located at second groove both sides respectively, and with the full first groove of filling and the 3rd groove
Barrier layer, the barrier layer stops that the Doped ions in conductive layer diffuse to dopant well, prevent in conductive layer Doped ions with
Dopant well hypotelorism, so as to improve the reliability of semiconductor structure and electric property.
Further, the width of second groove is more than the width of first groove and the 3rd groove so that first groove and the 3rd
It is smaller that groove accounts for chip area, i.e. barrier layer accounts for that chip area is smaller so that semiconductor structure meet miniaturization, miniaturization
Development trend.
Further, second groove side wall has separation layer, and the separation layer further prevents conductive layer side-walls from adulterating
The diffusion of ion, so as to further improve the reliability and electric property of semiconductor structure.
Brief description of the drawings
Fig. 1 to Fig. 2 is the cross-sectional view for the semiconductor structure that an embodiment provides；
Fig. 3 to Figure 10 is the cross-sectional view for the formation semiconductor structure process that another embodiment of the present invention provides.
Embodiment
From background technology, the problem of noise resisting ability how research improves device is urgent need to resolve.
To solve the above problems, research discovery is carried out for the forming method of semiconductor structure, in order to improve semiconductor junction
The noise resisting ability of structure, reduce influence of the noise to semiconductor structure performance in substrate, can use on the basis of following structure
Semiconductor structure is formed, refer to Fig. 1：
Including：Substrate 100；Buried regions area 101 in substrate 100, the buried regions area 101 is interior to have Doped ions, and
The 101 conductive energy of buried regions area；Ring-shaped groove in substrate 100, and the ring-shaped groove is located at buried regions area 101
Side wall boundary, the channel bottom expose buried regions area 101；The conductive layer 102 of the full groove of filling, and the conductive layer
102 are connected with buried regions area 101.Include in the step of formation semiconductor structure on the basis of the structure of above-mentioned offer：In conduction
Dopant well 103 is formed in the substrate 100 that floor 102 and buried regions area 101 surround；Follow-up processing step also includes forming source electrode, leakage
Pole, grid structure.
Due to having Doped ions in buried regions area 101, and the Doped ions concentration in buried regions area 101 is much larger than substrate 100
Interior Doped ions concentration, when semiconductor structure is in running order, apply voltage to buried regions area 101, so as to increase buried regions area
101 surround in the range of carrier to the potential barrier of the outer-lining bottom 100 of buried regions area 101 so that in the outer-lining bottom 100 of buried regions area 101
Noise be difficult to go beyond the potential barrier and diffuse into dopant well 103, so as to reduce influence of the substrate noise to semiconductor structure.
The conductive layer 102 is act as：Buried regions area 101 is set to be connected with external voltage by conductive layer 102, so as to carry
Potential barrier of the carrier to the outer-lining bottom 100 of buried regions area 101 in the range of high buried regions area 101 surrounds；Also, pass through conductive layer
102 apply voltages, can improve carrier that conductive layer 102 surrounded to the barrier height of the outer-lining bottom 100 of conductive layer 102, increase
Lateral isolation capacity, further improve the noise resisting ability of device.
In order to reduce influence of the conductive layer 102 to semiconductor structure resistance as far as possible, doping in usual conductive layer 102 from
Sub- content is higher, so as to reduce the resistance of conductive layer 102 as far as possible.
However, in order to reduce influence of the formation process of buried regions area 101 and conductive layer 102 to semiconductor structure as far as possible, bury
Floor area 101 and conductive layer 102 need to be formed before dopant well；Therefore, after buried regions area 101 and conductive layer 102 is formed, half
The formation process of conductor structure can include one or multi-channel thermal anneal process, under thermal anneal process effect, in conductive layer 102
Doped ions spread, and refer to Fig. 2, the side wall of conductive layer 102 can by form barrier layer stop side-walls adulterate from
The diffusion of son；However, because the bottom of conductive layer 102 needs buried regions area 101 to be connected, accordingly, it is difficult to by the bottom of conductive layer 102
Portion forms barrier layer to stop the diffusion of the Doped ions of bottom section；Under thermal anneal process effect, form with conductive layer
102 bottoms are the diffusion zone in the center of circle, because the Doped ions content in conductive layer 102 is high, if doped region and dopant well 103
What is be separated by is excessively near, and when the doping type of dopant well 103 and the doping type difference in buried regions area 101, if 101 external height of buried regions area
Voltage, and when the voltage of dopant well 103 is relatively low, it is likely that cause dopant well 103 breakdown；Or conductive layer 102 and buried regions
Area 101 forms unnecessary electrical connection with other regions, causes degraded performance, the poor reliability of semiconductor structure, or even cause
Semiconductor structure performance failure.
In order to avoid Doped ions have undesirable effect to dopant well 103 in conductive layer 102, can make conductive layer 102 with
The distance of dopant well 103 is set farther out, however, the setting of the distance of conductive layer 102 and dopant well 103 can waste chip farther out
Area, the area of semiconductor structure is caused to become big；And constantly reduced with the characteristic size of semiconductor structure, it is difficult to by making
Conductive layer 102 and the distant method of dopant well 103, it is bad to avoid the Doped ions of conductive layer 102 from causing dopant well 103
Influence.
Therefore, the present invention provides a kind of semiconductor structure and forming method thereof, first groove is formed in second groove both sides
With the 3rd groove, and the barrier layer of the full first groove of filling and the 3rd groove is formed, fill the conductive layer of full second groove, it is described
Barrier layer stops the diffusion of Doped ions in conductive layer, particularly stops the diffusion of conductive layer bottom section Doped ions, so as to
The electric property and reliability of semiconductor structure are improved, and has saved chip area, meets semiconductor miniaturization and miniaturization
Development trend.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Present invention firstly provides a kind of forming method of semiconductor structure, Fig. 3 to Figure 10 is provided in an embodiment of the present invention
Semiconductor structure forms the cross-sectional view of process.
It refer to Fig. 3, there is provided substrate 200；Buried regions area 201 is formed in the substrate 200, the buried regions area 201 has
Electric conductivity, and there are Doped ions in the buried regions area 201.
Specifically, the material of the substrate 200 is the silicon therein one on monocrystalline silicon, polysilicon, non-crystalline silicon or insulator
Kind；The substrate 200 can also be Si substrates, Ge substrates, GeSi substrates or GaAs substrates.
The surface of substrate 200 can also form some epitaxial interface layers or strained layer to improve the electricity of semiconductor structure
Performance.
In the present embodiment, the substrate 200 is Si substrates.In other embodiments of the present invention, substrate can also be to be formed
There is the substrate of device, for example, formed with transistor, electric capacity or resistance etc. in substrate.
The buried regions area 201 is act as：The conductive energy in buried regions area 201, and there is doping in buried regions area 201
Ion, when semiconductor structure is in running order, after applying appropriate voltage to buried regions area 201 so that buried regions area 201 is wrapped
Potential barrier increase of the carrier to the outer-lining bottom 200 of buried regions area 201 in the range of enclosing, so that in the outer-lining bottom 200 of buried regions area 201
Noise coupling the ability of the dopant well that is subsequently formed diffused into across the potential barrier reduce, and then improve semiconductor structure
Noise resisting ability, improve the reliability of semiconductor structure.
As one embodiment, the forming step of the substrate 200 with buried regions area 201 includes：On the surface of substrate 200
Form patterned photoresist layer；Using the patterned photoresist layer as mask, substrate 200 is entered using ion implantation technology
Row ion implanting, and the injection depth of the ion implantation technology is deeper；Remove patterned photoresist layer；Substrate 200 is entered
Row thermal anneal process, active ions injection technology inject the injection ion of substrate 200, form buried regions area 201.
As another embodiment, the forming step of the substrate 200 with buried regions area 201 includes：Initial substrate is provided；
Patterned photoresist layer is formed in the initial substrate surface；Using the patterned photoresist layer as mask, using ion
Injection technology carries out ion implanting to initial substrate, and the injection depth of the ion implantation technology is shallower；Remove patterned
Photoresist layer；Thermal anneal process is carried out to initial substrate, active ions injection technology injects the injection ion of initial substrate, is formed
Buried regions area 201；Semiconductor layer, initial substrate and the common shape of semiconductor layer are formed in the initial substrate surface using epitaxy technique
Into substrate 200.
As other embodiment, the forming step of the substrate 200 with buried regions area 201 includes：Initial substrate is provided；
Patterned photoresist layer is formed in the initial substrate surface；Using the patterned photoresist layer as mask, using ion
Injection technology carries out ion implanting to initial substrate, and the injection depth of the ion implantation technology is shallower；Remove patterned
Photoresist layer；Thermal anneal process is carried out to initial substrate, active ions injection technology injects the injection ion of initial substrate, is formed
Buried regions area 201；Using wafer bonding（wafer bonding）Technique is in initial substrate surface bonding semiconductor layer, initial substrate
Substrate 200 is collectively forming with semiconductor layer.
The doping type in the buried regions area 201 is that n-type doping or p-type are adulterated：The doping type in buried regions area 201 is mixed for N-type
When miscellaneous, the injection ion of ion implantation technology is P, As or Sb；When the doping type in buried regions area 201 is that p-type is adulterated, ion implanting
The injection ion of technique is B, Ga, In.
Fig. 4 is refer to, patterned mask layer 202, the patterned mask layer are formed on the surface of substrate 200
202 define the first groove being subsequently formed, the position of second groove and the 3rd groove and width.
The patterned mask layer 202 has first opening the 203, second opening 204 and the 3rd opening 205, and described the
The position of one opening 203 and width correspond to position and the width for being subsequently formed first groove, the position of the second opening 204 and width
Degree corresponds to position and the width for being subsequently formed second groove, and the 3rd opening 205 corresponds to the position for being subsequently formed the 3rd groove
And width.
In the present embodiment, the material of the mask layer 202 is silicon nitride, forms the work of the patterned mask layer 202
Skill step includes：Formation is covered in the original mask layer on the surface of substrate 200 and the initial lithographic positioned at original mask layer surface
Glue-line；Development treatment is exposed to the initial lithographic glue-line, forms patterned photoresist layer；With the patterned light
Photoresist layer is mask, etches original mask layer, forms the figure with first opening the 203, second opening 204 and the 3rd opening 205
The mask layer 202 of shape.
In other embodiments, the material of patterned mask layer is photoresist.
Fig. 5 is refer to, is mask with the patterned mask layer 202, etching removes the substrate 200 of segment thickness,
First groove 213, the groove 215 of second groove 214 and the 3rd of annular are formed in the substrate 200.
In the present embodiment, the bottom of second groove 214 is located at the side wall boundary in buried regions area 201.
The groove 215 of first groove 213 and the 3rd is located at the both sides of second groove 214 respectively.
Second groove 214 is act as：Conductive layer, the conductive layer and buried regions area are subsequently formed in second groove 214
201 are connected, and also apply voltage, the load for being surrounded buried regions area 201 to buried regions area 201 by conductive layer external voltage to realize
Potential barrier increase of stream to substrate 200, plays antimierophonic effect.
As the above analysis, the bottom of second groove 214 is at least to expose the top of buried regions area 201, so that after
Continue the conductive layer formed in second groove 214 with buried regions area 201 to be connected.As one embodiment, second groove 214
Bottom-exposed goes out the top of buried regions area 201；As another embodiment, the bottom of second groove 214 is located in buried regions area 201.
The groove 215 of first groove 213 and the 3rd is act as：The present embodiment forms in the both sides of second groove 214 respectively
One groove 213 and the 3rd groove 215, subsequently form barrier layer, the barrier layer in the groove 215 of first groove 213 and the 3rd
Play a part of stopping that the inner conducting layer of second groove 214 diffuses to undesirable region, so as to improve the electrical property of semiconductor structure
Energy and reliability.If not forming first groove and the 3rd groove in second groove both sides, formed subsequently in second groove conductive
After layer, the conductive layer can have stronger diffusivity in experience Technology for Heating Processing, and the diffusion of conductive layer can cause semiconductor
Structure occurs avalanche breakdown or unnecessary electrical connection occurs, and causes semiconductor structure degraded performance or even fails.
The position relationship of the groove 215 of first groove 213 and the 3rd needs to meet：Subsequently in the ditch of first groove 213 and the 3rd
The barrier layer formed in groove 215 influences small requirement, therefore, the present embodiment to the electrical connection between conductive layer and buried regions area 201
In, the bottom of the groove 215 of first groove 201 and the 3rd is less than the bottom of buried regions area 201.
Also, because the bottom conductive layer of second groove 214 is connected with buried regions area 201, the side wall of second groove 214 can
Form the barrier layer for stopping the diffusion of conductive layer ion, and the bottom of second groove 214 is with buried regions area 201 because need to be connected, therefore the
The ion diffusion of the conductive layer of the bottom of two groove 214 is to influence the principal element of semiconductor structure performance；In order to avoid the second ditch
The ion of the bottom conductive layer of groove 214 diffuses to undesirable region, the barrier layer bottom in the groove 215 of first groove 213 and the 3rd
With conductive layer bottom flush or below conductive layer bottom, bottom and second groove when the groove 215 of first groove 213 and the 3rd
When 214 tops are flush or below 214 bottom of second groove, the barrier layer in the groove 215 of first groove 213 and the 3rd stops conductive
The ability of leafing son diffusion is optimal.
In the present embodiment, the width of the groove 215 of first groove 213 and the 3rd is less than the width of second groove 214, mainly has
Following benefit：
First, the width of the groove 215 of first groove 213 and the 3rd is less than the width of second groove 214, is subsequently formed filling
During the barrier layer of the full groove 215 of first groove 213 and the 3rd, the barrier layer can also be formed in the bottom of second groove 214
And side wall, so as to form the separation layer positioned at the side wall of second groove 214, the separation layer can also play stop second groove
The effect of the conductive layer diffusion of 214 sidewall areas, and conductive layer is re-formed after removing the separation layer of the bottom of second groove 214,
The conductive layer still can be connected with buried regions area 201；Secondly, the groove 215 of first groove 213 and the 3rd accounts for semiconductor structure
Area is small, has saved chip area.
The distance between the first groove 213, the groove 215 of second groove 214 and the 3rd and first groove 213
Width, the width of second groove 214, the width of the 3rd groove 215 can determine according to actual process needs.Extended meeting is formed and filled out afterwards
Barrier layer full of the groove 215 of first groove 213 and the 3rd, the conductive layer of full second groove 214 is filled, is had in conductive layer easy
The Doped ions of diffusion（Under thermal processes act, the diffusion zone using conductive layer bottom as the center of circle can be formed）If first groove
The distance between distance, the 3rd groove 215 and second groove 214 between 213 and second groove 214 is too small, then barrier layer and conduction
The distance between layer is excessively near, then barrier layer stops that Doped ions spread limited in one's ability in conductive layer, subsequently in thermal processes act
Under, the Doped ions of conductive layer bottom still can cross barrier layer and be spread to the dopant well being subsequently formed；If the He of first groove 213
The distance between distance, the 3rd groove 215 and second groove 214 between second groove 214 is excessive, then can cause the wave of chip area
Take, be unfavorable for the development trend of semiconductor structure miniaturization miniaturization.Summary considers, in the present embodiment, first groove 213
The distance between distance, the 3rd groove 215 and second groove 214 between second groove 214 is 10 angstroms to 1000 angstroms.
It should be noted that in other embodiments, the width of first groove and the 3rd groove is more than or equal to the second ditch
The width of groove is also feasible.
In the present embodiment, first groove 213, second groove 214 and the 3rd groove 215 are the shape in the processing step with along with
Into；In other embodiments, first groove, second groove and the 3rd groove can also be sequentially formed.
Fig. 6 is refer to, forms the barrier layer 216 of the full groove 215 of first groove 213 and the 3rd of filling.
The material on the barrier layer 216 is silica, silicon nitride or silicon oxynitride, using chemical vapor deposition, physics gas
Mutually deposition or atom layer deposition process form the barrier layer 216.
As one embodiment, the material on barrier layer 216 is silicon nitride, and the technological parameter of chemical vapor deposition method is：
Reacting gas includes silicon source gas and oxygen source gas, wherein, silicon source gas TEOS（C8H20O4Si）Or SiH4, oxygen source gas is
O2Or O3, silicon source gas flow is 10sccm to 100sccm, and oxygen source gas flow is 50sccm to 100sccm, and radio-frequency power is
2000 watts to 4000 watts, bias power is 1000 watts to 2500 watts.
The barrier layer 216 is act as：Subsequently when undergoing thermal anneal process technique, the conduction in second groove 214
Doped ions in layer can spread, and played positioned at the barrier layer 216 of conductive layer both sides and stop that conductive layer Doped ions expand
The effect in undesirable region is dissipated to, particularly, stop second is played on the barrier layer 216 in the groove 215 of first groove 213 and the 3rd
The Doped ions diffusion of the conductive layer of the bottom of groove 215, improve the electric property and reliability of semiconductor structure.
In the present embodiment, while barrier layer 216 for filling the full groove 215 of first groove 213 and the 3rd are formed, the
The bottom of two groove 214 and side wall form separation layer 219；Played positioned at the separation layer 219 of the side wall of second groove 214 and stop the second ditch
The effect of the conductive layer Doped ions diffusion of the sidewall areas of groove 214.
Also, because the width of the groove 215 of first groove 213 and the 3rd is less than the width of second groove 214, ensure filling out
After the groove 215 of first groove 213 and the 3rd, second groove 214 is not filled full, and second groove 214 only has bottom and side
Wall forms separation layer 219, and the material of the separation layer 219 is identical with the material of barrier layer 216, in favor of subsequently in second groove
The conductive layer being connected with buried regions area 201 is formed in 214 so that the filling barrier layer in the groove 215 of first groove 213 and the 3rd
While 216, the technique simple possible of separation layer 219 is formed in the bottom of second groove 215 and side wall.
In the present embodiment, the shape in 213 and the 3rd groove of first groove, 215 interior formation barrier layer 216, second groove 214
While into separation layer 219, the surface of substrate 200 also form barrier layer 216.
In other embodiments, when the width of first groove and the 3rd groove is more than or equal to the width of second groove, shape
Processing step into the full first groove of filling and the barrier layer of the 3rd groove includes：Form the full first groove of filling and the 3rd groove
Barrier layer while, full second groove is also filled on the barrier layer；The barrier layer formed after, formed positioned at substrate with
And the patterned photoresist layer of barrier layer surface, the patterned photoresist layer expose the barrier layer table in second groove
Face；Using the patterned photoresist layer as mask, etching removes the barrier layer in second groove, until exposing second groove
Bottom.It should be noted that the barrier layer of second groove side wall can be retained, there is second groove side wall and stop conductive leafing
The ability of son diffusion.
Fig. 7 is refer to, the separation layer 219 positioned at the bottom of second groove 214 is removed, exposes the bottom of second groove 214
Buried regions area 201.
In the present embodiment, the separation layer 219 positioned at the bottom of second groove 214 is removed using dry etch process.
Because dry etch process has stronger directionality so that the separation layer 219 of the bottom of second groove 214 is etched
While removal, also it is etched removal positioned at the barrier layer 216 on the surface of substrate 200, and the separation layer of the side wall of second groove 214
219 still retain.
Also, in the present embodiment, in the technical process for the separation layer 219 that the bottom of second groove 214 is removed in etching, first
The surface of barrier layer 216 in the groove 215 of groove 213 and the 3rd also can be right by a certain degree of etching, the barrier layer 216 of loss
The performance impact of semiconductor structure is smaller；Also, subsequently in the technical process of isolation structure or grid structure is formed, loss
Barrier layer 216 can be compensated.
Fig. 8 is refer to, forms the full second groove 214 of filling（It refer to Fig. 7）Conductive layer 217.
The conductive layer 217 is act as：When semiconductor structure is in running order, applied by conductive layer 217
Voltage to apply voltage to buried regions area 201, improves the noise resisting ability of semiconductor structure；When conductive layer 217 applies voltage, lead
Carrier in the range of electric layer 217 is surrounded is increased the potential barrier of substrate 200, so as to improve the lateral of semiconductor structure
The ability of noise insulation.
The material of the conductive layer 217 is the polysilicon of doping.Also, in order to reduce the electricity of the semiconductor structure of formation
Resistance, the resistance of conductive layer 217 need to do smaller, and therefore, the Doped ions content of conductive layer 217 is higher.
The forming step of conductive layer 217 includes：Form the full second groove 214 of filling and positioned at the conduction on the surface of substrate 200
Film；Conducting film higher than the surface of substrate 200 is removed using CMP process, forms leading for the full second groove 214 of filling
Electric layer 217.
The doping type of conductive layer 217 is identical with the doping type in buried regions area 201, and with being subsequently formed mixing for dopant well
Miscellany type is opposite.As one embodiment, the doping type of the dopant well being subsequently formed is p-type, the doping type of conductive layer 217
For N-type, Doped ions are N-type ion, for example, P, As or Sb；As another embodiment, the doping class for the dopant well being subsequently formed
Type is N-type, and the doping type of conductive layer 217 is p-type, and doping type is p-type ion, for example, B, Ga or In.
Forming the technique of the conductive layer 217 includes in situ adulterate.
Fig. 9 is refer to, dopant well 218 is formed in the substrate 200 that the conductive layer 217 and buried regions area 201 surround.
As one embodiment, the doping type of the dopant well 218 is identical with the doping type in buried regions area 201, as
Other embodiment, the dopant well 218 and the doping type in buried regions area 201 may be reversed.The present embodiment is with dopant well 218
Doping type is opposite with the doping type in buried regions area 201 do it is exemplary illustrated.
The technique for forming the dopant well 218 is ion implanting.As one embodiment, the doping type in buried regions area 201
For n-type doping, the injection ion of ion implanting is p-type ion；As another embodiment, the doping type in buried regions area 201 is p-type
Doping, the injection ion of ion implanting is N-type ion.
When semiconductor structure is in running order by applying voltage to buried regions area 201, increase buried regions area 201 is surrounded
In the range of carrier to the potential barrier of substrate 200 so that the noise coupling in substrate 200 is difficult to diffuse to by the potential barrier
In dopant well 218, so as to improve the noise resisting ability of the semiconductor structure formed on the basis of dopant well 218, semiconductor is improved
Reliability of structure.
Figure 10 is refer to, follow-up processing step includes：After dopant well 218 is formed, the is carried out to the substrate 200
One annealing；Grid structure 220 is formed on the surface of dopant well 218；In the dopant well 218 of the grid structure both sides
Doped region 230 is formed, the second annealing is carried out to the substrate 200.
In the presence of the first annealing and the second annealing, the Doped ions in conductive layer 217 spread, every
Absciss layer 219 stops the sidewall diffusion of the Doped ions conductive layer 217 in conductive layer 217 so that doping in conductive layer 217 from
The sub- bottom of conductive layer 217 diffusion, forms the diffusion zone using the bottom of conductive layer 217 as the center of circle；However, due to away from conductive layer
The barrier effect on the barrier layer 216 of 217 both sides so that in the Doped ions in the region inner conducting layer 217 of dopant well 218 only
The side wall on barrier layer 216 can be reached, in the range of the diffusion zone using the bottom of conductive layer 217 as the center of circle is strapped in into very little, prevented
Only so as to avoid breakdown or break-through occur for Doped ions too close to dopant well 218 between buried regions area 201 and dopant well 218,
Improve the electric property and reliability of semiconductor structure.Also, the barrier effect on the barrier layer 216 due to remote conductive layer 217,
Prevent from forming PN junction between the Doped ions in conductive layer 217 and other Doped ions, avoid the formation of unnecessary PN junction, from
And further improve the electric property of semiconductor structure.
And in the prior art, in the presence of thermal anneal process, the Doped ions hair in conductive layer 217 or buried regions area 201
Life diffuses to form diffusion zone, and when the thermal annealing time is longer or temperature is higher, the distance of the diffusion zone and dopant well becomes
Obtain close；If now buried regions area and dopant well doping type on the contrary, and the voltage that applies to buried regions area and dopant well it is opposite when,
The backward voltage can to puncture between buried regions area and dopant well.
Also, can by setting first groove 213, the position of the groove 215 of second groove 214 and the 3rd and width size
So that the area of barrier layer 216 and conductive layer 217 shared by semiconductor structure is small as far as possible, so as to improve semiconductor junction
While the electric property and reliability of structure, meet the development trend of semiconductor miniaturization miniaturization.
To sum up, the technical scheme of method for forming semiconductor structure provided by the invention has advantages below：
First, formed in substrate after buried regions area, etching removes the substrate of segment thickness, and the first ditch is formed in substrate
Groove, second groove and the 3rd groove, first groove and the 3rd groove are located at the both sides of second groove respectively, and second groove bottom is extremely
Expose less at the top of buried regions area；Conductive layer is formed in second groove with buried regions area to be connected；Also, form full first ditch of filling
The barrier layer of groove and the 3rd groove, the barrier layer stop that the Doped ions of conductive layer bottom spread to dopant well, prevent conduction
Doped ions in layer, so as to prevent breakdown or punchthrough issues, improve the reliable of semiconductor structure too close to dopant well
Property.
Secondly, the width of second groove is more than the width of first groove and the 3rd groove so that forms full first ditch of filling
While the barrier layer of groove and the 3rd groove, barrier layer is formed in the side wall of second groove and bottom, second groove side-walls
Barrier layer can play the diffusion for stopping conductive layer side-walls Doped ions, so as to further prevent the Doped ions in conductive layer
Diffuse to undesirable region.
Again, the width of first groove and the 3rd groove be less than second groove width, make barrier layer account for chip area compared with
It is small, meet the development trend of semiconductor miniaturization and miniaturization.
Accordingly, the present invention also provides a kind of semiconductor structure, refer to Fig. 9, including：
Substrate 200；
Buried regions area 201 in substrate 200, the conductive energy in buried regions area 201, and in the buried regions area 201
With Doped ions；
Annular first groove, second groove and the 3rd groove in substrate 200, and the first groove and the 3rd
Groove is located at second groove both sides respectively, and second groove bottom is at least to expose the top of buried regions area 201；
The barrier layer 216 of the full first groove of filling and the 3rd groove；
The conductive layer 217 of the full second groove of filling, the conductive layer 217 are connected with buried regions area 201, and described lead
The doping type of electric layer 217 is identical with the doping type in buried regions area 201；
Dopant well 218 in the substrate 200 that the conductive layer 217 and buried regions area 201 surround；
Grid structure 220 positioned at the surface of dopant well 218；
Doped region 230 in the dopant well 218 of the both sides of grid structure 220.
Specifically, the material of the substrate 200 is silicon, germanium, SiGe, GaAs or carborundum, the substrate 200 also may be used
Think the silicon substrate on insulator.In the present embodiment, the substrate 200 is silicon substrate.
The doping type in the buried regions area 201 is that n-type doping or p-type are adulterated, and the material in the buried regions area 201 is containing mixing
The silicon of heteroion.As one embodiment, the doping type in buried regions area 201 is n-type doping, and the Doped ions in buried regions area 201 are
P, As or Sb；As another embodiment, the doping type in buried regions area 201 is p-type doping, the Doped ions in buried regions area 201 are B,
Ga or In.
The distance between distance, the 3rd groove and second groove between the first groove and second groove can be according to reality
Technique it needs to be determined that, in the present embodiment, the distance between distance, the 3rd groove and second groove between first groove and second groove
It is 10 angstroms to 1000 angstroms.
Second groove bottom is at least to expose the top of buried regions area 201.As one embodiment, second groove bottom-exposed
Go out the top of buried regions 201；Second groove bottom is located in buried regions area 201 in another embodiment.
In the present embodiment, second groove bottom is less than the top of buried regions area 201, that is to say, that the bottom of conductive layer 217 is less than
The top of buried regions area 201 so that conductive layer 217 is connected with buried regions area 201, when semiconductor structure is in running order, passes through
The external voltage of conductive layer 217 and realize to buried regions area 201 apply voltage, carried so as to increase in the range of buried regions area 201 surrounds
Potential barrier of stream to substrate 200 so that the noise coupling in substrate 200 is difficult to enter in dopant well 218 by the potential barrier, carries
The noise resisting ability of high semiconductor structure.Also, second groove bottom is located at the border of buried regions area 201.
The material of the conductive layer 217 is the polysilicon of doping, and the doping type of conductive layer 217 and buried regions area 201
Doping type is identical, and the doping type of conductive layer 217 adulterates for n-type doping or p-type.In order to reduce conductive layer 217 to semiconductor
The influence of structural resistance, the Doped ions content in usual conductive layer 217 is higher, so that conductive layer 217 has less electricity
Resistance.
In the present embodiment, the width of second groove is more than the width of first groove and the 3rd groove, and in second groove
Side wall can stop second groove side-walls conductive layer formed with separation layer 219, the separation layer 219 of the second groove side-walls
217 ion diffusion.Also, because the width of first groove and the 3rd groove is smaller, the area of semiconductor structure can be reduced, it is full
The miniaturization trend of sufficient semiconductor.
The material on the barrier layer 216 is silica, silicon nitride or silicon oxynitride.In first groove and second groove
Barrier layer 216 can both stop the bottom section of conductive layer 217 ion diffusion, can also stop the sidewall areas of conductive layer 217 from
Son diffusion, prevents the Doped ions in conductive layer 217 from diffusing to undesirable region, electrically connects or hit with undesirable region
Wear, so as to improve the reliability of semiconductor structure and electric property.
Due to barrier layer 216 can play stop conductive layer 217 in Doped ions diffusion, by set barrier layer 216 with
And position and the width of conductive layer 217, the distance between barrier layer 216, conductive layer 217 and dopant well 218 can be made relatively near, resistance
Barrier 216 and conductive layer 217 account for the development trend that chip area is smaller, meet semiconductor miniaturization, is miniaturized.
The doping type of the dopant well 218 can be with identical or opposite with the doping type in buried regions area 201.
To sum up, the technical scheme of semiconductor structure provided by the invention has advantages below：
First, semiconductor structure of the invention includes the buried regions area in the substrate, first groove in substrate, the
Two grooves and the 3rd groove, and first groove and the 3rd groove are located at second groove both sides respectively, second groove bottom is at least sudden and violent
Expose at the top of buried regions area；The conductive layer of the full second groove of filling, conductive layer are connected with buried regions area, wrapped in conductive layer and buried regions area
There is dopant well in the substrate enclosed；When semiconductor structure is in running order, voltage is applied to buried regions area by conductive layer, increased
Adding the carrier surrounded described in buried regions area, the increase of the potential barrier is so that the noise diffusion in substrate is extremely adulterated to the potential barrier of substrate
The ability of trap reduces, so as to improve the noise resisting ability of semiconductor structure；Also, first groove and the 3rd groove are respectively positioned at the
Two groove both sides, and the barrier layer with the full first groove of filling and the 3rd groove, the barrier layer stops mixing in conductive layer
Heteroion diffuses to dopant well, Doped ions and dopant well hypotelorism in conductive layer is prevented, so as to improve semiconductor structure
Reliability and electric property.
Secondly, the width of second groove is more than the width of first groove and the 3rd groove so that first groove and the 3rd ditch
It is smaller that groove accounts for chip area, i.e. barrier layer accounts for that chip area is smaller, so that semiconductor structure meets miniaturization, miniaturization
Development trend.
Again, second groove side wall has separation layer, and the separation layer further prevents conductive layer side-walls Doped ions
Diffusion, so as to further improve semiconductor structure reliability and electric property.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided；Buried regions area, the conductive energy in buried regions area are formed in the substrate, and there are Doped ions in the buried regions area；Etching removes the substrate of segment thickness, and first groove, second groove and the 3rd ditch of annular are formed in the substrate Groove, the first groove and the 3rd groove are located at the both sides of second groove respectively, and second groove bottom at least exposes buried regions At the top of area；Form the barrier layer of the full first groove of filling and the 3rd groove；The conductive layer of the full second groove of filling is formed, the conductive layer is connected with buried regions area, and the conductive layer is mixed Miscellany type is identical with the doping type in buried regions area；Dopant well is formed in the substrate that the conductive layer and buried regions area surround；Grid structure is formed on the dopant well surface；Doped region is formed in the dopant well of the grid structure both sides, doped region is made annealing treatment.
- 2. the forming method of semiconductor structure according to claim 1, it is characterised in that the first groove and second groove Between distance, the distance between the 3rd groove and second groove be 10 angstroms to 1000 angstroms.
- 3. the forming method of semiconductor structure according to claim 1, it is characterised in that the second groove bottom is at least Expose includes at the top of buried regions area：Second groove bottom-exposed goes out at the top of buried regions area；Second groove bottom is located in buried regions area.
- 4. the forming method of semiconductor structure according to claim 1, it is characterised in that the second groove bottom, which is located at, buries Floor area border.
- 5. the forming method of semiconductor structure according to claim 1, it is characterised in that the first groove and the 3rd groove Width be less than second groove width.
- 6. the forming method of semiconductor structure according to claim 1, it is characterised in that also including step：Filled being formed While the barrier layer of the full first groove and the 3rd groove, separation layer is formed in second groove bottom and side wall；Remove position Separation layer in second groove bottom, expose the buried regions area of second groove bottom.
- 7. the forming method of semiconductor structure according to claim 1, it is characterised in that the material on the barrier layer is oxidation Silicon, silicon nitride or silicon oxynitride.
- 8. the forming method of semiconductor structure according to claim 1, it is characterised in that using chemical vapor deposition, physics Vapour deposition or atom layer deposition process form the barrier layer.
- 9. the forming method of semiconductor structure according to claim 8, it is characterised in that the chemical vapor deposition method Technological parameter is：Reacting gas includes silicon source gas and oxygen source gas, wherein, silicon source gas is TEOS or SiH4, oxygen source gas For O2Or O3, silicon source gas flow is 10sccm to 100sccm, and oxygen source gas flow is 50sccm to 100sccm, radio-frequency power For 2000 watts to 4000 watts, bias power is 1000 watts to 2500 watts.
- 10. the forming method of semiconductor structure according to claim 1, it is characterised in that the first groove and the 3rd ditch The bottom of groove is less than at the top of buried regions area.
- 11. the forming method of semiconductor structure according to claim 1, it is characterised in that the first groove, second groove Formed with the 3rd groove in the processing step with along with.
- 12. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of the conductive layer is to mix Miscellaneous polysilicon.
- A kind of 13. semiconductor structure, it is characterised in that including：Substrate；Buried regions area in substrate, the conductive energy in buried regions area, and there are Doped ions in the buried regions area；Annular first groove, second groove and the 3rd groove in substrate, and the first groove and the 3rd groove point Not Wei Yu second groove both sides, and the second groove bottom is at least exposed at the top of buried regions area；The barrier layer of the full first groove of filling and the 3rd groove；The conductive layer of the full second groove of filling, the conductive layer is connected with buried regions area, and the doping class of the conductive layer Type is identical with the doping type in buried regions area；The dopant well in substrate surrounded positioned at conductive layer and buried regions area；Grid structure positioned at dopant well surface；Doped region in the dopant well of grid structure both sides；The bottom of the first groove and the 3rd groove is less than at the top of buried regions area.
- 14. the semiconductor structure according to claim 13, it is characterised in that between the first groove and second groove away from From being 10 angstroms to 1000 angstroms with a distance between, the 3rd groove and second groove.
- 15. the semiconductor structure according to claim 13, it is characterised in that the second groove bottom is at least to expose to bury Include at the top of floor area：Second groove bottom-exposed goes out at the top of buried regions area；Second groove bottom is located in buried regions area.
- 16. the semiconductor structure according to claim 13, it is characterised in that the second groove bottom is located at buried regions area side Boundary.
- 17. the semiconductor structure according to claim 13, it is characterised in that the width of the second groove is more than first groove With the width of the 3rd groove.
- 18. the semiconductor structure according to claim 13, it is characterised in that the side wall of the second groove has separation layer.
- 19. the semiconductor structure according to claim 13, it is characterised in that the material on the barrier layer is silica, nitridation Silicon or silicon oxynitride.
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| US7071530B1 (en) * | 2005-01-27 | 2006-07-04 | International Business Machines Corporation | Multiple layer structure for substrate noise isolation |
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