CN104900631A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104900631A CN104900631A CN201410076994.5A CN201410076994A CN104900631A CN 104900631 A CN104900631 A CN 104900631A CN 201410076994 A CN201410076994 A CN 201410076994A CN 104900631 A CN104900631 A CN 104900631A
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Abstract
Provided are a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing a substrate; forming a buried layer area in the substrate, wherein the buried layer area is provided with a conductive property; removing a certain thickness of the substrate by etching, and forming an annular first trench, an annular second trench, and a third trench in the substrate, wherein the first trench and the third trench are disposed on both sides of the second trench respectively and the bottom of the second trench at least exposes the top of the buried layer area; forming a barrier layer fully filling the first trench and the third trench; forming a conductive layer fully filling the second trench, wherein the conductive layer is connected with the buried layer area and the doping type of the conductive layer is the same as that of the buried layer area; and forming a doped well in the substrate surrounded by the conductive layer and the buried layer area. While improving the anti-noise capability of the semiconductor structure, the method stops the diffusion of ions doped in the conductive layer and prevents the doped ions from excessively getting close to the doped well so as to improve the electrical performance and the reliability of the semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture technology, particularly semiconductor structure and forming method thereof.
Background technology
Along with the develop rapidly of semiconductor technology, high-speed digital circuit (DC:Digital Circuit) and high performance analog circuits (AC:Analog Circuit) can be integrated and form composite signal integrated circuits (IC:Integrated Circuit).
But in hybrid integrated circuit, because the switching transient electric current of digital state circuit is comparatively large, form disturbance electric charge, these disturbance electric charges are coupled in responsive analog circuit by Semiconductor substrate, form substrate noise, interference is configured to the semiconductor junction of analog circuit.
Especially, along with constantly the reducing of physical dimension of semiconductor structure, the noise coupling of Semiconductor substrate has become the problem having to pay attention to.
For this reason, study the noise resisting ability how improving semiconductor structure and become the problem needing solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure and forming method thereof, while reduction substrate noise is to semiconductor structure performance impact, avoids the Doped ions of substrate inner conducting layer to diffuse to undesirably region.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided; In described substrate, form buried regions district, described buried regions district has electric conductivity, and has Doped ions in described buried regions district; Etching removes the substrate of segment thickness, and in described substrate, form the first groove of annular, the second groove and the 3rd groove, described first groove and the 3rd groove lay respectively at the both sides of the second groove, and the second channel bottom at least exposes top, buried regions district; Form the barrier layer of filling full described first groove and the 3rd groove; Form the conductive layer of filling full described second groove, described conductive layer is connected with buried regions district, and the doping type of described conductive layer is identical with the doping type in buried regions district; Dopant well is formed in the substrate that described conductive layer and buried regions district surround; Grid structure is formed on described dopant well surface; In the dopant well of described grid structure both sides, form doped region, annealing in process is carried out to doped region.
Optionally, the distance between described first groove and the second groove, distance between the 3rd groove and the second groove are 10 dust to 1000 dusts.
Optionally, described second channel bottom comprises at least exposing top, buried regions district: the second channel bottom exposes top, buried regions district; Second channel bottom is positioned at buried regions district.
Optionally, described second channel bottom is positioned at border, buried regions district.
Optionally, the width of described first groove and the 3rd groove is less than the width of the second groove.
Optionally, also comprise step: while forming the barrier layer of filling full described first groove and the 3rd groove, form separator at the second channel bottom and sidewall; Remove the separator being positioned at the second channel bottom, expose the buried regions district of the second channel bottom.
Optionally, the material on described barrier layer is silica, silicon nitride or silicon oxynitride.
Optionally, chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process is adopted to form described barrier layer.
Optionally, the technological parameter of described chemical vapor deposition method is: reacting gas comprises silicon source gas and oxygen source gas, and wherein, silicon source gas is TEOS or SiH
4, oxygen source gas is O
2or O
3, silicon source gas flow is 10sccm to 100sccm, and oxygen source gas flow is 50sccm to 100sccm, and radio-frequency power is 2000 watts to 4000 watts, and bias power is 1000 watts to 2500 watts.
Optionally, the bottom of described first groove and the 3rd groove is lower than top, buried regions district.
Optionally, described first groove, the second groove and the 3rd groove are formed in processing step.
Optionally, the material of described conductive layer is the polysilicon of doping.
Accordingly, the present invention also provides a kind of semiconductor structure, comprising: substrate; Be positioned at the buried regions district of substrate, described buried regions district has electric conductivity, and has Doped ions in described buried regions district; Be positioned at the first groove of the annular of substrate, the second groove and the 3rd groove, and described first groove and the 3rd groove lay respectively at the second groove both sides, and described second channel bottom at least exposes top, buried regions district; Fill the barrier layer of full described first groove and the 3rd groove; Fill the conductive layer of full described second groove, described conductive layer is connected with buried regions district, and the doping type of described conductive layer is identical with the doping type in buried regions district; Be positioned at the dopant well of the substrate of conductive layer and the encirclement of buried regions district; Be positioned at the grid structure on dopant well surface; Be positioned at the doped region of the dopant well of grid structure both sides.
Optionally, the distance between described first groove and the second groove, distance between the 3rd groove and the second groove are 10 dust to 1000 dusts.
Optionally, described second channel bottom comprises at least exposing top, buried regions district: the second channel bottom exposes top, buried regions district; Second channel bottom is positioned at buried regions district.
Optionally, described second channel bottom is positioned at border, buried regions district.
Optionally, the width of described second groove is greater than the width of the first groove and the 3rd groove.
Optionally, the sidewall of described second groove has separator.
Optionally, the bottom of described first groove and the 3rd groove is lower than top, buried regions district.
Optionally, the material on described barrier layer is silica, silicon nitride or silicon oxynitride.
Compared with prior art, technical scheme of the present invention has the following advantages:
The invention provides a kind of formation method of semiconductor structure, wherein, form buried regions district in substrate after, etching removes the substrate of segment thickness, the first groove, the second groove and the 3rd groove is formed in substrate, first groove and the 3rd groove lay respectively at the both sides of the second groove, and the second channel bottom at least exposes top, buried regions district; In the second groove, form conductive layer be connected with buried regions district; And, form the barrier layer of filling full first groove and the 3rd groove, described barrier layer stops that the Doped ions bottom conductive layer spreads to dopant well, (Doped ions only can diffuse to barrier layer side-walls) within very little scope will be strapped in the diffusion zone for the center of circle bottom conductive layer, prevent Doped ions in conductive layer too near dopant well, thus prevent to puncture or punchthrough issues, improve the reliability of semiconductor structure.
Simultaneously, the buried regions district with electric conductivity is formed in substrate, by applying voltage to buried regions district, charge carrier in the scope that raising buried regions district surrounds is to the potential barrier of substrate, make the noise coupling in substrate be difficult to cross described potential barrier and enter dopant well, thus prevent noise coupling from causing harmful effect to dopant well, improve the noise resisting ability of semiconductor structure.
Further, the width of the second groove is greater than the width of the first groove and the 3rd groove, while making to be formed the barrier layer of filling full first groove and the 3rd groove, at sidewall and the bottom formation separator of the second groove, the separator at the second trenched side-wall place can play the diffusion stopping conductive layer side-walls Doped ions, thus prevents the Doped ions in conductive layer from diffusing to undesirably region further.
Meanwhile, the width of the first groove and the 3rd groove is less than the width of the second groove, makes barrier layer account for chip area less, meets the development trend that semiconductor is miniaturized and microminiaturized.
The present invention also provides the semiconductor structure that a kind of structural behaviour is superior, wherein, comprise the buried regions district being positioned at substrate, be positioned at the first groove of substrate, the second groove and the 3rd groove, and the first groove and the 3rd groove lay respectively at the second groove both sides, the second channel bottom at least exposes top, buried regions district; Fill the conductive layer of full second groove, conductive layer is connected with buried regions district, in the substrate that conductive layer and buried regions district surround, have dopant well; When semiconductor structure is in running order, voltage is applied to buried regions district by conductive layer, the scope carriers that increase buried regions district surrounds is to the potential barrier of buried regions district outer-lining bottom, the increase of described potential barrier makes the noise diffusion in substrate reduce to the ability of dopant well, thus improves the noise resisting ability of semiconductor structure; And, first groove and the 3rd groove lay respectively at the second groove both sides, and there is the barrier layer of filling full first groove and the 3rd groove, described barrier layer stops that the Doped ions in conductive layer diffuses to dopant well, prevent Doped ions and dopant well hypotelorism in conductive layer, thus improve reliability and the electric property of semiconductor structure.
Further, the width of the second groove is greater than the width of the first groove and the 3rd groove, makes the first groove and the 3rd groove account for chip area less, and namely to account for chip area less on barrier layer, thus the semiconductor structure made meets miniaturization, microminiaturized development trend.
Further, the second trenched side-wall has separator, and described separator prevents the diffusion of conductive layer side-walls Doped ions further, thus improves reliability and the electric property of semiconductor structure further.
Accompanying drawing explanation
The cross-sectional view of the semiconductor structure that Fig. 1 to Fig. 2 provides for an embodiment;
The cross-sectional view of the formation semiconductor structure process that Fig. 3 to Figure 10 provides for another embodiment of the present invention.
Embodiment
From background technology, the noise resisting ability how research improves device is the problem needing solution badly.
For solving the problem, formation method for semiconductor structure is carried out research and is found, in order to improve the noise resisting ability of semiconductor structure, in reduction substrate, noise is on the impact of semiconductor structure performance, can adopt and form semiconductor structure on the basis of following structure, please refer to Fig. 1:
Comprise: substrate 100; Be positioned at the buried regions district 101 of substrate 100, in described buried regions district 101, there is Doped ions, and described buried regions district 101 has electric conductivity; Be positioned at the ring-shaped groove of substrate 100, and described ring-shaped groove is positioned at buried regions district 101 sidewall boundary, described channel bottom exposes buried regions district 101; Fill the conductive layer 102 of full described groove, and described conductive layer 102 is connected with buried regions district 101.The step that the basis of the above-mentioned structure provided is formed semiconductor structure comprises: in the substrate 100 that conductive layer 102 and buried regions district 101 surround, form dopant well 103; Follow-up processing step also comprises formation source electrode, drain electrode, grid structure.
Owing to there is Doped ions in buried regions district 101, and the Doped ions concentration in buried regions district 101 is much larger than Doped ions concentration in substrate 100, when semiconductor structure is in running order, voltage is applied to buried regions district 101, thus the charge carrier increased in buried regions district 101 scope of surrounding is to the potential barrier of buried regions district 101 outer-lining bottom 100, make the noise in buried regions district 101 outer-lining bottom 100 be difficult to go beyond described potential barrier to diffuse in dopant well 103, thus reduce substrate noise to the impact of semiconductor structure.
Acting as of described conductive layer 102: buried regions district 101 is connected by conductive layer 102 with external voltage, thus the scope carriers that raising buried regions district 101 surrounds is to the potential barrier of buried regions district 101 outer-lining bottom 100; Further, apply voltage by conductive layer 102, charge carrier that conductive layer 102 surrounds can be improved to the barrier height of conductive layer 102 outer-lining bottom 100, increase the isolation capacity of side direction, improve the noise resisting ability of device further.
In order to reduce the impact of conductive layer 102 on semiconductor structure resistance as far as possible, the Doped ions content in usual conductive layer 102 is higher, thus reduces the resistance of conductive layer 102 as much as possible.
But in order to reduce the formation process of buried regions district 101 and conductive layer 102 to the impact of semiconductor structure as far as possible, buried regions district 101 and conductive layer 102 need to be formed before dopant well; Therefore, after formation buried regions district 101 and conductive layer 102, the formation process of semiconductor structure can comprise one or multi-channel thermal anneal process, under thermal anneal process effect, Doped ions in conductive layer 102 spreads, please refer to Fig. 2, conductive layer 102 sidewall can stop the diffusion of side-walls Doped ions by forming barrier layer; But, owing to needing buried regions district 101 to be connected bottom conductive layer 102, therefore, be difficult to by forming barrier layer to stop the diffusion of the Doped ions of bottom section bottom conductive layer 102; Under thermal anneal process effect, define with the diffusion zone for the center of circle bottom conductive layer 102, because the Doped ions content in conductive layer 102 is high, if it is excessively near that doped region and dopant well 103 are separated by, and the doping type of dopant well 103 different from the doping type in buried regions district 101 time, if the external high voltage in buried regions district 101, and when the voltage of dopant well 103 is lower, then likely cause dopant well 103 breakdown; Or conductive layer 102 and buried regions district 101 form unnecessary electrical connection with other regions, cause the degraded performance of semiconductor structure, poor reliability, even cause semiconductor structure performance failure.
In conductive layer 102, Doped ions causes harmful effect to dopant well 103, what conductive layer 102 and the distance of dopant well 103 can be made to arrange is far away, but what conductive layer 102 was arranged with the distance of dopant well 103 far can waste chip area, the area of semiconductor structure is caused to become large; And along with the characteristic size of semiconductor structure constantly reduces, be difficult to, by the method making conductive layer 102 and dopant well 103 distant, avoid conductive layer 102 Doped ions to cause harmful effect to dopant well 103.
For this reason, the invention provides a kind of semiconductor structure and forming method thereof, the first groove and the 3rd groove is formed in the second groove both sides, and form the barrier layer of filling full first groove and the 3rd groove, fill the conductive layer of full second groove, described barrier layer stops the diffusion of Doped ions in conductive layer, the diffusion of special stop conductive layer bottom section Doped ions, thus improve electric property and the reliability of semiconductor structure, and save chip area, meet the development trend that semiconductor is miniaturized and microminiaturized.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First the present invention provides a kind of formation method of semiconductor structure, the cross-sectional view of the semiconductor structure formation process that Fig. 3 to Figure 10 provides for the embodiment of the present invention.
Please refer to Fig. 3, substrate 200 is provided; In described substrate 200, form buried regions district 201, described buried regions district 201 has electric conductivity, and has Doped ions in described buried regions district 201.
Concrete, the material of described substrate 200 is monocrystalline silicon, polysilicon, amorphous silicon or isolate supports one wherein; Described substrate 200 also can be Si substrate, Ge substrate, GeSi substrate or GaAs substrate.
Described substrate 200 surface can also form some epitaxial interface layers or strained layer to improve the electric property of semiconductor structure.
In the present embodiment, described substrate 200 is Si substrate.In other embodiments of the present invention, substrate for being formed with the substrate of device, such as, can also be formed with transistor, electric capacity or resistance etc. in substrate.
Described buried regions district 201 act as: described buried regions district 201 has electric conductivity, and in buried regions district 201, there is Doped ions, when semiconductor structure is in running order, after applying suitable voltage to buried regions district 201, charge carrier in the scope that buried regions district 201 is surrounded increases the potential barrier of buried regions district 201 outer-lining bottom 200, thus make the noise coupling in buried regions district 201 outer-lining bottom 200 cross over described potential barrier diffuse into the dopant well of follow-up formation ability reduce, and then improve the noise resisting ability of semiconductor structure, improve the reliability of semiconductor structure.
As an embodiment, described in there is the substrate 200 in buried regions district 201 forming step comprise: form patterned photoresist layer on substrate 200 surface; With described patterned photoresist layer for mask, adopt ion implantation technology to carry out ion implantation to substrate 200, and the injection degree of depth of described ion implantation technology is darker; Remove patterned photoresist layer; Carry out thermal anneal process to substrate 200, active ions injection technology injects the injection ion of substrate 200, forms buried regions district 201.
As another embodiment, described in there is the substrate 200 in buried regions district 201 forming step comprise: initial substrate is provided; Patterned photoresist layer is formed at described initial substrate surface; With described patterned photoresist layer for mask, adopt ion implantation technology to carry out ion implantation to initial substrate, and the injection degree of depth of described ion implantation technology is more shallow; Remove patterned photoresist layer; Carry out thermal anneal process to initial substrate, active ions injection technology injects the injection ion of initial substrate, forms buried regions district 201; Adopt epitaxy technique to form semiconductor layer at described initial substrate surface, initial substrate and semiconductor layer form substrate 200 jointly.
As other embodiments, described in there is the substrate 200 in buried regions district 201 forming step comprise: initial substrate is provided; Patterned photoresist layer is formed at described initial substrate surface; With described patterned photoresist layer for mask, adopt ion implantation technology to carry out ion implantation to initial substrate, and the injection degree of depth of described ion implantation technology is more shallow; Remove patterned photoresist layer; Carry out thermal anneal process to initial substrate, active ions injection technology injects the injection ion of initial substrate, forms buried regions district 201; Adopt wafer bonding (wafer bonding) technique at initial substrate surface bonding semiconductor layer, initial substrate and semiconductor layer form substrate 200 jointly.
The doping type in described buried regions district 201 is N-type doping or the doping of P type: when the doping type in buried regions district 201 is N-type doping, the injection ion of ion implantation technology is P, As or Sb; When the doping type in buried regions district 201 is the doping of P type, the injection ion of ion implantation technology is B, Ga, In.
Please refer to Fig. 4, form patterned mask layer 202 on described substrate 200 surface, described patterned mask layer 202 defines position and the width of the first groove of follow-up formation, the second groove and the 3rd groove.
Described patterned mask layer 202 has the first opening 203, second opening 204 and the 3rd opening 205, the position of described first opening 203 and width correspond to position and the width of follow-up formation first groove, the position of the second opening 204 and width correspond to position and the width of follow-up formation second groove, and the 3rd opening 205 corresponds to position and the width of follow-up formation the 3rd groove.
In the present embodiment, the material of described mask layer 202 is silicon nitride, and the processing step forming described patterned mask layer 202 comprises: formed and be covered in the original mask layer on substrate 200 surface and be positioned at the initial lithographic glue-line on original mask layer surface; Exposure imaging process is carried out to described initial lithographic glue-line, forms patterned photoresist layer; With described patterned photoresist layer for mask, etching original mask layer, forms the patterned mask layer 202 with the first opening 203, second opening 204 and the 3rd opening 205.
In other embodiments, the material of patterned mask layer is photoresist.
Please refer to Fig. 5, with described patterned mask layer 202 for mask, etching removes the substrate 200 of segment thickness, forms the first groove 213, second groove 214 and the 3rd groove 215 of annular in described substrate 200.
In the present embodiment, bottom the second groove 214, be positioned at the sidewall boundary in buried regions district 201.
Described first groove 213 and the 3rd groove 215 lay respectively at the both sides of the second groove 214.
Acting as of second groove 214: follow-up in the second groove 214 formed conductive layer, described conductive layer is connected with buried regions district 201, realize also applying to buried regions district 201 voltage by conductive layer external voltage, the charge carrier that buried regions district 201 is surrounded increases the potential barrier of substrate 200, plays antimierophonic effect.
As the above analysis, at least to expose top, buried regions district 201 bottom described second groove 214, thus the follow-up conductive layer formed in the second groove 214 can be connected with buried regions district 201.As an embodiment, the second groove 214 bottom-exposed goes out top, buried regions district 201; As another embodiment, bottom the second groove 214, be positioned at buried regions district 201.
Acting as of first groove 213 and the 3rd groove 215: the present embodiment forms the first groove 213 and the 3rd groove 215 respectively in the second groove 214 both sides, follow-up in the first groove 213 and the 3rd groove 215 formed barrier layer, the effect that stop second groove 214 inner conducting layer diffuses to undesirably region is played on described barrier layer, thus improves electric property and the reliability of semiconductor structure.If do not form the first groove and the 3rd groove in the second groove both sides, follow-up in the second groove, form conductive layer after, described conductive layer can have stronger diffusivity in experience Technology for Heating Processing, the diffusion of conductive layer can cause semiconductor structure generation avalanche breakdown or unnecessary electrical connection occurs, and causes semiconductor structure degraded performance even to lose efficacy.
The position relationship demand fulfillment of the first groove 213 and the 3rd groove 215: the follow-up barrier layer formed in the first groove 213 and the 3rd groove 215 affects little requirement to the electrical connection between conductive layer and buried regions district 201, therefore, in the present embodiment, the bottom of the first groove 201 and the 3rd groove 215 is lower than bottom buried regions district 201.
And, because the second groove 214 bottom conductive layer is connected with buried regions district 201, second groove 214 sidewall can form the barrier layer stopping conductive layer ion diffuse, and because need being connected with buried regions district 201 bottom the second groove 214, the ion diffuse of the conductive layer therefore bottom the second groove 214 is the principal element affecting semiconductor structure performance; In order to avoid the ion diffuse extremely undesirably region of the second groove 214 bottom conductive layer, bottom barrier layer in first groove 213 and the 3rd groove 215 with to flush bottom conductive layer or lower than bottom conductive layer, when the bottom of the first groove 213 and the 3rd groove 215 to flush with the second groove 214 top or lower than bottom the second groove 214 time, the barrier layer in the first groove 213 and the 3rd groove 215 stops that the ability of conductive layer ion diffuse is optimum.
In the present embodiment, the width of the first groove 213 and the 3rd groove 215 is less than the width of the second groove 214, mainly contains following benefit:
First, the width of the first groove 213 and the 3rd groove 215 is less than the width of the second groove 214, when the barrier layer of full first groove 213 and the 3rd groove 215 is filled in follow-up formation, described barrier layer also can be formed in bottom and the sidewall of the second groove 214, thus form the separator being positioned at the second groove 214 sidewall, described separator also can play the effect of the conductive layer diffusion of stop second groove 214 sidewall areas, and form conductive layer again after removing the separator bottom the second groove 214, described conductive layer still can be connected with buried regions district 201; Secondly, the area that the first groove 213 and the 3rd groove 215 account for semiconductor structure is little, has saved chip area.
The width of the distance between described first groove 213, second groove 214 and the 3rd groove 215 and the width of the first groove 213, the second groove 214, the width of the 3rd groove 215 can need determine according to actual process.Rear extended meeting forms the barrier layer of filling full first groove 213 and the 3rd groove 215, fill the conductive layer of full second groove 214, there is the Doped ions of easily diffusion in conductive layer (under thermal processes act, can be formed with the diffusion zone for the center of circle bottom conductive layer), if the distance between the first groove 213 and the second groove 214, distance between the 3rd groove 215 and the second groove 214 is too small, hypotelorism then between barrier layer and conductive layer, then barrier layer stops the limited in one's ability of Doped ions diffusion in conductive layer, follow-up under thermal processes act, Doped ions bottom conductive layer still can be crossed barrier layer and spread to the dopant well of follow-up formation, if the distance between the first groove 213 and the second groove 214, distance between the 3rd groove 215 and the second groove 214 are excessive, then can cause the waste of chip area, be unfavorable for the miniaturized microminiaturized development trend of semiconductor structure.Comprehensive above-mentioned consideration, in the present embodiment, the distance between the first groove 213 and the second groove 214, distance between the 3rd groove 215 and the second groove 214 are 10 dust to 1000 dusts.
It should be noted that, in other embodiments, the width of the first groove and the 3rd groove is greater than or the width that equals the second groove is also feasible.
In the present embodiment, the first groove 213, second groove 214 and the 3rd groove 215 are formed in processing step; In other embodiments, the first groove, the second groove and the 3rd groove can also be formed successively.
Please refer to Fig. 6, form the barrier layer 216 of filling full first groove 213 and the 3rd groove 215.
The material on described barrier layer 216 is silica, silicon nitride or silicon oxynitride, adopts chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process to form described barrier layer 216.
As an embodiment, the material on barrier layer 216 is silicon nitride, and the technological parameter of chemical vapor deposition method is: reacting gas comprises silicon source gas and oxygen source gas, and wherein, silicon source gas is TEOS(C
8h
20o
4or SiH Si)
4, oxygen source gas is O
2or O
3, silicon source gas flow is 10sccm to 100sccm, and oxygen source gas flow is 50sccm to 100sccm, and radio-frequency power is 2000 watts to 4000 watts, and bias power is 1000 watts to 2500 watts.
Acting as of described barrier layer 216: follow-up when experiencing thermal anneal process technique, Doped ions in conductive layer in second groove 214 can spread, and the effect that stop conductive layer Doped ions diffuses to undesirably region is played on the barrier layer 216 being positioned at conductive layer both sides, especially, the Doped ions diffusion of the conductive layer bottom stop second groove 215 is played on barrier layer 216 in first groove 213 and the 3rd groove 215, improves electric property and the reliability of semiconductor structure.
In the present embodiment, while forming the barrier layer 216 of filling full first groove 213 and the 3rd groove 215, bottom the second groove 214, form separator 219 with sidewall; The separator 219 being positioned at the second groove 214 sidewall plays the effect of the conductive layer Doped ions diffusion of stop second groove 214 sidewall areas.
And, width due to the first groove 213 and the 3rd groove 215 is less than the width of the second groove 214, ensure after full first groove 213 of filling and the 3rd groove 215, second groove 214 is not filled full, second groove 214 only has bottom and sidewall to define separator 219, the material of described separator 219 is identical with barrier layer 216 material, be beneficial to the follow-up conductive layer that formation is connected with buried regions district 201 in the second groove 214, while making to fill barrier layer 216 in the first groove 213 and the 3rd groove 215, the technique simple possible of separator 219 is formed with sidewall bottom the second groove 215.
In the present embodiment, formed in the first groove 213 and the 3rd groove 215 while forming separator 219 in the groove 214 of barrier layer 216, second, substrate 200 surface also form barrier layer 216.
In other embodiments, when the width of the first groove and the 3rd groove is more than or equal to the width of the second groove, the processing step forming the barrier layer of filling full first groove and the 3rd groove comprises: while forming the barrier layer of filling full first groove and the 3rd groove, and full second groove is also filled on described barrier layer; After described barrier layer is formed, form the patterned photoresist layer being positioned at substrate and barrier layer surface, described patterned photoresist layer exposes the barrier layer surface in the second groove; With described patterned photoresist layer for mask, the barrier layer in etching removal second groove, until expose the bottom of the second groove.It should be noted that, the barrier layer of the second trenched side-wall can be retained, make the second trenched side-wall have the ability stopping conductive layer ion diffuse.
Please refer to Fig. 7, remove the separator 219 be positioned at bottom the second groove 214, expose the buried regions district 201 bottom the second groove 214.
In the present embodiment, dry etch process is adopted to remove the separator 219 be positioned at bottom the second groove 214.
Because dry etch process has stronger directivity, while the separator 219 bottom the second groove 214 being etched remove, the barrier layer 216 being positioned at substrate 200 surface is also etched removal, and the separator 219 of the second groove 214 sidewall still retains.
And, in the present embodiment, in the technical process of the separator 219 bottom etching removal second groove 214, the surface, barrier layer 216 in the first groove 213 and the 3rd groove 215 also can by etching to a certain extent, and the performance impact of the 216 pairs of semiconductor structures in barrier layer of loss is less; Further, follow-up in the technical process forming isolation structure or grid structure, the barrier layer 216 of loss can be compensated.
Please refer to Fig. 8, formed and fill full second groove 214(and please refer to Fig. 7) conductive layer 217.
Acting as of described conductive layer 217: when semiconductor structure is in running order, applies voltage by conductive layer 217 and applies voltage to buried regions district 201, improves the noise resisting ability of semiconductor structure; When conductive layer 217 applies voltage, the potential barrier of charge carrier to substrate 200 in the scope that conductive layer 217 surrounds is increased, thus improves the ability of the side direction noise insulation of semiconductor structure.
The material of described conductive layer 217 is the polysilicon of doping.Further, in order to reduce the resistance of semiconductor structure formed, it is less that the resistance of conductive layer 217 needs to do, and therefore, the Doped ions content of conductive layer 217 is higher.
The forming step of conductive layer 217 comprises: formed and fill full second groove 214 and the conducting film being positioned at substrate 200 surface; Adopt CMP (Chemical Mechanical Polishing) process removal higher than the conducting film on substrate 200 surface, form the conductive layer 217 of filling full second groove 214.
The doping type of conductive layer 217 is identical with the doping type in buried regions district 201, and contrary with the doping type of follow-up formation dopant well.As an embodiment, the doping type of the dopant well of follow-up formation is P type, and the doping type of conductive layer 217 is N-type, and Doped ions is N-type ion, such as, and P, As or Sb; As another embodiment, the doping type of the dopant well of follow-up formation is N-type, and the doping type of conductive layer 217 is P type, and doping type is P type ion, such as, and B, Ga or In.
The technique forming described conductive layer 217 comprises in-situ doped.
Please refer to Fig. 9, in the substrate 200 that described conductive layer 217 and buried regions district 201 surround, form dopant well 218.
As an embodiment, the doping type of described dopant well 218 is identical with the doping type in buried regions district 201, and as other embodiments, described dopant well 218 also can be contrary with the doping type in buried regions district 201.The present embodiment does exemplary illustrated so that the doping type of dopant well 218 is contrary with the doping type in buried regions district 201.
The technique forming described dopant well 218 is ion implantation.As an embodiment, the doping type in buried regions district 201 is N-type doping, and the injection ion of ion implantation is P type ion; As another embodiment, the doping type in buried regions district 201 is the doping of P type, and the injection ion of ion implantation is N-type ion.
When semiconductor structure is in running order by applying voltage to buried regions district 201, the scope carriers that increase buried regions district 201 surrounds is to the potential barrier of substrate 200, thus make the noise coupling in substrate 200 be difficult to diffuse in dopant well 218 by described potential barrier, thus improve the noise resisting ability of the semiconductor structure formed on dopant well 218 basis, improve the reliability of semiconductor structure.
Please refer to Figure 10, follow-up processing step comprises: after formation dopant well 218, carry out the first annealing in process to described substrate 200; Grid structure 220 is formed on described dopant well 218 surface; In the dopant well 218 of described grid structure both sides, form doped region 230, the second annealing in process is carried out to described substrate 200.
Under the effect of the first annealing in process and the second annealing in process, Doped ions in conductive layer 217 spreads, separator 219 stops the sidewall diffusion of the Doped ions conductive layer 217 in conductive layer 217, make to spread bottom the Doped ions conductive layer 217 in conductive layer 217, formed with the diffusion zone for the center of circle bottom conductive layer 217; But, due to the barrier effect on the barrier layer 216 away from conductive layer 217 both sides, make the sidewall that only can reach barrier layer 216 at the Doped ions in dopant well 218 region inner conducting layer 217, be strapped in very little scope by with the diffusion zone for the center of circle bottom conductive layer 217, prevent Doped ions too near dopant well 218, thus avoid between buried regions district 201 and dopant well 218 and puncture or break-through, improve electric property and the reliability of semiconductor structure.Further, due to the barrier effect on the barrier layer 216 away from conductive layer 217, prevent the Doped ions in conductive layer 217 and form PN junction between other Doped ions, avoid the formation of unnecessary PN junction, thus improve the electric property of semiconductor structure further.
And in prior art, under the effect of thermal anneal process, the Doped ions in conductive layer 217 or buried regions district 201 diffuses to form diffusion zone, and when the thermal annealing time is longer or temperature is higher, the distance of described diffusion zone and dopant well becomes very near; If now buried regions district is contrary with the doping type of dopant well, and when the voltage applied to buried regions district and dopant well is contrary, described reverse voltage can make to puncture between buried regions district and dopant well.
And, by arranging position and the width size of the first groove 213, second groove 214 and the 3rd groove 215, the area that barrier layer 216 and conductive layer 217 can be made shared in semiconductor structure is little as much as possible, thus while the electric property improving semiconductor structure and reliability, meet the miniaturized microminiaturized development trend of semiconductor.
To sum up, the technical scheme of method for forming semiconductor structure provided by the invention has the following advantages:
First, form buried regions district in substrate after, etching removes the substrate of segment thickness, forms the first groove, the second groove and the 3rd groove in substrate, first groove and the 3rd groove lay respectively at the both sides of the second groove, and the second channel bottom at least exposes top, buried regions district; In the second groove, form conductive layer be connected with buried regions district; And, form the barrier layer of filling full first groove and the 3rd groove, described barrier layer stops that the Doped ions bottom conductive layer spreads to dopant well, prevents Doped ions in conductive layer too near dopant well, thus prevent to puncture or punchthrough issues, improve the reliability of semiconductor structure.
Secondly, the width of the second groove is greater than the width of the first groove and the 3rd groove, while making to be formed the barrier layer of filling full first groove and the 3rd groove, on sidewall and the formation barrier layer, bottom of the second groove, the diffusion stopping conductive layer side-walls Doped ions can be played in the barrier layer at the second trenched side-wall place, thus prevents the Doped ions in conductive layer from diffusing to undesirably region further.
Again, the width of the first groove and the 3rd groove is less than the width of the second groove, makes barrier layer account for chip area less, meets the development trend that semiconductor is miniaturized and microminiaturized.
Accordingly, the present invention also provides a kind of semiconductor structure, please refer to Fig. 9, comprising:
Substrate 200;
Be positioned at the buried regions district 201 of substrate 200, described buried regions district 201 has electric conductivity, and has Doped ions in described buried regions district 201;
Be positioned at the first groove of the annular of substrate 200, the second groove and the 3rd groove, and described first groove and the 3rd groove lay respectively at the second groove both sides, the second channel bottom is at least to expose top, buried regions district 201;
Fill the barrier layer 216 of full described first groove and the 3rd groove;
Fill the conductive layer 217 of full described second groove, described conductive layer 217 is connected with buried regions district 201, and the doping type of described conductive layer 217 is identical with the doping type in buried regions district 201;
Dopant well 218 in the substrate 200 that described conductive layer 217 and buried regions district 201 surround;
Be positioned at the grid structure 220 on dopant well 218 surface;
Be positioned at the doped region 230 of the dopant well 218 of grid structure 220 both sides.
Concrete, the material of described substrate 200 is silicon, germanium, SiGe, GaAs or carborundum, and described substrate 200 also can be isolate supports substrate.In the present embodiment, described substrate 200 is silicon substrate.
The doping type in described buried regions district 201 is N-type doping or the doping of P type, and the material in described buried regions district 201 is the silicon containing Doped ions.As an embodiment, the doping type in buried regions district 201 is N-type doping, and the Doped ions in buried regions district 201 is P, As or Sb; As another embodiment, the doping type in buried regions district 201 is the doping of P type, and the Doped ions in buried regions district 201 is B, Ga or In.
Distance between described first groove and the second groove, distance between the 3rd groove and the second groove can need to determine according to the technique of reality, in the present embodiment, the distance between the first groove and the second groove, distance between the 3rd groove and the second groove are 10 dust to 1000 dusts.
Second channel bottom is at least to expose top, buried regions district 201.As an embodiment, the second channel bottom exposes buried regions 201 top; In another embodiment, the second channel bottom is positioned at buried regions district 201.
In the present embodiment, second channel bottom is lower than top, buried regions district 201, that is, the bottom of conductive layer 217 is lower than top, buried regions district 201, conductive layer 217 is connected with buried regions district 201, when semiconductor structure is in running order, realize applying to buried regions district 201 voltage by conductive layer 217 external voltage, thus the scope carriers that increase buried regions district 201 surrounds is to the potential barrier of substrate 200, make the noise coupling in substrate 200 be difficult to enter in dopant well 218 by described potential barrier, improve the noise resisting ability of semiconductor structure.Further, the second channel bottom is positioned at border, buried regions district 201.
The material of described conductive layer 217 is the polysilicon of doping, and the doping type of conductive layer 217 is identical with the doping type in buried regions district 201, and the doping type of conductive layer 217 is N-type doping or the doping of P type.In order to reduce the impact of conductive layer 217 on semiconductor structure resistance, the Doped ions content in usual conductive layer 217 is higher, thus makes conductive layer 217 have less resistance.
In the present embodiment, the width of the second groove is greater than the width of the first groove and the 3rd groove, and is formed with separator 219 at the sidewall of the second groove, and the separator 219 at described second trenched side-wall place can stop the ion diffuse of the second trenched side-wall place conductive layer 217.Further, because the width of the first groove and the 3rd groove is less, the area of semiconductor structure can be reduced, meet the miniaturization trend of semiconductor.
The material on described barrier layer 216 is silica, silicon nitride or silicon oxynitride.The barrier layer 216 being positioned at the first groove and the second groove both can stop the ion diffuse of conductive layer 217 bottom section, also the ion diffuse of conductive layer 217 sidewall areas can be stopped, prevent the Doped ions in conductive layer 217 from diffusing to undesirably region, be electrically connected with undesirably region or puncture, thus improve reliability and the electric property of semiconductor structure.
Because the diffusion stopping Doped ions in conductive layer 217 can be played in barrier layer 216, by arranging position and the width of barrier layer 216 and conductive layer 217, barrier layer 216, close together between conductive layer 217 and dopant well 218 can be made, it is less that barrier layer 216 and conductive layer 217 account for chip area, meets semiconductor miniaturization, microminiaturized development trend.
The doping type of described dopant well 218 can be identical or contrary with the doping type in buried regions district 201.
To sum up, the technical scheme of semiconductor structure provided by the invention has the following advantages:
First, semiconductor structure of the present invention comprises the buried regions district being positioned at substrate, be positioned at the first groove of substrate, the second groove and the 3rd groove, and the first groove and the 3rd groove lay respectively at the second groove both sides, the second channel bottom at least exposes top, buried regions district; Fill the conductive layer of full second groove, conductive layer is connected with buried regions district, in the substrate that conductive layer and buried regions district surround, have dopant well; When semiconductor structure is in running order, voltage is applied to buried regions district by conductive layer, the charge carrier surrounded described in increase buried regions district is to the potential barrier of substrate, and the increase of described potential barrier makes the noise diffusion in substrate reduce to the ability of dopant well, thus improves the noise resisting ability of semiconductor structure; And, first groove and the 3rd groove lay respectively at the second groove both sides, and there is the barrier layer of filling full first groove and the 3rd groove, described barrier layer stops that the Doped ions in conductive layer diffuses to dopant well, prevent Doped ions and dopant well hypotelorism in conductive layer, thus improve reliability and the electric property of semiconductor structure.
Secondly, the width of the second groove is greater than the width of the first groove and the 3rd groove, makes the first groove and the 3rd groove account for chip area less, and namely to account for chip area less on barrier layer, thus make semiconductor structure meet miniaturization, microminiaturized development trend.
Again, the second trenched side-wall has separator, and described separator prevents the diffusion of conductive layer side-walls Doped ions further, thus improves reliability and the electric property of semiconductor structure further.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided;
In described substrate, form buried regions district, described buried regions district has electric conductivity, and has Doped ions in described buried regions district;
Etching removes the substrate of segment thickness, and in described substrate, form the first groove of annular, the second groove and the 3rd groove, described first groove and the 3rd groove lay respectively at the both sides of the second groove, and the second channel bottom at least exposes top, buried regions district;
Form the barrier layer of filling full described first groove and the 3rd groove;
Form the conductive layer of filling full described second groove, described conductive layer is connected with buried regions district, and the doping type of described conductive layer is identical with the doping type in buried regions district;
Dopant well is formed in the substrate that described conductive layer and buried regions district surround;
Grid structure is formed on described dopant well surface;
In the dopant well of described grid structure both sides, form doped region, annealing in process is carried out to doped region.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, the distance between described first groove and the second groove, distance between the 3rd groove and the second groove are 10 dust to 1000 dusts.
3. the formation method of semiconductor structure according to claim 1, it is characterized in that, described second channel bottom comprises at least exposing top, buried regions district: the second channel bottom exposes top, buried regions district; Second channel bottom is positioned at buried regions district.
4. the formation method of semiconductor structure according to claim 1, it is characterized in that, described second channel bottom is positioned at border, buried regions district.
5. the formation method of semiconductor structure according to claim 1, it is characterized in that, the width of described first groove and the 3rd groove is less than the width of the second groove.
6. the formation method of semiconductor structure according to claim 1, is characterized in that, also comprise step: while forming the barrier layer of filling full described first groove and the 3rd groove, forms separator at the second channel bottom and sidewall; Remove the separator being positioned at the second channel bottom, expose the buried regions district of the second channel bottom.
7. the formation method of semiconductor structure according to claim 1, it is characterized in that, the material on described barrier layer is silica, silicon nitride or silicon oxynitride.
8. the formation method of semiconductor structure according to claim 1, is characterized in that, adopts chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process to form described barrier layer.
9. the formation method of semiconductor structure according to claim 8, it is characterized in that, the technological parameter of described chemical vapor deposition method is: reacting gas comprises silicon source gas and oxygen source gas, and wherein, silicon source gas is TEOS or SiH
4, oxygen source gas is O
2or O
3, silicon source gas flow is 10sccm to 100sccm, and oxygen source gas flow is 50sccm to 100sccm, and radio-frequency power is 2000 watts to 4000 watts, and bias power is 1000 watts to 2500 watts.
10. the formation method of semiconductor structure according to claim 1, it is characterized in that, the bottom of described first groove and the 3rd groove is lower than top, buried regions district.
The formation method of 11. semiconductor structures according to claim 1, it is characterized in that, described first groove, the second groove and the 3rd groove are formed in processing step.
The formation method of 12. semiconductor structures according to claim 1, is characterized in that, the material of described conductive layer is the polysilicon of doping.
13. 1 kinds of semiconductor structures, is characterized in that, comprising:
Substrate;
Be positioned at the buried regions district of substrate, described buried regions district has electric conductivity, and has Doped ions in described buried regions district;
Be positioned at the first groove of the annular of substrate, the second groove and the 3rd groove, and described first groove and the 3rd groove lay respectively at the second groove both sides, and described second channel bottom at least exposes top, buried regions district;
Fill the barrier layer of full described first groove and the 3rd groove;
Fill the conductive layer of full described second groove, described conductive layer is connected with buried regions district, and the doping type of described conductive layer is identical with the doping type in buried regions district;
Be positioned at the dopant well of the substrate of conductive layer and the encirclement of buried regions district;
Be positioned at the grid structure on dopant well surface;
Be positioned at the doped region of the dopant well of grid structure both sides.
14., according to semiconductor structure described in claim 13, is characterized in that, the distance between described first groove and the second groove, distance between the 3rd groove and the second groove are 10 dust to 1000 dusts.
15., according to semiconductor structure described in claim 13, is characterized in that, described second channel bottom comprises at least exposing top, buried regions district: the second channel bottom exposes top, buried regions district; Second channel bottom is positioned at buried regions district.
16., according to semiconductor structure described in claim 13, is characterized in that, described second channel bottom is positioned at border, buried regions district.
17., according to semiconductor structure described in claim 13, is characterized in that, the width of described second groove is greater than the width of the first groove and the 3rd groove.
18., according to semiconductor structure described in claim 13, is characterized in that, the sidewall of described second groove has separator.
19., according to semiconductor structure described in claim 13, is characterized in that, the bottom of described first groove and the 3rd groove is lower than top, buried regions district.
20., according to semiconductor structure described in claim 13, is characterized in that, the material on described barrier layer is silica, silicon nitride or silicon oxynitride.
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| US7071530B1 (en) * | 2005-01-27 | 2006-07-04 | International Business Machines Corporation | Multiple layer structure for substrate noise isolation |
| CN1992272A (en) * | 2005-12-27 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| US20130270557A1 (en) * | 2012-04-13 | 2013-10-17 | Jian-Bin Shiu | Test structure for semiconductor process and method for monitoring semiconductor process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7071530B1 (en) * | 2005-01-27 | 2006-07-04 | International Business Machines Corporation | Multiple layer structure for substrate noise isolation |
| CN1992272A (en) * | 2005-12-27 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| US20130270557A1 (en) * | 2012-04-13 | 2013-10-17 | Jian-Bin Shiu | Test structure for semiconductor process and method for monitoring semiconductor process |
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