CN104900485A - Nano dielectric layer preparation method based on thermal oxidation process - Google Patents

Nano dielectric layer preparation method based on thermal oxidation process Download PDF

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Publication number
CN104900485A
CN104900485A CN201510164402.XA CN201510164402A CN104900485A CN 104900485 A CN104900485 A CN 104900485A CN 201510164402 A CN201510164402 A CN 201510164402A CN 104900485 A CN104900485 A CN 104900485A
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dielectric layer
silicon wafer
mask
metal layer
preparation
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CN104900485B (en
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贺涛
芦姗
胡海峰
韩运忠
周傲松
张涛
王颖
高文军
徐明明
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Beijing Institute of Spacecraft System Engineering
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Beijing Institute of Spacecraft System Engineering
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer

Abstract

A nano dielectric layer preparation method based on a thermal oxidation process of the invention belongs to the technical field of microelectronics, solid-state electronics and nano science. A square mask window is opened on a base metal layer by electron beam lithography. The base metal layer exposed at the mask window is oxidized by a thermal oxidation method. The specific process conditions are as follows: a silicon wafer is put in a drying oven and heated at 150-200 DEG C for 15-60min, the silicon wafer is immersed in butanone reagent for heating and ultrasonic processing, and mask stripping is completed. Characterization results show that the nano dielectric layer preparation method based on a thermal oxidation process can be used to prepare a dielectric layer film with certain oxidation ratio and certain thickness successfully. A dielectric layer is generated on the surface of the base metal layer in one step through in-situ oxidation. The preparation process is simple. No material needs to be added. The interface is highly coherent and has fewer defects. The method is expected to be widely used in scientific research and production.

Description

A kind of nanometer dielectric layer preparation method based on thermal oxidation technology
Technical field
The present invention relates to a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, belong to microelectronics and solid electronics, nanoscale science and technology field.
Background technology
Tunnel-through diode (TD) is a kind of novel high speed nano-device utilizing quantum effect to form, and has high-frequency rectification characteristic.Conventional tunnel-through diode has resonance tunnel-through diode (RTD), material-insulator-material tunnel-through diode (MIM-TD), and wherein, MIM-TD structure is simple, is subject to extensive concern.The intermediate insulating layer of MIM-TD is very thin, and under the effect of tunneling effect, electronics can move to another layer of conductive material from layer of conductive material like a cork, and this tunneling time is short to femtosecond magnitude, and this makes MIM-TD become the optimal selection of high-frequency rectification.
Usually, when making the dielectric layer of MIM-TD, mostly vacuum deposition method is adopted, such as magnetically controlled sputter method, Atomic layer deposition method.If select this class methods, when prepared by dielectric layer, need additionally to prepare target, this dielectric layer preparation manipulation that causes is complicated, and Presence of an interface defect between metal and dielectric layer in theory, serious conditions then has influence on rectification function.
Comprehensive foregoing, the dielectric layer complicated process of preparation of current MIM-TD, need the large-scale instruments such as supporting magnetron sputtering or ald, and need additionally to prepare target, this will cause device fabrication processes cost high.Meanwhile, in above-mentioned manufacturing process, issuable boundary defect is unfavorable for the device obtaining excellent performance.
Summary of the invention
The technical problem that the present invention solves is: overcome the deficiencies in the prior art, provide a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, when there is graphic mask, the metallic region at dielectric layer place is oxidized, technique is simple, without the need to additionally increasing material, the less dielectric layer of defect just can be obtained.
Technical scheme of the present invention is: a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, and step is as follows:
1) silicon wafer substrate is cleaned;
2) prepare substrate metal layer, substrate metal layer is placed on silicon wafer in the mode of electron beam evaporation;
3) preparation of dielectric layer mask
31) gluing is not with the rotating speed of 2000 ~ 6000rpm idle running silicon wafer, clean to make the organic solvent on silicon wafer volatilize;
32) with the rotating speed of 2000 ~ 6000rpm coating ZEP520 photoresist 1 ~ 5min, then in thermal station 150 ~ 200 DEG C of front baking 2 ~ 8min;
33) utilize electron beam exposure, substrate metal layer exposes the square of 0.3 μm × 0.3 μm ~ 1 μm × 1 μm, form square mask;
34) utilize paraxylene to carry out development 1 ~ 5min to ZEP520 photoresist, utilize isopropyl alcohol to carry out fixing 1 ~ 3min to ZEP520 photoresist, utilize n-hexane to carry out negative ions to ZEP520 photoresist and exchange 20 ~ 60s, naturally dry;
35) oxygen plasma treatment machine is utilized, to step 33) square mask that produces removes cull, obtains dielectric layer mask; Described oxygen plasma treatment machine back end vacuum is 0.3 ~ 0.7Torr, passes into oxygen flow 10 ~ 50sccm, power 50 ~ 120watt, time 20 ~ 60s;
4) preparation of dielectric layer film
Baking oven is made to be warming up to 150 ~ 200 DEG C at 1 ~ 2h, then silicon wafer is put into baking oven, thermal oxidation is carried out to the substrate metal layer surface in mask, after heating maintenance 15 ~ 60min, silicon wafer is placed in air and naturally cools to room temperature, generate nano-metal-oxide dielectric layer;
5) ultrasonic machine is utilized to carry out photoresist lift off to wafer
Silicon wafer with mask is soaked in butanone solution, is placed in thermal station 60 DEG C of heating 15min, then under the power of 30 ~ 60% ultrasonic 2min, clear water is cleaned, and dries up.
The present invention's advantage is compared with prior art:
Now the method for magnetron sputtering or ald that adopts prepares Homogeneous media layer more, and the two equipment needed thereby is complicated, causes preparation process comparatively lengthy and tedious.Adopt magnetically controlled sputter method to prepare dielectric layer, because material granule degree is comparatively large, be difficult to obtain thickness and be less than 10nm, uniform dielectric layer film; In addition, the growth mechanism of dielectric layer film be preferentially in local with island growth, cause the dielectric layer film of preparation and the contact portion of substrate metal layer to there is certain defect.Adopt Atomic layer deposition method to prepare dielectric layer, although can the thickness of accurate control medium layer film, in preparation process, introducing the reactant species of more non-dielectric layer chemical composition, there is certain impure phenomenon in the dielectric layer film prepared.
Be different from the method for manufacturing thin film such as magnetron sputtering and ald, the present invention develops a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, silicon wafer with substrate metal layer and dielectric layer mask is put in (in baking oven) in airtight air atmosphere and carries out heated at constant temperature, the substrate metal layer at mask window place (part of exposure) is oxidized by slow, uniform In Situ Heating, not only make dielectric layer uniform component, heat treated mode more decreases the defect in base metal level and dielectric layer.In addition, by changing heating time and temperature, the dielectric layer film that thickness is less and controlled is obtained.In addition, in oxidizing process, substrate metal layer covered by photoresist is not oxidized, oxidized through overexposure, the substrate metal layer at mask window place that comes out of developing, and adopts this invention can the size of control medium layer film area coverage simultaneously.
Accompanying drawing explanation
Fig. 1 is the making schematic diagram of the substrate metal layer of invention example;
Fig. 2 is the making schematic diagram of invention example dielectric layer;
Fig. 3 is the Making programme figure of invention example nanometer dielectric layer.
Embodiment
Below in conjunction with accompanying drawing and example, the invention will be further described.
1) substrate cleaning
11) substrate used crystal chip is the silicon wafer with 2 μm of silicon dioxide layers.Concrete cleaning step is as follows: utilize ultrasonic machine, silicon wafer is soaked in the power ultrasonic 15min with 40% in acetone, silicon wafer is soaked in the power ultrasonic 15min with 40% in isopropyl alcohol, and deionized water is cleaned, and dries up;
12) be soaked in by silicon wafer in the mixed liquor of the concentrated sulfuric acid and hydrogen peroxide (5:1), in 70 DEG C of heating 15min, deionized water is cleaned;
13) silicon wafer is soaked in the mixed liquor of water, hydrogen peroxide and ammoniacal liquor (7:2:1), in 70 DEG C of heating 15min;
14) be soaked in by silicon wafer in the mixed liquor of water, hydrogen peroxide and concentrated hydrochloric acid (7:2:1), in 70 DEG C of heating 15min, deionized water is cleaned, and dries up;
2) metal layer thin film preparation
21) utilize sol evenning machine, gluing is not with the speed of 3000rpm idle running 3min.By the ZEP520 photoresist uniform fold of 40 μ L on silicon wafer, with the even glue 3min of the rotating speed of 3000rpm.Utilize thermal station, to silicon chip in 150 DEG C of heating 3min, form mask a as shown in Figure 1.
22) electron beam exposure instrument is utilized, with 230C/cm 2exposure dose ZEP520 photoresist film is exposed, exposing patterns is the square of 0.3 μm × 0.3 μm.Make silicon wafer be soaked in 3min in paraxylene successively, 2min in isopropyl alcohol, 40s in n-hexane, natural drying, complete development, fixing and negative ions exchange, form mask b as shown in Figure 1;
23) utilize oxygen plasma etching machine to remove cull to ZEP520 photoresist, back end vacuum is 0.6Torr, and passing into oxygen flow is 30sccm, power 80watt, time 40s;
24) utilize electron beam evaporation instrument evaporation metal layer film, back end vacuum is 5E -6mbar, under the line of 48mA, with speed evaporation 60nm titanium film.Naturally cool 10h, take out silicon wafer, form metal level a as shown in Figure 1;
25) silicon wafer is soaked in 5min in the glassware that butanone solution is housed, is taken out by silicon wafer from glassware, clear water is cleaned, and dries up, completes stripping, forms metal level b as shown in Figure 1;
3) preparation of dielectric layer mask
31) utilize sol evenning machine, by the 2nd) step prepare complete silicon wafer not gluing with the rotating speed of 4000rpm idle running 3min, to make the volatilization of the organic solvent on silicon wafer clean;
32) by the ZEP520 uniform fold of 40 μ L on silicon wafer, with the rotating speed of 4000rpm coating ZEP520 photoresist 3min, utilize thermal station, to silicon chip in 150 DEG C of heating 3min, form ZEP520 photoresist, form mask c as shown in Figure 2;
33) utilize electron beam exposure instrument, expose with the exposure dose of 230C/cm2 to ZEP520 photoresist, exposing patterns is the square of 0.5 μm × 0.5 μm.Make silicon wafer be soaked in 3min in paraxylene successively, 2min in isopropyl alcohol, 40s in n-hexane, natural drying, complete development, fixing and negative ions exchange;
34) utilize oxygen plasma etching machine to remove cull to ZEP520 photoresist, back end vacuum is 0.6Torr, and passing into oxygen flow is 30sccm, power 80watt, time 40s, forms mask d as shown in Figure 2.
4) preparation of dielectric layer film
Make baking oven 1.5h be warming up to 150 DEG C, then silicon wafer is put into baking oven constant temperature oxidation 60min, the metal layer thin film in thermal oxidation square.Afterwards, be placed in air and naturally cool to room temperature.
5) ultrasonic machine is utilized to peel off mask
Being soaked in by silicon wafer is equipped with in the glassware of butanone solution, glassware is placed in thermal station and heats 15min, again glassware is put into ultrasonic machine with 40% power ultrasonic 3min, silicon wafer is taken out from glassware, clear water is cleaned, dry up, complete stripping, form dielectric layer as shown in Figure 2.
In sum, Fig. 3 gives the Making programme figure of nanometer dielectric layer.
Performance Detection
Utilize the constituent of x-ray photoelectron spectroscopy (XPS) quantitative analysis dielectric layer film, silicon wafer is positioned in XPS chamber, when analysis room's vacuum degree is close to 1 × 10E -7test during Pa, adopt monochromatization Al K αx-ray source, voltage is set to 15kV.Programming is automatically carried out XPS and is adopted spectrum.The system processes data using instrument to carry, utilizes standard C 1s peak position 284.8eV to calibrate, and confirms element kind, valence state and relative amount thereof according to handbook.Test result is, the titanyl of dielectric layer film is than being Ti:O=0.41:0.59, and gained oxide is TiO 1.44.
Utilize spectroscopic ellipsometers to analyze the thickness of dielectric layer film, the thickness recording dielectric layer film is 5.0nm.
The content be not described in detail in specification of the present invention belongs to the known technology of those skilled in the art.

Claims (1)

1., based on a nanometer dielectric layer preparation method for thermal oxidation technology, it is characterized in that step is as follows:
1) silicon wafer substrate is cleaned;
2) prepare substrate metal layer, substrate metal layer is placed on silicon wafer in the mode of electron beam evaporation;
3) preparation of dielectric layer mask
31) gluing is not with the rotating speed of 2000 ~ 6000rpm idle running silicon wafer, clean to make the organic solvent on silicon wafer volatilize;
32) with the rotating speed of 2000 ~ 6000rpm coating ZEP520 photoresist 1 ~ 5min, then in thermal station 150 ~ 200 DEG C of front baking 2 ~ 8min;
33) utilize electron beam exposure, substrate metal layer exposes the square of 0.3 μm × 0.3 μm ~ 1 μm × 1 μm, form square mask;
34) utilize paraxylene to carry out development 1 ~ 5min to ZEP520 photoresist, utilize isopropyl alcohol to carry out fixing 1 ~ 3min to ZEP520 photoresist, utilize n-hexane to carry out negative ions to ZEP520 photoresist and exchange 20 ~ 60s, naturally dry;
35) oxygen plasma treatment machine is utilized, to step 33) square mask that produces removes cull, obtains dielectric layer mask; Described oxygen plasma treatment machine back end vacuum is 0.3 ~ 0.7Torr, passes into oxygen flow 10 ~ 50sccm, power 50 ~ 120watt, time 20 ~ 60s;
4) preparation of dielectric layer film
Baking oven is made to be warming up to 150 ~ 200 DEG C at 1 ~ 2h, then silicon wafer is put into baking oven, thermal oxidation is carried out to the substrate metal layer surface in mask, after heating maintenance 15 ~ 60min, silicon wafer is placed in air and naturally cools to room temperature, generate nano-metal-oxide dielectric layer;
5) ultrasonic machine is utilized to carry out photoresist lift off to wafer
Silicon wafer with mask is soaked in butanone solution, is placed in thermal station 60 DEG C of heating 15min, then under the power of 30 ~ 60% ultrasonic 2min, clear water is cleaned, and dries up.
CN201510164402.XA 2015-04-09 2015-04-09 A kind of nanometer dielectric layer preparation method based on thermal oxidation technology Active CN104900485B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1266286A (en) * 1999-03-03 2000-09-13 光颉科技股份有限公司 RC semiconductor integrated circuit with MIS pulse protector
US20040070030A1 (en) * 2002-10-09 2004-04-15 Chindalore Gowrishankar L. Non-volatile memory device and method for forming
CN103151245A (en) * 2013-03-28 2013-06-12 中国科学院上海微系统与信息技术研究所 Thin film patterning method
CN104485279A (en) * 2014-12-11 2015-04-01 国家纳米科学中心 Transparent electrode based on metal nanometer grid and preparing method of transparent electrode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1266286A (en) * 1999-03-03 2000-09-13 光颉科技股份有限公司 RC semiconductor integrated circuit with MIS pulse protector
US20040070030A1 (en) * 2002-10-09 2004-04-15 Chindalore Gowrishankar L. Non-volatile memory device and method for forming
CN103151245A (en) * 2013-03-28 2013-06-12 中国科学院上海微系统与信息技术研究所 Thin film patterning method
CN104485279A (en) * 2014-12-11 2015-04-01 国家纳米科学中心 Transparent electrode based on metal nanometer grid and preparing method of transparent electrode

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
张士钧: "天线电池用MIM隧道二极管的制备及表征", 《中国优秀硕士学位论文全文数据库信息科技辑》 *

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