CN104900485B - A kind of nanometer dielectric layer preparation method based on thermal oxidation technology - Google Patents
A kind of nanometer dielectric layer preparation method based on thermal oxidation technology Download PDFInfo
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- CN104900485B CN104900485B CN201510164402.XA CN201510164402A CN104900485B CN 104900485 B CN104900485 B CN 104900485B CN 201510164402 A CN201510164402 A CN 201510164402A CN 104900485 B CN104900485 B CN 104900485B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
Abstract
A kind of nanometer dielectric layer preparation method based on thermal oxidation technology of the present invention, belongs to microelectronics and Solid State Electronics, nanoscale science and technology field.Using electron beam lithography, a square mask window is opened on substrate metal layer.The substrate metal layer exposed at mask window is aoxidized using thermal oxidation process, concrete technology condition is：It is placed in 150~200 DEG C of 15~60min of heating of baking oven, butanone reagent by heating, ultrasound, completes mask and peel off.Characterization result shows that the nanometer dielectric layer preparation method based on thermal oxidation technology can be prepared successfully with certain oxidation ratio and certain thickness medium layer film.The present invention is using one-step method in substrate metal layer surface in situ oxidation generation dielectric layer, and preparation technology is simple, and without added material, interface coherency is good, defect is few, is expected to be widely applied to scientific research and production.
Description
Technical field
The present invention relates to a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, belong to microelectronics and solid electronic
, nanoscale science and technology field.
Background technology
Tunnel-through diode (TD) is a kind of novel high speed nano-device constituted using quantum effect, special with high-frequency rectification
Property.Conventional tunnel-through diode has resonance tunnel-through diode (RTD), material-insulator-material tunnel-through diode (MIM-TD),
Wherein, MIM-TD is simple in construction, receives significant attention.MIM-TD intermediate insulating layer is very thin, in the presence of tunneling effect,
Electronics easily can move to another layer of conductive material from layer of conductive material, and the tunneling time is short to femtosecond magnitude, and this makes
Obtaining MIM-TD turns into the optimal selection of high-frequency rectification.
Generally when making MIM-TD dielectric layer, mostly using vacuum deposition method, such as magnetically controlled sputter method, atom
Deposition method.If this to cause dielectric layer system when prepared by dielectric layer, it is necessary to additionally prepare target from such method
Standby complex operation, and in theory in metal and medium interlayer Presence of an interface defect, serious conditions then have influence on rectification function.
Summary content, current MIM-TD dielectric layer preparation technology complexity is, it is necessary to supporting magnetron sputtering or atomic layer
The large-scale instruments such as deposition, and extra preparation target is needed, this will cause device fabrication processes cost high.Meanwhile, in above-mentioned system
During work, it is possible to create boundary defect be unfavorable for obtaining the device of excellent performance.
The content of the invention
Present invention solves the technical problem that being：Overcome the deficiencies in the prior art there is provided a kind of based on thermal oxidation technology
Nanometer dielectric layer preparation method, in the case where there is graphic mask, is aoxidized, technique to the metallic region where dielectric layer
Simply, without extra increase material, it is possible to obtain the less dielectric layer of defect.
The technical scheme is that：A kind of nanometer dielectric layer preparation method based on thermal oxidation technology, step is as follows：
1) silicon wafer substrate is cleaned；
2) substrate metal layer is prepared, substrate metal layer is placed on silicon wafer in the way of electron beam evaporation；
3) preparation of dielectric layer mask
31) gluing is not with 2000~6000rpm rotating speed idle running silicon wafer, so that the organic solvent volatilization on silicon wafer is dry
Only；
32) ZEP520 1~5min of photoresist are coated with 2000~6000rpm rotating speed, then 150~200 DEG C in thermal station
2~8min of front baking；
33) electron beam exposure is utilized, exposes the square of 1 μm of 0.3 μ m, 0.3 μm~1 μ m on substrate metal layer,
Form square mask；
34) 1~5min of development is carried out to ZEP520 photoresists using paraxylene, using isopropanol to ZEP520 photoresists
Fixing 1~3min is carried out, carrying out negative ions to ZEP520 photoresists using n-hexane exchanges 20~60s, dries naturally；
35) oxygen plasma processor being utilized, to step 33) square mask that produces removes cull, and obtain dielectric layer and cover
Film；The oxygen plasma processor back end vacuum is 0.3~0.7Torr, is passed through 10~50sccm of oxygen flow, power 50~
120watt, 20~60s of time；
4) preparation of medium layer film
Make baking oven be warming up to 150~200 DEG C in 1~2h, then silicon wafer is put into baking oven, to the substrate gold in mask
Belong to layer surface and carry out thermal oxidation, heating keeps after 15~60min, silicon wafer is placed in air and naturally cools to room temperature,
Generate nano-metal-oxide dielectric layer；
5) photoresist lift off is carried out to chip using ultrasonic machine
Silicon wafer with mask is soaked in butanone solution, 60 DEG C of heating 15min are placed in thermal station, then 30~
Ultrasound 2min under 60% power, clear water is cleaned, drying.
The advantage of the present invention compared with prior art is：
Now many methods using magnetron sputtering or ald prepare Homogeneous media layer, and the two required equipment is complicated, causes
Make preparation process more lengthy and tedious.Dielectric layer is prepared using magnetically controlled sputter method, because material granule degree is larger, thickness is hardly resulted in
Less than 10nm, uniform medium layer film；In addition, the growth mechanism of medium layer film is preferentially in part with island growth, cause
The medium layer film of preparation and the contact portion of substrate metal layer is set to there is certain defect.Prepared and be situated between using Atomic layer deposition method
Matter layer, although the thickness of medium layer film can be precisely controlled, in preparation process, introduces more non-dielectric layer chemistry
There is certain impure phenomenon in the reactant species of composition, the medium layer film prepared.
Different from method for manufacturing thin film such as magnetron sputtering and alds, the present invention develops a kind of based on thermal oxide work
The nanometer dielectric layer preparation method of skill, the silicon wafer with substrate metal layer and dielectric layer mask is put in closed air atmosphere
In (in baking oven) carry out heated at constant temperature, make at mask window the substrate metal layer of (exposed part) by slow, uniform original position
Heated oxide, not only makes dielectric layer uniform component, and the mode of heat treatment more reduces the defect in base metal level and dielectric layer.
In addition, the smaller and controllable medium layer film of thickness can be obtained by changing heat time and temperature.In addition, in oxidizing process
In, the substrate metal layer being covered by photoresist is not oxidized, the substrate where the mask window being exposed through overexposure, development
Metal level is oxidized, and can control the size of medium layer film area coverage simultaneously using this invention.
Brief description of the drawings
Fig. 1 is the making schematic diagram of the substrate metal layer of invention example；
Fig. 2 is the making schematic diagram of invention example dielectric layer；
Fig. 3 is the Making programme figure of invention example nanometer dielectric layer.
Embodiment
The invention will be further described with example below in conjunction with the accompanying drawings.
1) substrate is cleaned
11) substrate used crystal chip is the silicon wafer with 2 μm of silicon dioxide layers.Specific cleaning step is as follows：Utilize ultrasound
Machine, silicon wafer is soaked in acetone with 40% power ultrasonic 15min, silicon wafer is soaked in isopropanol with 40% work(
Rate ultrasound 15min, deionized water is cleaned, drying；
12) silicon wafer is soaked in the concentrated sulfuric acid and hydrogen peroxide (5:1) in mixed liquor, 15min, deionization are heated in 70 DEG C
Water is cleaned；
13) silicon wafer is soaked in water, hydrogen peroxide and ammoniacal liquor (7：2：1) in mixed liquor, 15min is heated in 70 DEG C；
14) silicon wafer is soaked in water, hydrogen peroxide and concentrated hydrochloric acid (7：2：1) in mixed liquor, 15min is heated in 70 DEG C,
Deionized water is cleaned, drying；
2) prepared by metal layer thin film
21) sol evenning machine is utilized, gluing is not with 3000rpm speed idle running 3min.40 μ L ZEP520 photoresists is uniform
It is covered on silicon wafer, with 3000rpm rotating speed spin coating 3min.Using thermal station, 3min is heated in 150 DEG C to silicon chip, formed
Mask a as shown in Figure 1.
22) electron beam exposure instrument is utilized, with 230C/cm2Exposure dose ZEP520 photoresist films are exposed,
Exposing patterns are the square of 0.3 μm of 0.3 μ m.Silicon wafer is made to be soaked in 2min in 3min in paraxylene, isopropanol successively,
40s in n-hexane, is spontaneously dried, and is completed development, fixing and negative ions and is exchanged, forms mask b as shown in Figure 1；
23) cull is removed to ZEP520 photoresists using oxygen plasma etching machine, back end vacuum is 0.6Torr, is passed through oxygen
Flow is 30sccm, power 80watt, time 40s；
24) electron beam evaporation instrument evaporation metal layer film is utilized, back end vacuum is 5E-6Mbar, under 48mA line, withSpeed evaporation 60nm titanium films.Natural cooling 10h, takes out silicon wafer, forms metal level a as shown in Figure 1；
25) silicon wafer is soaked in 5min in the glassware equipped with butanone solution, silicon wafer is taken from glassware
Go out, clear water is cleaned, drying, complete to peel off, form metal level b as shown in Figure 1；
3) preparation of dielectric layer mask
31) utilize sol evenning machine, by the 2) step prepare the silicon wafer that finishes gluing do not dallied 3min with 4000rpm rotating speed,
So that the organic solvent volatilization on silicon wafer is clean；
32) 40 μ L ZEP520 uniform folds are coated into ZEP520 photoresists on silicon wafer with 4000rpm rotating speed
3min, using thermal station, heats 3min in 150 DEG C to silicon chip, forms ZEP520 photoresists, form mask c as shown in Figure 2；
33) electron beam exposure instrument is utilized, ZEP520 photoresists are exposed with 230C/cm2 exposure dose, is exposed
Pattern is the square of 0.5 μm of 0.5 μ m.Make silicon wafer be soaked in 2min in 3min in paraxylene, isopropanol successively, just oneself
40s in alkane, is spontaneously dried, and is completed development, fixing and negative ions and is exchanged；
34) cull is removed to ZEP520 photoresists using oxygen plasma etching machine, back end vacuum is 0.6Torr, is passed through oxygen
Flow is 30sccm, power 80watt, time 40s, forms mask d as shown in Figure 2.
4) preparation of medium layer film
Make baking oven 1.5h be warming up to 150 DEG C, silicon wafer is then put into baking oven constant temperature oxidation 60min, thermal oxidation is just
Metal layer thin film in square.Afterwards, it is placed in air and naturally cools to room temperature.
5) mask is peeled off using ultrasonic machine
Silicon wafer is soaked in the glassware equipped with butanone solution, glassware is placed in thermal station and heats 15min,
Glassware is put into ultrasonic machine with 40% power ultrasonic 3min again, silicon wafer is taken out from glassware, clear water is cleaned,
Drying, completes to peel off, forms dielectric layer as shown in Figure 2.
In summary, Fig. 3 gives the Making programme figure of nanometer dielectric layer.
Performance detection
Using the constituent of x-ray photoelectron spectroscopy (XPS) quantitative analysis medium layer film, silicon wafer is placed
In in XPS chambers, when analysis room's vacuum is close to 1 × 10E-7Tested during Pa, using monochromatization Al KαX-ray source, voltage
It is set to 15kV.The automatic XPS that carries out of programming adopts spectrum.The system processes data carried using instrument, utilizes standard C1s peak positions
284.8eV is calibrated, and element species, valence state and its relative amount are confirmed according to handbook.Test result is, medium layer film
Titanyl ratio is Ti:O=0.41:0.59, gained oxide is TiO1.44。
The thickness of medium layer film is analyzed using spectroscopic ellipsometers, the thickness for measuring medium layer film is 5.0nm.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.
Claims (1)
1. a kind of nanometer dielectric layer preparation method based on thermal oxidation technology, it is characterised in that step is as follows：
1) silicon wafer substrate is cleaned；
2) substrate metal layer is prepared, substrate metal layer is placed on silicon wafer in the way of electron beam evaporation；
3) preparation of dielectric layer mask
31) gluing is not with 2000~6000rpm rotating speed idle running silicon wafer, so that the organic solvent volatilization on silicon wafer is clean；
32) ZEP520 1~5min of photoresist, then 150~200 DEG C of front bakings 2 in thermal station are coated with 2000~6000rpm rotating speed
~8min；
33) electron beam exposure is utilized, exposes the square of 1 μm of 0.3 μ m, 0.3 μm~1 μ m on substrate metal layer, is formed
Square mask；
34) 1~5min of development is carried out to ZEP520 photoresists using paraxylene, ZEP520 photoresists is carried out using isopropanol
Fixing 1~3min, carries out negative ions to ZEP520 photoresists using n-hexane and exchanges 20~60s, dry naturally；
35) oxygen plasma processor being utilized, to step 33) square mask that produces removes cull, obtains dielectric layer mask；Institute
Oxygen plasma processor back end vacuum is stated for 0.3~0.7Torr, 10~50sccm of oxygen flow is passed through, power 50~
120watt, 20~60s of time；
4) preparation of medium layer film
Make baking oven be warming up to 150~200 DEG C in 1~2h, then silicon wafer is put into baking oven, to the substrate metal layer in mask
Surface carries out thermal oxidation, and heating keeps after 15~60min, silicon wafer is placed in air and naturally cools to room temperature, generates
Nano-metal-oxide dielectric layer；
5) photoresist lift off is carried out to chip using ultrasonic machine
Silicon wafer with mask is soaked in butanone solution, 60 DEG C of heating 15min in thermal station are placed in, then 30~60%
Ultrasound 2min under power, clear water is cleaned, drying.
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| CN201510164402.XA CN104900485B (en) | 2015-04-09 | 2015-04-09 | A kind of nanometer dielectric layer preparation method based on thermal oxidation technology |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266286A (en) * | 1999-03-03 | 2000-09-13 | 光颉科技股份有限公司 | RC semiconductor integrated circuit with MIS pulse protector |
| CN103151245A (en) * | 2013-03-28 | 2013-06-12 | 中国科学院上海微系统与信息技术研究所 | Thin film patterning method |
| CN104485279A (en) * | 2014-12-11 | 2015-04-01 | 国家纳米科学中心 | Transparent electrode based on metal nanometer grid and preparing method of transparent electrode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6887758B2 (en) * | 2002-10-09 | 2005-05-03 | Freescale Semiconductor, Inc. | Non-volatile memory device and method for forming |
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2015
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266286A (en) * | 1999-03-03 | 2000-09-13 | 光颉科技股份有限公司 | RC semiconductor integrated circuit with MIS pulse protector |
| CN103151245A (en) * | 2013-03-28 | 2013-06-12 | 中国科学院上海微系统与信息技术研究所 | Thin film patterning method |
| CN104485279A (en) * | 2014-12-11 | 2015-04-01 | 国家纳米科学中心 | Transparent electrode based on metal nanometer grid and preparing method of transparent electrode |
Non-Patent Citations (1)
| Title |
|---|
| 天线电池用MIM隧道二极管的制备及表征;张士钧;《中国优秀硕士学位论文全文数据库信息科技辑》;20131031(第2013年第10期);第27-29页 * |
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