CN104898311A - Chip, liquid crystal display panel and cell test method - Google Patents
Chip, liquid crystal display panel and cell test method Download PDFInfo
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- CN104898311A CN104898311A CN201510314976.0A CN201510314976A CN104898311A CN 104898311 A CN104898311 A CN 104898311A CN 201510314976 A CN201510314976 A CN 201510314976A CN 104898311 A CN104898311 A CN 104898311A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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- General Physics & Mathematics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The invention discloses a chip, a liquid crystal display panel and a cell test method. The chip comprises a high-resistance enablement port and an output port capable of being configured to have three states, and when the high-resistance enablement port receives a high-resistance enablement signal, the output port of the chip is configured to be a high-resistance state. If the chip provided by the invention is used in the liquid crystal display panel, when a cell test is performed on the liquid crystal display panel after welding of the chip is completed, the chip does not need to be taken down from the liquid crystal display panel, test time and test cost are saved, and the possibility of caused damage of the chip and a corresponding circuit board when the chip is taken down from the liquid crystal display panel can also be prevented.
Description
Technical field
The present invention relates to technical field of liquid crystal display, specifically, relate to a kind of chip, display panels and false pressure method of testing.
Background technology
In the manufacture process of liquid crystal display, need constantly to monitor the quality problems of product.In the process of quality monitoring, substandard product can be filtered out in time by monitoring result.Meanwhile, the link going wrong or exist risk can also be understood in liquid crystal display manufacture process according to monitoring result, to solve the problem in time, thus ensure the quality of the product obtained.
In the manufacture process of display panels, at welding display driver chip (Display Driver IC, referred to as DDIC) and touch control chip (Touch Controller IC, referred to as TCIC) front, usually need to carry out vacation pressure test (i.e. Cell Test) to LCD panel.Only in the test of vacation pressure, the satisfactory display panels of picture display effect just can enter into next website, to weld display driver chip and touch control chip.After display driver chip and touch control chips welding complete, also need to test the overall display effect of module and other performances, after whole test all meets correlated quality specification and customer requirement, this liquid crystal display can shipment to client.
But, in some cases (such as liquid crystal display inefficacy), after on the circuit board that display driver chip and/or touch control chips welding is corresponding in a liquid crystal display, also need that vacation pressure is carried out to display panels and test.Now, before carrying out the test of vacation pressure, just need first display driver chip and/or touch control chip to be taken off from circuit board.But, display driver chip and/or touch control chip being taken off from circuit board needs the equipment of specialty and personnel to operate, at present, if need to carry out this operation just liquid crystal display can only be returned to supplier to be operated to perform this by supplier, and the cycle that this process need is very long.
Meanwhile, the operation that display driver chip and/or touch control chip take off from circuit board probably can be damaged relevant chip and panel.So also just clearly cannot locate the principal element that liquid crystal display lost efficacy.
Summary of the invention
Technical matters to be solved by this invention is to solve when display panels completes the problem of carrying out after chips welding needing chip to take off from panel when false pressure is tested.For solving the problem, one embodiment of the present of invention provide firstly a kind of chip for liquid crystal display, described chip comprises high resistant enable port and can be configured to the output port of tri-state, when described high resistant enable port receives high resistant enable signal, the output port of described chip is configured to high-impedance state.
According to one embodiment of present invention, described high resistant enable signal is high level signal or low level signal.
According to one embodiment of present invention, described chip comprises multiple tri-state gate circuit, and the output terminal of described multiple tri-state gate circuit forms the output port of described chip.
According to one embodiment of present invention, the control end of described multiple tri-state gate circuit is all connected with described high resistant enable port.
According to one embodiment of present invention, described tri-state gate circuit is CMOS tri-state gate circuit.
Present invention also offers a kind of display panels, the test port that described display panels comprises chip bonding pad and is connected with described chip bonding pad, described chip bonding pad is connected with the corresponding ports of the chip be welded thereon, described test port is connected with the output port of described chip by described chip bonding pad, and described test port comprises high resistant enable signal input end.
According to one embodiment of present invention, described test port also comprises any one in following lising or several:
Sweep trace test lead, data line test lead and public electrode test lead.
According to one embodiment of present invention, described sweep trace test lead comprises the first sweep trace test lead and the second sweep trace test lead, wherein, described first sweep trace test lead is connected with the sweep trace of odd-numbered line in described display panels and the sweep trace of even number line respectively with the second sweep trace test lead.
Present invention also offers a kind of false pressure method of testing, described method comprises:
For completing the display panels of specifying chips welding, sending high resistant enable signal to the high resistant enable signal input end in the test port of described display panels, the output port of described appointment chip is configured to high-impedance state;
Send corresponding test signal to other test leads in described test port, thus realize the vacation pressure test to being welded with the display panels of specifying chip.
According to one embodiment of present invention, in the process,
For not completing the display panels of specifying chips welding, in described test port, each test lead sends corresponding test signal, thus realizes the vacation pressure test to not being welded with the display panels of specifying chip.
When chip provided by the present invention is used on display panels, the enable IC_EN of high resistant to chip is only needed to input high resistant enable signal, just can realize taking off identical effect with by chip from display panels, so also just no longer need chip to take off from display panels.This also makes, when carrying out the test of vacation pressure to the liquid crystal display after chips welding, no longer to need that display panels is returned to producer and taken off by chip, thus save time and the cost of test.Meanwhile, owing to no longer needing to be taken off from circuit board by chip, also just avoid the possibility of chip and the damage of related circuit plate.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in instructions, claims and accompanying drawing and obtain.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, do simple introduction by accompanying drawing required in embodiment or description of the prior art below:
Fig. 1 is the part-structure schematic diagram of chip according to an embodiment of the invention;
Fig. 2 is the circuit theory diagrams of tri-state gate circuit according to an embodiment of the invention;
Fig. 3 is the circuit theory diagrams of tri-state gate circuit in accordance with another embodiment of the present invention;
Fig. 4 is the schematic diagram of test port according to an embodiment of the invention;
Fig. 5 is the process flow diagram of false according to an embodiment of the invention pressure method of testing.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical matters whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Meanwhile, in the following description, many details have been set forth for illustrative purposes, to provide thorough understanding of embodiments of the invention.But, it will be apparent to those skilled in the art that the present invention can detail here or described ad hoc fashion implement.
Existing display panels is in welding after display driver chip and/or touch control chip, if need to carry out the test of vacation pressure to display panels, just need first display driver chip and touch control chip to be taken off from display panels, and then to corresponding test lead input test signal, to complete false pressure test operation.
But need to adopt the equipment of specialty by technical professional owing to taking off display driver chip or touch control chip from the circuit board of display panels, therefore this process often needs time and the cost of at substantial.Meanwhile, in the process of taking off display driver chip or touch control chip, probably can cause the damage of chip itself or circuit board.
For the above-mentioned problems in the prior art, the invention provides a kind of chip for liquid crystal display newly.
Fig. 1 shows the part-structure schematic diagram of the chip for liquid crystal display that the present embodiment provides.
As shown in Figure 1, the chip 100 that the present embodiment provides comprises high resistant enable port IC_EN and can be configured to the output port of tri-state.When high resistant enable port receives high resistant enable signal, all output ports of chip are all configured to high-impedance state.
When all output ports of chip are all in high-impedance state, chip also would not to other circuit output signals be connected with this chip, and this is also just equivalent to this chip and is in unsettled (floating) state.When chip is in vacant state, although chip is welded on the circuit board of display panels physically, but it seems from electrical structure, display panels can be equivalent to and do not weld this chip.
Particularly, the chip that the present embodiment provides adopts tri-state gate circuit to realize the output terminal of chip to be configured to the function of high-impedance state.Wherein, in this chip, each output port of chip is all configured with a tri-state gate circuit, and the control end of each tri-state gate circuit is all connected with high resistant enable port IC_EN.
As shown in Figure 1, in the present embodiment, first tri-state gate circuit 102a, the second tri-state gate circuit 102b signal port A1, A2 and A3 corresponding to chip internal with B3 with input end B1, B2 of the 3rd tri-state gate circuit 102c is connected, and the output terminal of these three tri-state gate circuits form respectively three output ports of chip 100 (i.e. output port OUT_1, output port OUT_2 and output port OUT_3).Meanwhile, the control end of above-mentioned three tri-state gate circuits is all connected with high resistant enable port IC_EN.
It should be noted that, Fig. 1 is only the structural drawing schematically showing the chip that the present embodiment provides, this chip not only just comprises three output ports, in other embodiments of the invention, the quantity of the output port of chip both can be 1 or 2, also for other reasonable values more than 3, can the present invention is not limited thereto.Meanwhile, also it is pointed out that Fig. 1 and the input port of not shown chip, when needs, the input port of chip also can be adopted and be configured to tri-state in a like fashion, the present invention is not limited thereto.
Fig. 2 shows the structural representation of the tri-state gate circuit that the present embodiment provides.The tri-state gate circuit that the present embodiment provides is CMOS tri-state gate circuit, and for this circuit, effective high resistant enable signal is low level signal.
As shown in Figure 2, the CMOS tri-state gate circuit that the present embodiment provides comprises: Sheffer stroke gate, two N channel enhancement metal-oxide-semiconductors (i.e. metal-oxide-semiconductor TN1 and metal-oxide-semiconductor TN2) and a P-channel enhancement type metal-oxide-semiconductor TP1.
When the signal that high resistant enable port IC_EN inputs is high level signal, metal-oxide-semiconductor TN2 conducting.Now, if the signal that the input end B1 of tri-state gate circuit inputs is high level signal, the signal C1 that so Sheffer stroke gate exports is then low level signal.Like this, metal-oxide-semiconductor TP1 is by conducting, and metal-oxide-semiconductor TN1 will end, thus makes the output terminal OUIT_1 of triple gate export high level signal.And if the signal that the input end B1 of tri-state gate circuit inputs is low level signal, the signal C1 that so Sheffer stroke gate exports is then high level signal.Like this, metal-oxide-semiconductor TP1 will end, and metal-oxide-semiconductor TN1 by conducting, thus makes the output terminal OUIT_1 output low level signal of triple gate.
When the signal that high resistant enable port IC_EN inputs is low level signal, metal-oxide-semiconductor TN2 ends.Now, the signal no matter the input end B1 of tri-state gate circuit inputs is high level signal or low level signal, and the signal C1 that Sheffer stroke gate exports is high level signal.Like this, metal-oxide-semiconductor TP1 will end, and metal-oxide-semiconductor TN1 is by conducting, and now the output terminal OUIT_1 of triple gate is in open-circuit condition, thus makes output terminal OUT_1 present high-impedance state.
It should be noted that, in different embodiments of the invention, tri-state gate circuit can also adopt other rational circuit forms to realize, and the present invention is not limited thereto.Meanwhile, it is pointed out that the circuit form adopted according to tri-state gate circuit, effective high resistant enable signal both may be low level signal, also may be high level signal.
Such as in one embodiment of the invention, tri-state gate circuit have employed circuit form as shown in Figure 3.For this tri-state gate circuit, effective high resistant enable signal is high level signal.
In addition, also it is pointed out that in different embodiments of the invention, said chip both can be display driver chip, can be also touch control chip, or be liquid crystal display circuit board in other rational chips, the present invention is not limited thereto.
Present invention also offers a kind of display panels, this display panels comprises chip bonding pad and test port.Wherein, chip bonding pad is connected with the corresponding ports of the chip be welded thereon, and test port is connected with the output port of chip by chip bonding pad.
Fig. 4 shows the structural representation of test port in the display panels that the present embodiment provides.
As shown in Figure 4, the test port 400 that the present embodiment provides comprises: sweep trace test lead 401, data line test lead 402, high resistant enable signal input end 403 and public electrode test lead 404.Wherein, public electrode test lead 404 is connected with the public electrode of display panels.
It should be noted that, in different embodiments of the invention, high resistant enable signal input port 403 in test port is required, and other test leads can be matched according to actual needs, in addition, test port can also comprise other ports (such as reserved port etc.), the present invention is not limited thereto.
Sweep trace test lead 401 comprises the first sweep trace test lead 401a and the second sweep trace test lead 401b.Wherein, the first sweep trace test lead 401a is connected with the sweep trace being in odd-numbered line in display panels, and the second sweep trace test lead 402b is connected with the sweep trace being in even number line in display panels.
In the present embodiment, data line test lead 402 contains further: the first data line test lead 402a, the second data line test lead 402b and the 3rd data line test lead 402c.Wherein, first data line test lead 402a is connected with the pixel electrode of red sub-pixel in the array base palte of display panels by corresponding data line, second data line test lead 402b is connected with the pixel electrode of array base palte Green sub-pix by corresponding data line, and the 3rd data line test lead 402c is connected with the pixel electrode of blue subpixels in array base palte by corresponding data line.
When the test of vacation pressure is carried out for display panels provided by the present invention, if this display panels is do not weld the panel of specifying chip (such as display driver chip), so just without the need to sending high resistant enable signal to the high resistant enable signal input end shown in Fig. 3, and existing vacation pressure method of testing (namely sending corresponding test signal to other test leads in test port) can be directly adopted to carry out testing.
And if this display panels is for having welded the panel of related chip (such as display driver chip), so when carrying out the test of vacation pressure to this panel, as shown in Figure 5, need to send high resistant enable signal to high resistant enable signal input end in step S501.Be welded on the high resistant enable port of the chip on display panels to be connected with the high resistant enable signal input port in test port, all output ports of chip, after receiving high resistant enable signal, all can be configured to high-impedance state by this chip.Now, this chip also just can be considered as being in vacant state.
In step S502, send corresponding test signal to other test leads (such as surface sweeping line test lead, data line test lead and/or public electrode test lead etc.) in test port, thus realize the vacation pressure test to display panels when not taken off from display panels by chip.
It should be noted that, in other embodiments of the invention, send high resistant enable signal to high resistant enable signal input end and can also carry out to the operation sending corresponding test signal to other test leads in test port simultaneously, the present invention is not limited thereto.
As can be seen from foregoing description, when the chip provided by the present embodiment is used on display panels, the enable IC_EN of high resistant to chip is only needed to input high resistant enable signal, just can realize taking off identical effect with by chip from display panels, so also just no longer need chip to take off from display panels.This also makes, when carrying out the test of vacation pressure to the liquid crystal display after chips welding, no longer to need that display panels is returned to producer and taken off by chip, thus save time and the cost of test.Meanwhile, owing to no longer needing to be taken off from circuit board by chip, the possibility of wafer damage is also just avoided.
It should be understood that disclosed embodiment of this invention is not limited to ad hoc structure disclosed herein and/or treatment step, and the equivalent of these features that those of ordinary skill in the related art understand should be extended to substitute.
Special characteristic, structure or characteristic that " embodiment " mentioned in instructions or " embodiment " mean to describe in conjunction with the embodiments comprise at least one embodiment of the present invention.Therefore, instructions various places throughout occur phrase " embodiment " or " embodiment " might not all refer to same embodiment.
Conveniently, multiple project, structural unit and/or component units can appear in common list as used herein.But each element that these lists should be interpreted as in this list is identified as member unique separately respectively.Therefore, when not having reverse side to illustrate, in this list, neither one member only can appear in common list the actual equivalent of other member any being just interpreted as same list based on them.In addition, can also come together with reference to various embodiment of the present invention and example together with for the alternative of each element at this.Should be understood that, these embodiments, example and substitute and be not interpreted as equivalent each other, and be considered to representative autonomous separately of the present invention.
In addition, described feature, structure or characteristic can be attached in one or more embodiment in any other suitable manner.In superincumbent description, provide some concrete details, such as quantity etc., to provide the complete understanding to embodiments of the invention.But those skilled in the relevant art will understand, the present invention just can realize without the need to above-mentioned one or more concrete details, or also can adopt the realizations such as other method, assembly, material.In other example, known structure, material or operation are not shown specifically or describe in order to avoid fuzzy various aspects of the present invention.
Although above-mentioned example is for illustration of the principle of the present invention in one or more application, but for a person skilled in the art, when not deviating from principle of the present invention and thought, obviously can in form, the details of usage and enforcement does various amendment and need not creative work be paid.Therefore, the present invention is limited by appending claims.
Claims (10)
1. the chip for liquid crystal display, it is characterized in that, described chip comprises high resistant enable port and can be configured to the output port of tri-state, and when described high resistant enable port receives high resistant enable signal, the output port of described chip is configured to high-impedance state.
2. chip as claimed in claim 1, it is characterized in that, described high resistant enable signal is high level signal or low level signal.
3. chip as claimed in claim 1 or 2, it is characterized in that, described chip comprises multiple tri-state gate circuit, and the output terminal of described multiple tri-state gate circuit forms the output port of described chip.
4. chip as claimed in claim 3, it is characterized in that, the control end of described multiple tri-state gate circuit is all connected with described high resistant enable port.
5. chip as claimed in claim 3, it is characterized in that, described tri-state gate circuit is CMOS tri-state gate circuit.
6. a display panels, it is characterized in that, the test port that described display panels comprises chip bonding pad and is connected with described chip bonding pad, described chip bonding pad is connected with the corresponding ports of the chip be welded thereon, described test port is connected with the output port of described chip by described chip bonding pad, and described test port comprises high resistant enable signal input end.
7. display panels as claimed in claim 6, is characterized in that, described test port also comprises any one in following lising or several:
Sweep trace test lead, data line test lead and public electrode test lead.
8. display panels as claimed in claim 7, it is characterized in that, described sweep trace test lead comprises the first sweep trace test lead and the second sweep trace test lead, wherein, described first sweep trace test lead is connected with the sweep trace of odd-numbered line in described display panels and the sweep trace of even number line respectively with the second sweep trace test lead.
9. a false pressure method of testing, it is characterized in that, described method comprises:
For completing the display panels of specifying chips welding, sending high resistant enable signal to the high resistant enable signal input end in the test port of described display panels, the output port of described appointment chip is configured to high-impedance state;
Send corresponding test signal to other test leads in described test port, thus realize the vacation pressure test to the display panels being welded with described appointment chip.
10. false pressure method of testing as claimed in claim 9, is characterized in that, in the process,
For not completing the display panels of specifying chips welding, in described test port, each test lead sends corresponding test signal, thus realizes the vacation pressure test to not being welded with the display panels of specifying chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510314976.0A CN104898311B (en) | 2015-06-10 | 2015-06-10 | A kind of chip, liquid crystal display panel and false pressure test method |
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| CN201510314976.0A CN104898311B (en) | 2015-06-10 | 2015-06-10 | A kind of chip, liquid crystal display panel and false pressure test method |
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| CN104898311A true CN104898311A (en) | 2015-09-09 |
| CN104898311B CN104898311B (en) | 2019-03-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901583A (en) * | 2010-06-07 | 2010-12-01 | 无锡新硅微电子有限公司 | Display drive circuit of LCD screen |
| CN102710478A (en) * | 2012-05-22 | 2012-10-03 | 天津理工大学 | Integration slave node device of Profibus-DP (profibus-data processing) and Modbus |
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2015
- 2015-06-10 CN CN201510314976.0A patent/CN104898311B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901583A (en) * | 2010-06-07 | 2010-12-01 | 无锡新硅微电子有限公司 | Display drive circuit of LCD screen |
| CN102710478A (en) * | 2012-05-22 | 2012-10-03 | 天津理工大学 | Integration slave node device of Profibus-DP (profibus-data processing) and Modbus |
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| CN104898311B (en) | 2019-03-19 |
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