CN104885219A

CN104885219A - Electrostatic discharge protection for electrical components, devices including such protection and methods for making the same

Info

Publication number: CN104885219A
Application number: CN201380067233.7A
Authority: CN
Inventors: D.汉比; A.斯科奇
Original assignee: Osram Sylvania Inc
Current assignee: Osram Sylvania Inc
Priority date: 2012-12-21
Filing date: 2013-12-16
Publication date: 2015-09-02
Also published as: WO2014099772A1; DE112013006122T5

Abstract

Systems and methods for protecting electrical components such as light emitting diodes are described. In some embodiments, electrical components are protected from high level electrostatic discharge ("ESD") events by a circuit board that provides an intrinsic level of ESD protection. At the same time, such electrical components are protected against low level ESD events by one or more diodes that are electrically coupled thereto. The one or more diodes may be thin film diodes comprising at least one layer of p-type semiconductive material and at least one layer of n-type semiconductive material. Devices including ESD protection and methods for manufacturing such devices are also described.

Description

For electric parts electrostatic discharge (ESD) protection, comprise the device of such protection and the method for making devices

The cross reference of related application

The application be submit in requirement on December 21st, 2012 and be entitled as " ELECTROSTATIC DISCHARGE PROTECTION FOR ELECTRICAL COMPONENTS; DEVICES INCLUDING SUCH PROTECTION AND METHODS FOR MAKING THE SAME(be used for electric parts electrostatic discharge (ESD) protection, comprise such protection device and for making its method) " U.S. Patent application No. 13/724; the international application of the rights and interests of 713, the overall content of this U. S. application is merged by this by reference.

Technical field

This application relates generally to provide the Electrostatic Discharge on printed circuit board (PCB) to protect, and relates more particularly to provide such protection in light-emitting diode (LED) system.

Background technology

From static discharge, be obtain well-verified problem to the infringement of electronic unit.Estimated by some, the financial cost of such infringement can exceed electronic product year gross sales amount 10.It also may affect productivity and product reliability across the electronics industry of wide region.

Light-emitting diode (LED) is the electronic unit of the type being subject to the infringement undertaken by ESD.ESD infringement can occur in the manufacture of LED, disposal, encapsulation or between erecting stage.The LED of large quantity is often aggregated in module to create the illuminator requiring esd protection.Surface installation and chip on board technology have been developed thinks that LED and other electronic circuit provide esd protection, but is subjected to one or more defect.Such as, such technology may require the pickup of the diode with surface mounting of large quantity and the manufacturing technology of placement and/or complexity.The circuit board comprising complete (such as, embedding) esd protection has also been developed to address these problems, but can not think that the parts of such as LED provide sufficient protection.Particularly, the circuit board with complete esd protection cannot protect such parts from producing the esd event of relatively little voltage with the electric current be associated in reverse bias.

Accompanying drawing explanation

Make reference to the following detailed description now, will read the following detailed description in conjunction with following figure, wherein, similar label represents similar part.

Figure 1A and Figure 1B respectively diagram diagrammatically comprises example modules according to esd protection of the present disclosure and array;

The circuit board that Fig. 2 diagram embeds according to exemplary ESD of the present disclosure;

Fig. 3 is the illustrative plot of certain electrical characteristics of dielectric material according to voltage switchable of the present disclosure;

Fig. 4 is according to exemplary esd protection circuit of the present disclosure;

Fig. 5 diagram diagrammatically comprises another example modules according to esd protection of the present disclosure;

Fig. 6 diagram diagrammatically comprises another exemplary array according to esd protection of the present disclosure;

Fig. 7 diagram is diagrammatically according to another esd protection circuit of the present disclosure;

Fig. 8 diagram diagrammatically comprises the exemplary arrangement of the electric parts according to esd protection of the present disclosure;

Fig. 9 A diagram diagrammatically comprises another exemplary arrangement of the electric parts according to esd protection of the present disclosure;

Fig. 9 B is the schematic representation of the cross section intercepted at the line A place of Fig. 9 A;

Figure 10 is the frame flow chart according to illustrative methods of the present disclosure; And

Figure 11 describes to manufacture process according to exemplary reel-to-reel of the present disclosure (reel to reel).

Embodiment

Light-emitting diode (LED) (photoelectric device of a type) be exposed to (such as, being caused by the transient event of such as Electrostatic Discharge) reverse bias voltage and be associated electric current time may be compromised.Really, modern LED is often extremely sensitive with the esd event of the electric current be associated to generating reverse bias voltage, and no matter those reverse bias voltage/electric currents are relatively large or relatively little.System and method of the present disclosure does not suffer the voltage produced in transient event (such as static discharge) period to solve this problem by the combination of the circuit board and one or more diode that use ESD embedding to protect the electronic unit of such as LED.As will be described in detail below, such system and method can protect responsive electronic unit not suffer low-level and high-level esd event.

In order to object of the present disclosure; term " circuit board that ESD embeds " means when not using other parts that may be attached or deposit on circuit board; and particularly provide when not using one or more diode from the circuit board (such as, printed circuit board (PCB)) in the protection of level in esd event.In certain embodiments, the circuit board that ESD described here embeds can be protected electronic unit not produced or involve the esd event of voltage of characteristic voltage of the circuit board embedded more than ESD in addition.Such esd event is mentioned as " high-level esd event " or " high-level ESD " at this.

Term " characteristic voltage " this be used to mean the circuit board that " triggering " or " causing " ESD embeds at least partially from state-transition non-conductive on electricity to the voltage applied of the state of conducting electricity at electricity.Term " low-level ESD " and " low-level esd event " are used at this esd event meaning the voltage producing or involve in addition the characteristic voltage being less than the circuit board that ESD embeds interchangeably.

The circuit board that ESD embeds such as can have the characteristic voltage of about 70V or larger (all 80V according to appointment, about 90V, about 100V, about 110V, about 120V or even about 240V).As a result, by being shunted by voltage and the electric current be associated being transmitted to ground, the circuit board that ESD embeds can protect the parts being attached to it not suffer high-level esd event, as will be described later.But; because the characteristic voltage of the circuit board that ESD embeds is relatively high; it cannot protect the parts being attached to it not suffer low-level esd event (that is, produce the event of the voltage lower than about 70V, or what characteristic voltage of the circuit board no matter ESD embeds can be).As a result, the parts of such as LED being attached to the circuit board that ESD embeds still easily can be subject to the infringement from low-level esd event.

In order to guard block does not suffer low-level ESD, system and method for the present disclosure can utilize the circuit board being attached to ESD embedding and/or one or more diode be deposited on the circuit board of ESD embedding.Diode described here can be any suitable diode, such as diode with surface mounting, thin film diode (" TFD ") and combination thereof etc.As will be described later, (multiple) diode of the present disclosure can or series coupled in parallel with electronic unit.In either case, (multiple) diode described here can have the electrical characteristics protecting the electronic unit be associated of such as LED not suffer to be exposed to the infringement voltage and current produced by low-level esd event.

Make reference to Figure 1A and Figure 1B now, Figure 1A and Figure 1B describes the non-restrictive example of the array according to module of the present disclosure and module.As shown in figure ia, module 100 comprises the circuit board 102 supporting that the ESD of multiple electronic unit 104 embeds.Single diode 106 also supported by the circuit board 102 that ESD embeds, and single diode 106 is in parallel with multiple electronic unit 104 or be connected in series.As graphic in fig. ib, multiple module 100 can be organized as array 110, such as, as can be found in illuminating device parts.

The circuit board 102 that ESD embeds can be flexible or rigidity, and comprises the dielectric material of one or more voltage switchable, is also mentioned as " dielectric of voltage switchable " or VSD at this.Term " dielectric material of voltage switchable ", " dielectric of voltage switchable ", " material of voltage switchable " and " VSD " are used to mean until the combination that is dielectric or non-conductive any composition or composition of the voltage (so VSD material becomes conduction) that applies to be more than or equal to VSD properties of materials voltage at this interchangeably.In other words, apply be more than or equal to characteristic voltage voltage (such as, as by esd event provide) time, VSD material becomes conduction, but otherwise is non-conductive.Alternatively or cumulatively, VSD material can be understood to non-linear resistance material.

The VSD material of any type can be used in the circuit board of ESD described here embedding.In certain embodiments, VSD material described here comprise anisotropically (heterogeneously) or isotropically (homogenously) be distributed on conduction in adhesive (such as polymer adhesive) and/or semiconductor grain.Such as, VSD material described here can comprise and is distributed on the first particle in adhesive material and the second particle, and wherein, the second particle is different from the first particle.First and second particles can be selected from conduction and/or semiconductor grain.

In certain embodiments, at least one in the first and second particles in VSD material described here is high aspect ratio particle (HAR) particle.HAR particle can be understood to have scope such as, from about 10:1 to about 100:1 or the particle of the aspect ratio of even about 10:1 to about 1000:1 (full-size: minimum dimension, length: diameter or length: cross section).Certainly, have be greater than aforementioned range or the aspect ratio in aforementioned range particle by desired by the disclosure, and can be used.Correspondingly, all or part of of particle of the present disclosure can be the shape of spheroid, platelet, fiber (such as, nanofiber), rod (such as, nanometer rods), pipe (such as, nanotube) and combination etc. thereof.The non-restrictive example of HAR particle comprises single wall or multi-walled carbon nano-tubes, carbon black and carbon fullerene.

To HAR particle alternatively or cumulatively, VSD material described here can comprise can be conduction or the organic and/or inorganic particle of semiconductor.The non-restrictive example of such particle comprises and is formed from or comprise following particle: copper, nickel, gold, silver, cobalt, zinc oxide, tin oxide, indium tin oxide, indium-zinc oxide, bismuth oxide, cerium oxide, antimony zinc oxide, silicon, carborundum, titanium dioxide, boron nitride, aluminium nitride, nickel oxide, zinc oxide, zinc sulphide, bismuth oxide, cerium oxide, iron oxide, metal, and/or the compound selecting autoxidisable substance, metal nitride, metal carbides, metal boride, metal sulfide and combination thereof etc.Ad lib, the particle that VSD material described here comprises can comprise the combination of metallic conduction particle and semiconductor grain, comprise following in one or more: silicon, carborundum, titanium dioxide, boron nitride, aluminium nitride, nickel oxide, zinc oxide, zinc sulphide, bismuth oxide, cerium oxide, iron oxide, metal, and/or the compound selecting autoxidisable substance, metal nitride, metal carbides, metal boride and metal sulfide.

The adhesive of any suitable type can be used in VSD material described here.In certain embodiments, adhesive comprises one or more as follows: silicon polymer, phenolic resins, epoxy, polyurethane, poly-(methyl) acrylic acid, polyamide, polyester, Merlon, polyacrylamide, polyimides, polyethylene, polypropylene, polyphenylene oxide, polysulfones, sol-gel material, pottery and combination thereof etc.

Ad lib, be included in U.S. Patent No. 7,695 according to the operable preferred VSD material of the disclosure, in 644 describe those, the overall content of this United States Patent (USP) is referred to herein.

Now reference is made to Fig. 2, the non-restrictive example of the circuit board that Fig. 2 diagram embeds according to the operable ESD of the disclosure.As shown, the circuit board 200 that ESD embeds comprises ground 202, VSD material layer 204 and the optional second layer 206.Generally speaking, ground 202 is provided to the path on electricity ground.Therefore, such as, ground 202 can comprise or be formed from electric conducting material, such as copper, silver, gold or aluminium etc.In certain embodiments, ground 202 is copper coin, layers of copper or another conductive material layers above or in substrate of substrate (such as fiber reinforced synthetic).

In the graphic embodiment of institute, VSD material 204 is present on ground 202.In order to simple and easy to understand, VSD material 204 is illustrated as the continuous print layer directly contacted with ground 202 in fig. 2.But it will be appreciated that, VSD material 204 can have any configuration wanted.Such as, during VSD material 204 can be deposited on the segregate region on ground 202, on ground 202 pattern and combination etc.Similarly, VSD material 204 does not need directly to contact with ground 202.Such as, VSD material 204 remotely can be located apart from ground 202, but can with ground 202 electrical contact, such as, by one or more wiring, weld pad, contact and combination thereof etc.

Electronic unit (not shown) can be engaged or be applied in addition the circuit board 200 that ESD embeds.In certain embodiments, such parts can directly be joined to VSD material 204.Alternatively or cumulatively, such parts can be engaged to optional second electric conducting material (such as, copper, silver, gold and aluminium etc.) layer 206, and this layer of itself can be engaged, adhere to or other and VSD material 204 electrical contact.

As set forth before, when being applied to the voltage on their characteristic voltage, VSD material described here can be converted to conduction state from non-conductive state.This design is usually illustrated in Fig. 3, and Fig. 3 is the illustrative plot of the basic electrical properties of VSD material described here.Generally speaking, characteristic (triggering) voltage is the voltage levvl becoming conduction at its place VSD material.Before the Vin being applied above characteristic (triggering) voltage, VSD material is non-conductive.Once this VSD material has been converted to such state, the clamp voltage (ClampV) in this curve chart has been exactly the voltage levvl maintained by VSD material required by conduction state.Usually, ClampV is less than characteristic voltage (TriggerV).

In embodiments more of the present disclosure, the VSD material be used in the circuit board of ESD described here embedding is selected to make their characteristic voltage to exceed the operating voltage of the electronic circuit be associated with one or more electronic unit (such as, the electronic unit 104 of Fig. 1).In other words, characteristic voltage can be non-conductive by the normal running period VSD material selecting to make at this circuit, but becomes conduction when substrate is exposed to high-level esd event.

VSD properties of materials voltage described here can broadly change.In certain embodiments, VSD properties of materials voltage described here from being more than or equal to about 28V, be more than or equal to about 40V, be more than or equal to about 50V, be more than or equal to about 60V, be more than or equal to about 70V, be more than or equal to about 80V, be more than or equal to about 120V or be even more than or equal to the scope about 240V.Certainly, such value is only exemplary, and to have on aforementioned value, below or within the VSD material of characteristic voltage predicted by the disclosure.In certain embodiments, characteristic voltage exceedes the reverse bias voltage of the electronic unit by damaging such as LED.

VSD properties of materials voltage described here can also be understood with regard to the voltage of per unit gap and/or material thickness.Therefore, such as, VSD material described here can be presented in and such as be more than or equal to about 15V/mil from being more than or equal to about 14V/mil(, being more than or equal to about 20V/mil or being even more than or equal to about 25V/mil(mil=0.001 inch or 0.0254mm)) the characteristic voltage of scope.Therefore, when across 5mil(0.005 inch) gap (the typical minimum gap width for being coated with the circuit board of 1 ounce of copper) when applying to have the VSD material of the characteristic voltage of 14V/mil, VSD properties of materials voltage will be about 70V.That is, when being applied above the voltage (such as, being caused by esd event) of about +/-70V, VSD will be switched to conduction from non-conductive.

In order to illustrate and easy to understand, the operation of the non-limiting embodiments of the circuit board 102 that the ESD that the circuit board 200 that the ESD described in wherein Fig. 2 embeds is used as Figure 1A by the disclosure now embeds.It should be understood that this description can be applied to (such as, as shown in Fig. 5, Fig. 6, Fig. 8 and Fig. 9 A) of the present disclosure other embodiment equally.

In this exemplary embodiment, voltage Vin can be applied to the circuit board 102,200 of ESD embedding to drive the electronic unit 104 being engaged or being electrically connected in addition it, is LED in this case.Ad lib, the Vin applied in the normal operation period is preferably less than the characteristic voltage (such as, 70V or larger) of VSD material 204 that is that comprise at the circuit board 102,200 of ESD embedding or that form the circuit board 102,200 that ESD embeds.In such example, during the normal running of circuit board 102,200, VSD material 204 remains in non-conductive state.Occur high-level esd event time, Vin(its can be biased forward or backwards) can, more than the characteristic voltage of VSD material 204, cause VSD material 204 to be converted to conduction state from non-conductive.In this conduction state, VSD material 204 can by the voltage that produces during high-level esd event and/or current distributing to ground 202, thus prevent voltage and current from arriving parts 104.In like fashion, the electronic unit 104 on the circuit board that the VSD material 204 in the circuit board 102,200 that embeds of ESD can protect ESD to embed does not suffer the voltage and current carrying out damaging possibly that produces during high-level esd event.

Return Figure 1A and Figure 1B, parts 104 can be the parts being easily subject to the voltage of comfortable transient event (such as high level or low-level ESD) period generation and/or any type of electric current infringement.In certain embodiments, electronic unit is the form of light-emitting diode.In this, even if it is noted that such reverse bias voltage/electric current is relatively little, by modern LED and other electronic unit still can be damaged for reverse bias voltage and the exposure of the electric current be associated.When LED, such as, by for be greater than 0 to be less than or equal to about 70V(be such as greater than 0 to about 60V, be greater than 0 to about 50V, be greater than 0 to about 40V, be greater than 0 to about 30V, be greater than 0 to about 20V, be greater than 0 to about 15V, be greater than 0 to about 14V, be greater than 0 to about 10V, be greater than 0 to about 5V or be even greater than 0 to about 3V) the exposure of reverse bias voltage, electronic unit 104 may be damaged.In certain embodiments, by for from being greater than 0 to about 70V, about 1 to being less than or equal to 70V, about 2 to being less than or equal to 70V, about 3 to being less than or equal to about 70V, about 4 to being less than or equal to about 70V, about 5 to being less than or equal to about 70V or even about 10 to the exposure of reverse bias voltage of scope being less than or equal to about 70V, electronic unit 104(may be damaged such as, LED).In some instances, the voltage (being biased forward or backwards) that may damage parts is mentioned as the first voltage levvl at this.

In many instances, the characteristic voltage of circuit board that ESD embeds can exceed electronic unit 104 and can tolerate and not damaged first voltage levvl (to be biased forward or backwards).As previously noted like that, such as, the circuit board that ESD embeds can comprise the VSD material of the characteristic voltage with about 70V.Like this, the circuit board that ESD embeds can protect the parts being electrically connected to it not suffer high-level esd event (that is, generating the event of the voltage levvl of about 70V or larger), as previously described.But the circuit board that ESD embeds may not alleviate low-level esd event, it produces the voltage levvl being less than this circuit board/VSD properties of materials voltage, but it can still higher than the first voltage levvl.In other words, during low-level esd event, the VSD material in the substrate 102,200 that ESD embeds can remain in non-conductive state, therefore allows the voltage and current (with forward and/or reverse bias) produced during this event to arrive electronic unit 104.

In order to guard block 104 does not suffer low-level esd event, diode 106 is mounted or be attached to the circuit board 102 that ESD embeds in addition, and in parallel with parts 104 or be connected in series.Diode 106 can be any suitable diode, and such as diode with surface mounting or thin film diode (" TFD ") etc., as long as it has suitable electrical characteristics can not suffer low-level esd event by guard block 104 to make it.Such as; in the example that diode 106 and parts 104 are connected in parallel wherein; diode 106 can be following Zener diode; Zener diode has and makes it can not suffer the peak value reversal voltage (that is, maximum reverse bias voltage level) carrying out the voltage damaged possibly that produces during low-level ESD by guard block 104.In the example that diode 106 and parts 104 are connected in series wherein, diode 106 can work the electric current carrying out damaging possibly that prevents from producing during low-level ESD and/or voltage arrives parts 104.

In certain embodiments, diode of the present disclosure can be configured to make them not suffer generation scope at the low-level esd event of following reverse bias voltage by guard block: from being greater than 0 to about 70V, about 1 to being less than or equal to about 70V, about 2 to being less than or equal to about 70V, about 3 to being less than or equal to about 70V, about 4 to being less than or equal to about 70V, about 5 to being less than or equal to about 70V or even about 10 to being less than or equal to about 70V.Such as, diode described here can work to stop (such as, more than the first voltage levvl) reverse bias voltage and the electric current that is associated to the transmission of responsive electronic unit (such as LED), allow forward bias voltage to pass through with the electric current be associated simultaneously.

Again return Figure 1A, module 100 is illustrated as and comprises single diode 106, and this single diode 106 is responsible for the multiple parts 104 of protection and is not suffered low-level esd event.More specifically, in this graphic embodiment, (1) diode 106 is responsible for protection 12 (12) LED 104 and is not suffered low-level esd event.Complete this design in fig. ib, wherein, array 110 comprises multiple module 100, and each module in multiple module 100 comprises the single diode 106 for the protection of multiple LED.

As previously noted like that, diode 106 can be connected in parallel with parts 104.This design is generally illustrated in the diagram, wherein, esd protection circuit 400 comprise with diode 106(such as, Zener diode) the string unit 104(that is connected in parallel in this case, LED).In this example, diode 106 can have following peak value reversal voltage, the characteristic voltage of the circuit board that the ESD that this peak value reversal voltage is less than below embeds, and is less than one or more the first voltage levvl in infringement parts 104 at its place.Such as, if parts 104 by be more than or equal to the reverse bias voltage of 4V damage, then diode 106 can be configured to have the peak value reversal voltage being less than 4V.If (being produced by low-level ESD) voltage exceedes the peak value reversal voltage of diode 106, then diode 106 can clamp the voltage at the lsafety level place for parts 104, and any voltage on its clamp voltage of dissipating.

Although the configuration shown in Figure 1A, Figure 1B and Fig. 4 is effective for some application, the degree of the esd protection provided by diode 106 may reduce along with one or more the distance in parts 104.That is, along with the distance between diode 106 and parts 104 increases, the amount that can be supplied to the esd protection diode 106 of such parts can reduce.In addition, diode 106 may not the low-level esd event that occurred by some region in circuit (such as corresponding parts 104 between) in the diagram place of the parts 104 in protective circuit.

Increase to the quantity that the electronic unit be associated provides the diode of low-level esd protection for solving a mechanism of this problem.In this; the disclosure predicts following esd protection circuit, this esd protection circuit be included in from the scope of about 1:10,1:5,1:2,1:1,2:1,3:1,5:1,10:1,100:1 or even about 1000:1 or larger, the ratio of esd protection diode and the electronic unit be associated.Certainly, such ratio is only exemplary, and according to the disclosure, can use any ratio of esd protection diode and electronic unit.

As the unrestricted explanation of this design, make reference to Fig. 5 and Fig. 6, Fig. 5 and Fig. 6 describes according to another example modules of the present disclosure and array.As shown, the circuit board 102 that the circuit board 102, ESD that module 500 and array 610 comprise ESD embedding embeds supports multiple electronic unit 104 and multiple diode 106.Identical with above about described by the embodiment shown in Figure 1A with B of each general aspects in these parts and function, and for the sake of simplicity, no longer reaffirm here.

As shown in fig. 5, each parts 104 are associated with single diode 106, and single diode 106 protects it from low-level esd event.Therefore, in the graphic embodiment of institute, diode 106 is 1:1 with the ratio of parts 104.In like fashion, by each parts of the diode protection of correspondence, corresponding diode can provide the low-level esd protection of the level of the enhancing about the embodiment shown in Figure 1A and Figure 1B, and wherein, the multiple parts 104 of protection are responsible for by single diode 106.

In order to strengthen low-level esd protection even further, the diode of even larger quantity can be used to protect individual component.This design shown in Figure 6, in figure 6, each substrate 102, multiple parts 104 and the multiple diode 106 comprising ESD and embed of example modules (not being labeled) array 610.Particularly, protect each parts 104 from low-level esd event by 16 diodes 106.Certainly, in Fig. 6, the quantity of graphic diode is only exemplary, and can use any amount of diode.In event in office, the quantity increasing diode can allow designer to place with required as many esd protection point in circuit.Really, this can allow designer to utilize the subregion of one or more protective circuit of diode, thus realizes the esd protection of the level wanted.As can be understood, this can reinforcing member 104 from the protection of low-level esd event.

As previously noted like that, diode of the present disclosure can be connected with one or more electric unit Series.Fig. 7 is the exemplary illustration of this design.As shown, circuit 700 comprises voltage source 708, multiple electric parts (in this case, LED) 104 ', 104 ' ', 104 ' ' ' and multiple diode 106 ', 106 ' ', 106 ' ' '.Each parts and complementary diode are connected in series.In this embodiment, each diode can be configured in the event of low-level esd event, get rid of reverse bias and punctures.That is, each diode can have the peak value reversal voltage (that is, maximum reverse bias voltage level) of the reverse bias voltage being enough to tolerate the characteristic voltage being less than the circuit board that ESD embeds.As a result, the existence of diode can effectively protect the parts be associated do not suffer during low-level esd event for infringement voltage exposure.

By way of example, at an A place, low-level esd event 701 can occur in parts 104 ' and 104 ' ' between.When there is not diode 106 ', low-level esd event 701 can generate the voltage and current that may dissipate around circuit 700 counterclockwise (that is, in the reverse bias direction), makes the infringement of cheek 104 '.But the existence due to diode 106 ' causes the voltage and current produced by low-level esd event 701 to be forced to dissipate with clockwise (that is, forward bias direction), as usually graphic by line B institute.Although these may by parts 104 ', ' and 104 ' ' ' is exposed to by the forward bias voltage that promotes and electric current, and such parts can restrain oneself such condition.When the LED in modern times, this is particularly real, and but modern LED may be responsive to reverse bias voltage have higher patience for forward bias voltage.

Although circuit 700 is depicted as the single complementary diode comprised for each parts by Fig. 7, it should be understood that, this configuration is only exemplary, and can use any amount of diode.Such as, multiple complementary diodes that circuit 700 can be configured to comprise for each parts 104 ', 104 ' ', 104 ' '.Such diode can be positioned at such as parts 104 ' and 104 ' ' between, parts 104 ' ' and 104 ' ' ' between and/or parts 104 ' ' ' and the anode of voltage source 708 between.

As previously noted like that, system and method for the present disclosure can utilize any suitable diode not suffer low-level esd event to protect electronic unit, and electronic unit comprises the diode and thin film diode installed on surface.As can be understood, diode with surface mounting may have some characteristic that possibility limits their use in electrostatic discharge (ESD) protection application.Such as, diode with surface mounting is relatively large dimensionally, and therefore may take significant real estate (real estate) on the surface of printed circuit board (PCB).Electrostatic discharge (ESD) protection application in operable diode with surface mounting quantity therefore may by can be assigned to diode place obtainable space amount limit.Diode with surface mounting also often requires to use pickup and placement technique, and wherein, individual diodes manually or is automatically placed on the region place wanted of circuit board.Although pickup and placement technique are practicable technology for manufacture electronic device, it may be consuming time, particularly when the diode of large quantity is placed in electronic device.In addition, diode with surface mounting and pickup and placement technique may not allow diode to be placed on certain the circuit position place wanted for esd protection.

Therefore, ad lib, diode described here is preferably the form of thin film diode (TFD) being deposited on circuit board that ESD embeds or being attached to the circuit board that ESD embeds in addition.Compared with diode with surface mounting, TFD is relatively little compared to diode with surface mounting, and can easily be deposited with large quantity across wide region.As a result, the quantity that can be included in the TFD in esd protection circuit can in fact be not confined.

The TFD of any type can be used in system and method for the present disclosure, as long as it has the suitable electrical characteristics for being used in esd protection application.Therefore, such as, TFD described here can be configured to have the Zener diode one or more electronic unit of protection not being suffered to reverse breakdown voltage suitable for low-level esd event, as previously described.Alternatively or cumulatively, described TFD can be configured to resist following reverse bias voltage and/or electric current, and infringement TFD is being positioned as the level place carrying out one or more parts protected by this reverse bias voltage and/or electric current.

In certain embodiments, TFD described here comprises at least one deck n-type semiconductor and at least one deck p-type semiconductor material.N-shaped or the p-type semiconductor material of any suitable type can be used.Such as, this N-shaped and p-type semiconductor material can be inorganic material, organic material (such as, semi-conducting polymer) or its combination.In certain embodiments, this N-shaped and p-type semiconductor material are all organic materials, such as, and semiconductor p and N-shaped polymer.As can by the non-restrictive example of n-type semiconductor polymer used, mention poly-[2-methoxyl group-5-(2-ethyl-own oxygen base)-Isosorbide-5-Nitrae-(1-cyano vinyl support (cyanovinylene)) phenylene (" CN-PPV).Polypyrrole (PPy) and poly-(3,4, ethene dioxythiophene) (PEDOT) can be comprised by the non-restrictive example of the p-type semiconductor polymer used.

In any suitable manner TFD described here can be deposited on the circuit board of ESD embedding.Such as, aerosol injection, ald (ALD), space ald (S-ALD), chemical vapor deposition (CVD), metallorganic CVD, pulsed laser deposition (PLD), sputtering can be passed through, directly write (such as, via positive displacement), one or more of TFD be deposited upon on the circuit board that ESD embeds by printing (such as, ink jet printing) and combination etc. thereof.In certain embodiments, thin film diode described here is the organic diode deposited via printing treatment (such as ink jet printing).In other non-limiting embodiments, thin film diode described here is the inorganic diode be deposited via ald.

As will by understood by one of ordinary skill in the art, each in these deposition processes comprises multiple parameter be associated, and the nominal value of multiple parameter be associated can be selected and/or adjust to produce the membrane structure with the attribute that one or more is wanted.As used in this, term " nominal " or " nominally " is used to mean indicate or the theoretic amount that can change from the amount of reality when the amount of mentioning.Such as, the process parameter be associated with pulsed laser deposition comprises temperature, deposition pressure, laser repetition rate, the total quantity of laser pulse and gaseous environment (such as, the N for growing film ₂, H ₂, Ar or forming gas).(multiple) nominal value of one or more selected parameter can depend on the thickness wanted of backing material, membrane structure and/or the surface characteristic (such as, uniform or uneven) wanted of membrane structure.(multiple) nominal value of parameter can be adjusted during deposition processes, with thus change the one or more characteristics of membrane structure.Under any circumstance, foregoing deposition techniques can allow TFD to be deposited directly upon on the substrate of ESD embedding in any position wanted.As a result, circuit designers can be placed and the as many esd protection point needed, thus any or all of parts as intended in protective circuit.

Fig. 8 diagram is according to another non-limiting embodiments of esd protection circuit of the present disclosure.As shown, circuit 800 comprises voltage source 708, the multiple parts 104 being engaged or being adhered in addition the substrate (track) 200 that corresponding ESD embeds and multiple thin film diode (TFD) 106.In this embodiment, parts 104 can be light-emitting diodes, but are not such as restricted to gallium nitride based LED.Certainly, be only exemplary to the use of gallium nitride based LED, and the combination of the LED of any type or LED type can be normally used as parts 104.

Individual component 104 is connected to the weld pad 812 of the circuit board 200 that ESD embeds by wiring 801.Like this, Fig. 8 can be understood to the array of the wire-bonded describing parts 104.As graphic in this embodiment, TFD 106 is formed to make them be adjacent to the weld pad 812 of ESD.Place in like fashion can allow TFD 106 fully guard block 104 do not suffer the reverse bias voltage that produces during low-level esd event, as previously described.In addition, TFD 106 is carried out between corresponding TFD and weld pad, esd event occurring close to placing to get rid of for weld pad 812.

Certainly, system and method for the present disclosure is not restricted to provides esd protection in the application of wire-bonded.Positively, the circuit board embedded with ESD can be used in any application to be suitably combined TFD to provide esd protection.In this, make reference to Fig. 9 A and Fig. 9 B, Fig. 9 A and Fig. 9 B diagram are according to another exemplary esd protection circuit of the present disclosure.Be similar to other embodiment, the circuit 900 in Fig. 9 A comprises the circuit board 200(track of voltage source 708 and multiple ESD embedding).Gap 905 is present between the circuit board/track 200 of corresponding ESD embedding.To each gap carry out bridge joint be parts 104(such as, light-emitting diode).Like this, Fig. 9 A can be understood to diagram " flip-chip " or " being directly attached " configuration.

What go out as illustrated in figure 9 a is such, and each parts 104 are protected by TFD 106 in its anode-side.TFD 106 can be deposited/be positioned at any position on the circuit board 200 of ESD embedding.But ad lib, TFD 106 is preferably placed the corresponding parts close to them.Such as, the distance between TFD 106 and their corresponding parts can from being less than or equal to about 5mm, be less than or equal to about 2.5mm, be less than or equal to about 1mm, be less than or equal to about 500 microns, be less than or equal to scope about 100 microns or less.TFD is placed can reduce the risk of the low-level esd event occurred between TFD and its parts close to its corresponding parts.Under any circumstance, TFD 106 can protect its corresponding parts 104 not suffer in downstream contingent reverse bias voltage (such as, not suffering low-level esd event).

Fig. 9 B is the cross sectional view of an element that intercept along the line A of Fig. 9, circuit 900.As shown in this cross sectional view, the substrate 200 that ESD embeds comprises ground 202 and VSD material 204.Describe character and the function of these parts before about Fig. 2, and no longer repeat at this for the sake of simplicity.TFD 106 comprises conductive layer 907, n-type semiconductor layer 909(" n-layer 909 ") and p-type semiconductor layer 911(" p-type layer 911 ").Conductive layer 907 can be formed from any electric conducting material, such as, and copper, aluminium, gold, silver and combination thereof etc.N-type layer 909 and p-type layer 911 can be formed from any n-type semiconductor and p-type semiconductor material, as previously described.In certain embodiments, n-layer 909 is formed autohemagglutination [2-methoxyl group-5-(2-ethyl-own oxygen base)-1,4-(1-cyano vinyl support (cyanovinylene)) phenylene (" CN-PPV); and p-type layer 911 is formed from polypyrrole (PPy) and poly-(3; 4, ethene dioxythiophene) (PEDOT).

As can be understood, can form conductive layer 907 via any deposition processes suitable for deposits conductive material, but deposition processes is not such as restricted to sputtering, chemical vapour deposition (CVD), physical vapour deposition (PVD), ald and combination thereof etc.Similarly, any suitable deposition technique can be used to form n-layer 909 and p-type layer 911.Such as, if n-layer 909 and p-type layer 911 are organic materials of all polymer as previously described, printing technology (such as, ink jet printing, injection etc.), chemical vapour deposition (CVD), physical layer deposition and combination thereof etc. then can be used they to be deposited on the substrate of ESD embedding.

Another aspect of the present disclosure relates to the method one or more electric parts of such as LED being provided to electrostatic discharge (ESD) protection.In this, make reference to Figure 10, Figure 10 is the frame flow chart of diagram according to illustrative methods of the present disclosure.As shown, method 1000 starts at frame 1001 place to provide the substrate of the esd protection with embedding (that is, the circuit board of ESD embedding).As previously noted like that, the circuit board that ESD embeds can be the form of flexibility or rigidity circuit board, such as, as graphic in Fig. 2.Ad lib, the circuit board that ESD embeds is preferably flexible, because the use of flexible PCB has opened approach to such as reel to the high power capacity treatment technology of reel manufacture.

Once provided with the circuit board that ESD embeds, the method just may proceed to optional frame 1002, and wherein, one or more electric parts (such as, LED) can be positioned at the position wanted on substrate.Alternatively, can skip optional frame 1002, and the method can directly proceed to frame 1003, wherein, thin film diode is deposited over the position wanted on the circuit board of ESD embedding.Such as, thin film diode can be deposited over ESD embed circuit board on make they with or with one or more Components Parallel Connection or will be connected in series.Ad lib, TFD diode is preferably deposited over the nearby components of their correspondence, thus these parts is provided to the low-level esd protection of the level wanted, as previously described.

Once deposit (multiple) TFD diode, the method just can be advanced further.In the event skipping optional frame 1002, the method may proceed to frame 1002 ', so the electric parts of such as LED are placed on the position wanted on the circuit board of ESD embedding.Performing optional frame 1002 and in the event of placing component, can frame 1002 ' skipped.Under any circumstance, the method terminates at frame 1004 place.

As previously noted like that, TFD can be deposited on the circuit board that flexible ESD embeds, and opens approach to such as reel to the high power capacity manufacturing technology of reel process.In this, reference is made to Figure 11, Figure 11 illustratively diagram according to of the present disclosure for LED module processing reel to reel manufacturing system 1100.As shown, system 1100 comprises discharging tep reel or reel 1102 and strains tep reel or reel 1104.In operation, reel 1102 can be fed to out circuit board 1108 that flexible ESD embeds for the treatment of.More specifically, the circuit board that flexible ESD embeds can launch from reel 1102 and be passed with continuous print feed motion under precipitation equipment 1106, and is wound onto subsequently on reel 1104.Precipitation equipment 1106 can be configured to by LED, TFD diode and alternatively other parts deposit on the circuit board 1108 that flexible ESD embeds.The circuit board 1108 that ESD flexible after a while embeds can be divided into each section (such as, along boundary line 1110), at boundary line place, each section is made the module of device, such as, the lighting module of parts comprising the array of LED, TFD diode and be associated.

Although being described herein principle of the present invention, it will be understood by those skilled in the art that, this description is made by means of only the mode of example and not as the restriction to scope of the present invention.Except exemplary embodiment shown and described herein, other embodiment is also expected within the scope of the invention.The amendment undertaken by those of ordinary skill in the art and replacement considered to be in scope of the present invention, and except being limited the scope of the invention by following claim, scope of the present invention is not limited.

Claims

1., to the method that electric parts provide Electrostatic Discharge to protect, comprising:

At least one electric parts is electrically connected to the circuit board that ESD embeds, at least one electric parts described are easily subject to the infringement from the exposure for the reverse biased current more than the first voltage levvl; And

At least one thin film diode is electrically connected at least one electric parts described;

Wherein:

The circuit board that described ESD embeds has following characteristic voltage, on described characteristic voltage, described circuit board at least partially from state-transition non-conductive on electricity to the state of conducting electricity at electricity, described characteristic voltage is on described first voltage levvl; And

At least one thin film diode described has the peak value reversal voltage being enough to tolerate the reverse bias voltage being less than described characteristic voltage.

2. method according to claim 1, wherein, described characteristic voltage is more than or equal to about 70V.

3. method according to claim 1, wherein, described first voltage levvl is from the scope being greater than 0 to about 70V.

4. method according to claim 1, wherein, at least one diode described comprises the multiple diodes be electrically connected with at least one unit Series described.

5. method according to claim 1, wherein, the circuit board that described ESD embeds comprises ground and is electrically connected to the dielectric material of voltage switchable on described ground, wherein, on described characteristic voltage, the dielectric material of described voltage switchable is from state-transition non-conductive on electricity to the state of conducting electricity at electricity.

6. method according to claim 1, wherein, at least one electric parts described comprise light-emitting diode.

7. method according to claim 1, wherein, described thin film diode comprises at least one deck p-type semiconductor material and at least one deck n-type semiconductor.

8. comprise a device for Electrostatic Discharge protection, comprising:

The circuit board that ESD embeds;

Be electrically coupled at least one the electric parts of the circuit board that described ESD embeds, at least one electric parts described are easily subject to the infringement from the exposure for the reverse biased current more than the first voltage levvl; And

At least one thin film diode, is electrically coupled at least one electric parts described;

Wherein:

The circuit board that described ESD embeds has characteristic voltage, on described characteristic voltage, described circuit board at least partially from state-transition non-conductive on electricity to the state of conducting electricity at electricity, described characteristic voltage is on described first voltage levvl; And

9. device according to claim 8, wherein, described characteristic voltage is more than or equal to about 70V.

10. device according to claim 8, wherein, described first voltage levvl is from the scope being greater than 0 to about 70V.

11. devices according to claim 8, wherein, at least one thin film diode described comprises the multiple diodes be electrically connected with at least one unit Series described.

12. devices according to claim 8, wherein, the circuit board that described ESD embeds comprises ground and is electrically connected to the dielectric material of voltage switchable on described ground, wherein, on described characteristic voltage, the dielectric material of described voltage switchable is from state-transition non-conductive on electricity to the state of conducting electricity at electricity.

13. devices according to claim 8, wherein, at least one electric parts described comprise light-emitting diode.

14. devices according to claim 8, wherein, described thin film diode comprises at least one deck p-type semiconductor material and at least one deck n-type semiconductor.

15. 1 kinds of methods providing Electrostatic Discharge to protect to LED illumination module, comprising:

Be deposited on by one or more light-emitting diode (LED) on the circuit board of ESD embedding, one or more LED described is easily subject to the infringement from the exposure for the reverse bias voltage on the first voltage levvl; And

One or more thin film diode is deposited on circuit board that described ESD embeds, is electrically coupled at least one thin film diode to make in one or more LED described each;

Wherein:

One or more thin film diode described has the peak value reversal voltage being enough to tolerate the reverse bias voltage being less than described characteristic voltage.

16. methods according to claim 15, wherein, described multiple thin film diode is deposited: aerosol injection, ald ALD, space ald S-ALD, chemical vapour deposition (CVD) CVD, metallorganic CVD, pulsed laser deposition PLD, sputtering, directly write (such as by least one in following, via positive displacement), printing (such as, ink jet printing) and combination.

17. methods according to claim 15, wherein, described characteristic voltage is more than or equal to about 70V.

18. methods according to claim 15, wherein, described first voltage levvl is from the scope being greater than 0 to about 70V.

19. methods according to claim 15, wherein, each and at least one the thin film diode coupled in series electrical in one or more LED described.

20. methods according to claim 19, wherein, the circuit board that described ESD embeds is flexible PCB, described flexible PCB comprises ground and is electrically connected to the dielectric material of voltage switchable on described ground, wherein, on described characteristic voltage, the dielectric material of described voltage switchable is from state-transition non-conductive on electricity to the state of conducting electricity at electricity.

21. methods according to claim 19, wherein, each thin film diode comprises at least one deck p-type semiconductor material and at least one deck n-type semiconductor.