CN104883175A - Output circuit suitable for integrated circuit and related control method - Google Patents
Output circuit suitable for integrated circuit and related control method Download PDFInfo
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- CN104883175A CN104883175A CN201410068694.2A CN201410068694A CN104883175A CN 104883175 A CN104883175 A CN 104883175A CN 201410068694 A CN201410068694 A CN 201410068694A CN 104883175 A CN104883175 A CN 104883175A
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Abstract
The invention provides an output circuit suitable for an integrated circuit. The output circuit comprises a driver, a pre-driver and a buffer circuit. The driver is electrically connected to two output ends outside the integrated circuit for outputting signals. The pre-driver is used for controlling the driver and comprises a load and an input transistor which are serially connected. A contact arranged between the load and the input transistor is used for controlling the driver. The buffer circuit controls the load and the input transistor according to one internal signal. Before controlling the input transistor to be off, the buffer circuit first makes the impedance of the load lowered so as to change the voltage of the contact.
Description
Technical field
System of the present invention, about the output circuit of integrated circuit, especially can stablize the output circuit of output common mode signal and relevant control method.
Background technology
Communication between electronic product, can reach through the transmission line of entity and special communication specification.Many communication specifications have employed differential wave and carry out communication, and it can reach quite high signaling rate.For high speed communication, transmission line often needs collocation to have terminal resistance, is used for reducing signal reflex, to increase transmission speed.For example, terminal resistance (terminator) can be located in a receiving terminal integrated circuit, is connected between a joint sheet and a power line.
Circuit framework in general integrated circuit, according to function, roughly can be divided into two classes: core circuit (corecircuit) and output/input circuit (input and output circuit).Core circuit is responsible for signal transacting in integrated circuit or conversion, and output/input circuit is then window as communication between integrated circuit and extraneous electronic building brick or bridge.Evolution along with manufacture of semiconductor and the demand for arithmetic speed, the core power supply voltage that core circuit adopts is often more and more lower.But output/input circuit must have enough actuating forces and the requirement with extraneous electronic building brick coupling, so the import and export supply voltage that output/input circuit adopts is often many higher than core power supply voltage.For example, import and export supply voltage may maintain 3.3V, and core power supply voltage is then low to 0.9V.And when core power supply voltage so low to 0.9V time, just there occurs problem unknown in many prior arts, need go to overcome or solve.
Summary of the invention
Embodiment provides a kind of output circuit being applicable to an integrated circuit.This output circuit includes a driver, a Das Vorderradfahrwerkmit Vorderradantrieb and a buffer circuit.This actuator electrical is connected to two outputs outside this integrated circuit to carry out signal output.This Das Vorderradfahrwerkmit Vorderradantrieb, in order to control this driver, comprises a load and an input transistors of serial connection.There is a contact in order to control this driver between this load and this input transistors.This buffer circuit controls this load and this input transistors according to an internal signal.This buffer circuit, before this input transistors of control is closed, first reduces an impedance of this load to change the voltage of this contact.
Embodiment separately provides a kind of control method being applicable to an output circuit of an integrated circuit.This output circuit includes a Das Vorderradfahrwerkmit Vorderradantrieb and a driver of signal crossfire.This driver is in order to be electrically connected to two outputs outside this integrated circuit to carry out signal output.This Das Vorderradfahrwerkmit Vorderradantrieb includes a load and an input transistors of serial connection.There is between this load and this input transistors a contact and be electrically connected to this driver.This control method includes: according to an internal signal, reduce an impedance of this load; And, after this impedance reducing this load, according to this internal signal, control this input transistors and close.
Embodiment separately provides a kind of control method being applicable to an output circuit of an integrated circuit.This output circuit includes a driver and a Das Vorderradfahrwerkmit Vorderradantrieb.This driver is in order to be electrically connected to two outputs outside this integrated circuit to carry out signal output.This Das Vorderradfahrwerkmit Vorderradantrieb has a non-return output and one and oppositely exports.This control method includes: according to an internal signal, makes this voltage oppositely exported start close to after a power line voltage, make a voltage of this non-return output from this power line voltage start away from; And, according to this voltage and this this driver of this voltage control oppositely exported of this non-return output.This this voltage oppositely exported starts the time point close to this power line voltage, early than this non-return output this voltage from this power line voltage start away from a time point.
Embodiment
Fig. 1 shows output circuit 100 in a transmitting terminal integrated circuit through transmission line 106N and 106P, is electrically connected to a receiving terminal integrated circuit 180.Output circuit 100 has buffer circuit 108, Das Vorderradfahrwerkmit Vorderradantrieb (pre-driver) 102 and current mode driver (current-mode driver) 104.Current mode driver 104 is through transmission line 106N and the 106P outside transmitting terminal integrated circuit, be electrically connected to two terminal resistance Rdln and Rdlp in receiving terminal integrated circuit 180, and terminal resistance Rdln and Rdlp is electrically connected to the import and export power line VIO-RX in receiving terminal integrated circuit 180, it is 3.3V.
Buffer circuit 108 is according to the internal signal V on inside end S-internal
s-internal, at the non-return signal V that non-return end S-non is roughly contrary with backward end S-inv producing logical value
s-nonwith reverse signal V
s-inv.At this specification, be not used in restriction example of the present invention, logical one represents an opposing high voltage potentials, and the logical zero contrary with logical one represents a relative low voltage.
Das Vorderradfahrwerkmit Vorderradantrieb 102 has two nmos pass transistor Nnpr and Nipr, two load resistance Rpln and Rplp and current source It-pr.Nmos pass transistor Nnpr, load resistance Rpln and current source It-pr are serially connected with between core power line Vcore (0.9V) and earth connection (0V).Similar, nmos pass transistor Nipr, load resistance Rplp and current source It-pr are serially connected with between core power line Vcore and earth connection.Tie point ND-between nmos pass transistor Nnpr and load resistance Rpln, is electrically connected the nmos pass transistor Nndr controlled in current mode driver 104; Tie point ND+ between nmos pass transistor Nipr and load resistance Rplp, is electrically connected the nmos pass transistor Nidr controlled in current mode driver 104.Briefly, nmos pass transistor Nnpr and Nipr can the electric current I of switchable current source It-pr
t-prflow through load resistance Rpln or Rplp, determine the signal V on tie point ND-and ND+ by this
nD-with V
nD+.So, non-return signal V
s-nonwith reverse signal V
s-invtwo current switching signals can be considered as.Tie point ND-and ND+ can be considered as the reverse output of Das Vorderradfahrwerkmit Vorderradantrieb 102 and non-return output respectively.
Nmos pass transistor Nndr and Nidr in current mode driver 104, is together electrically connected to current source It-dr.Similar, nmos pass transistor Nndr and Nidr can the electric current I of switchable current source It-dr
t-drflow through terminal resistance Rdln or Rdlp, determine the output signal V on output NO-and NO+ by this
nO-with V
nO+.
Fig. 2 shows some signal waveforms in Fig. 1.Along with non-return signal V
s-nonwith reverse signal V
s-invchange its magnitude of voltage at time point t1, namely change its logical value, the signal V in Das Vorderradfahrwerkmit Vorderradantrieb 102
nD-with V
nD+start to change its magnitude of voltage.Such change is until time point t4 just completes.In period between time point t2 to t3, signal V
nD-with V
nD+hand over more.In fig. 2, signal V
nD-with V
nD+hand over more in crossover voltage V
nD-CROSS.In order to have enough signal swings (signal swing), signal V
nD-with V
nD+minimum voltage value V
nD-MINcan be on the low side as much as possible.Expected, lower minimum voltage value V
nD-MIN, lower crossover voltage V
nD-CROSS.
Note that the current source It-dr in current mode driver 104 needs enough cross-pressure V
dROP, maintain electric current I
t-drfor desired definite value.But, as shown in Figure 2, in the period between time point t2 to t3, because signal V
nD-with V
nD+simultaneously on the low side, so cross-pressure V
dROPdeficiency, causes electric current I
t-drdiminishing unfortunately, is no longer a default definite value.
Unstable electric current I
t-dr, can exacerbate electromagnetic wave interference (electromagnetic interference, EMI).In fig. 2, output common mode signal V
cMrepresent output signal V
nO-with V
nO+mean value.When the resistance value of terminal resistance Rdln and Rdlp is all R
lOADfixed value time, the output common mode signal V in Fig. 1
cMthe large appointment of voltage be (3.3 – 0.5*I
t-dr* R
lOAD) volt.Work as electric current I
t-drduring for certain value, output common mode signal V can be extrapolated
cMapproximately also can be one determines voltage.But, work as electric current I
t-drdiminish, output common mode signal V
cMwill increase, as shown in Figure 2.And the output common mode signal V of instability
cM, larger Electromagnetic Interference can be produced.In other words, signal V
nD-with V
nD+simultaneously on the low side, namely crossover voltage V
nD-CROSSon the low side, bad Electromagnetic Interference may be caused.
Fig. 3 shows the output circuit 200 implemented according to the present invention.In one embodiment, output circuit 200 replaces the output circuit 100 in Fig. 1.Although Fig. 3 does not show, in an embodiment, output circuit 200 through transmission line 106N and the 106P in Fig. 1, can be electrically connected to receiving terminal integrated circuit 180.In order to the convenience that solution is said, there are many symbols the same with the symbol in Fig. 1 in Fig. 3, the assembly representated by it, material or material, for functionally the same or similar, so may no longer repeat.But the present invention is not limited thereto, the assembly of same-sign, in different embodiments, may implement with different circuit, material or framework.
In figure 3, buffer circuit 208 provides signal to Das Vorderradfahrwerkmit Vorderradantrieb 202, and Das Vorderradfahrwerkmit Vorderradantrieb 202 provides signal to current mode driver 104.So buffer circuit 208, Das Vorderradfahrwerkmit Vorderradantrieb 202 and current mode driver 104 form signal crossfire (cascode) framework.
The PMOS transistor Ppln and Pplp compared to the Das Vorderradfahrwerkmit Vorderradantrieb more than 202 in the Das Vorderradfahrwerkmit Vorderradantrieb 102, Fig. 3 in Fig. 1.PMOS transistor Ppln in parallel and load resistance Rpln constitutes a load Ln; PMOS transistor Pplp in parallel and load resistance Rplp constitutes another load Lp.PMOS transistor Ppln and Pplp has control end S-CHG+ and S-CHG-respectively, and it has load control signal V respectively
s-CHG+and V
s-CHG-.
Control end S-CHG+ and S-CHG-is electrically connected to extraly compared to the buffer circuit 208 in the buffer circuit 108, Fig. 3 in Fig. 1.Connect from the circuit of buffer circuit 208, load control signal V
s-CHG+with V
s-CHG-, be all the internal signal V on inside end S-internal
s-internaldelayedly to produce, just load control signal V
s-CHG+with V
s-CHG-logical value contrary.In other words, as load control signal V
s-CHG+when being positioned at a high voltage of logical one, load control signal V
s-CHG-a low-voltage of logical zero will be positioned at.Similar, non-return signal V
s-nonwith reverse signal V
s-invload control signal V respectively
s-CHG-with V
s-CHG+delayedly to produce, therefore non-return signal V
s-nonwith reverse signal V
s-invlogical value contrary.
Fig. 4 shows some signal waveforms in Fig. 3 and sequential relationship.In the diagram, internal signal V
s-internalto load control signal V
s-CHG+with V
s-CHG-between signal delay time, be approximately all Td
1; Load control signal V
s-CHG-or V
s-CHG+to non-return signal V
s-nonor reverse signal V
s-invbetween signal delay time, be approximately all Td
2.Can know by inference, internal signal V
s-internalto non-return signal V
s-nonor reverse signal V
s-invbetween signal delay time, large appointment is Td
1+ Td
2.
Before time point t0, non-return signal V
s-nonwith reverse signal V
s-invlay respectively at a low-voltage (logical zero) and a high voltage (logical one), so most electric current I
t-prcapital flows through nmos pass transistor Nipr, therefore signal V
nD+in a low-voltage, and signal V
nD-at a high voltage, as shown in Figure 4.
As shown in Figure 4, in time point t0, internal signal V
s-internalfrom a low-voltage (logical zero), become a high voltage (logical one).
Through Td signal delay time
1after time point t01, load control signal V
s-CHG+with V
s-CHG-start change.Load control signal V
s-CHG+voltage become large, the channel impedance of PMOS transistor Ppln increases, so the impedance of load Ln increases.Contrary, load control signal V
s-CHG-voltage diminish, so load Lp impedance reduce.At time point t01, because natively almost do not have electric current to flow through nmos pass transistor Nnpr and load Ln, therefore, the impedance increase of load Ln can't have influence on signal V
nD-, it still maintains a high voltage, for example the 0.9V of core power line Vcore.At time point t01, because nearly all electric current I
t-prall flow through load Lp, so the impedance of load Lp reduces will draw high signal V
nD+voltage, make it start to approach toward 0.9V, as shown in Figure 4.
Again through Td signal delay time
2after time point t1, non-return signal V
s-nonwith reverse signal V
s-invstart change.Now, the impedance of nmos pass transistor Nnpr reduces, and the impedance of nmos pass transistor Nipr increases.Electric current I
t-prstarting from flowing through load Lp, being switched to and flowing through load Ln.Therefore, signal V
nD-decline from 0.9V, signal V
nD+maintain ascendant trend or maintain 0.9V.
Load control signal V
s-CHG-with V
s-CHG+be equal to two feed-forward signals (feed-forward signal), the time point t01 before the impedance of nmos pass transistor Nnpr and Nipr changes, just changes the impedance of load Lp and Ln in advance.As shown in Figure 4, the result of feedforward like this, make signal ND+ just start to rise at time point t01, and signal ND-just starts to decline at time point t1.
Some dotted lines in Fig. 4, replicate the signal V in Fig. 2
nD+, electric current I
t-dr, and output common mode signal V
cM, using as comparing.In the embodiment of Fig. 3 and Fig. 4, because signal V
nD+just start to rise at time point t01, so signal V
nD+with V
nD-crossover voltage V
nD-CROSS-NEW, will compared with the crossover voltage V in Fig. 2
nD-CROSSthe height come.As long as design is suitable, higher crossover voltage V
nD-CROSS-NEWcan ensure that the current source It-dr in Fig. 3 has enough cross-pressure V
dROP, maintain electric current I
t-drand output common mode signal V
cMfor fixed value, as shown in Figure 4.In other words, the embodiment of Fig. 3, can improve in Fig. 1, because output common mode signal V
cMthe unstable Electromagnetic Interference problem caused.
Also can know by inference, as internal signal V from the explanation of Fig. 3 and Fig. 4
s-internalfrom a high voltage of logical one, when becoming a low-voltage of logical zero, signal V
nD-start the time point risen, can early than signal V
nD+start the time point declined, so a higher crossover voltage can be obtained.Equally can stabling current I
t-drand output common mode signal V
cM.
In figure 3, non-return signal V
s-nonpostpone load control signal V
s-CHG-produce, but the present invention is not limited to this.Fig. 5 shows another buffer circuit 208a, in certain embodiments, can replace buffer circuit 208.In Figure 5, non-return signal V
s-nonpostpone load control signal V
s-CHG+produce, and reverse signal V
s-invpostpone load control signal V
s-CHG-produce.
Fig. 6 shows another Das Vorderradfahrwerkmit Vorderradantrieb 202a, in certain embodiments, and can in order to replace the Das Vorderradfahrwerkmit Vorderradantrieb 202 in Fig. 3.Change the impedance of load Lna and Lpa with nmos pass transistor Npln and Nplp compared to the Das Vorderradfahrwerkmit Vorderradantrieb 202a in the Das Vorderradfahrwerkmit Vorderradantrieb 202, Fig. 6 in Fig. 3.Fig. 4 also can be used for some signal waveforms in key diagram 6.Das Vorderradfahrwerkmit Vorderradantrieb 202a in Fig. 6, can improve Electromagnetic Interference problem.
The output circuit of previously having illustrated is all using nmos pass transistor as current changeover switch, and for example, nmos pass transistor Nnpr and the Nipr in Fig. 1 is exactly two current changeover switch.But the present invention is not limited to this.Fig. 7 shows according to the output circuit 400 in another embodiment of the present invention, wherein uses many PMOS transistor as current changeover switch.Operating principle and the effect improving electromagnetic interference of Fig. 7, can learn with reference to previous explanation, therefore be not repeated.Certainly, in certain embodiments, be used in Fig. 7 changing the nmos pass transistor of load impedance, also can change and adopt PMOS transistor to implement.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Accompanying drawing explanation
Fig. 1 shows a transmitting terminal integrated circuit and a receiving terminal integrated circuit.
Fig. 2 shows some signal waveforms of transmitting terminal integrated circuit in Fig. 1.
Fig. 3 shows the output circuit according to one embodiment of the invention.
Fig. 4 shows some signal waveforms in Fig. 3 and sequential relationship.
Fig. 5 shows another embodiment of buffer circuit in Fig. 3.
Fig. 6 shows another embodiment of Das Vorderradfahrwerkmit Vorderradantrieb in Fig. 3.
Fig. 7 shows according to the output circuit in another embodiment of the present invention.
Claims (20)
1. be applicable to an output circuit for integrated circuit, include:
Driver, is electrically connected to two outputs outside this integrated circuit to carry out signal output;
Das Vorderradfahrwerkmit Vorderradantrieb, in order to control this driver, comprises load and the input transistors of serial connection, wherein, has contact in order to control this driver between this load and this input transistors; And
Buffer circuit, controls this load and this input transistors according to internal signal, and wherein, this buffer circuit, before this input transistors of control is closed, first reduces the impedance of this load to change the voltage of this contact.
2. output circuit as claimed in claim 1, it is characterized in that, this buffer circuit, is used for controlling this load and this input transistors to produce load control signal and switching signal for internal signal delay first time of delay and the second time of delay respectively.
3. output circuit as claimed in claim 2, it is characterized in that, this input transistors is the first input transistors, this Das Vorderradfahrwerkmit Vorderradantrieb separately has the second input transistors, this first and second input transistors is controlled by reverse signal and non-return signal respectively, one of them of this reverse signal and this non-return signal postpones this load control signal produced.
4. output circuit as claimed in claim 2, is characterized in that, this load includes load transistor in parallel and resistance, and this load control signal is in order to control this load transistor.
5. output circuit as claimed in claim 4, it is characterized in that, this input transistors is nmos pass transistor, and this load transistor is PMOS transistor.
6. output circuit as claimed in claim 1, is characterized in that, this buffer circuit, before this input transistors of control is opened, first increases the impedance of this load.
7. output circuit as claimed in claim 1, it is characterized in that, this Das Vorderradfahrwerkmit Vorderradantrieb separately includes current source, and this load and this input transistors are sequentially serially connected with between this power line and this current source.
8. output circuit as claimed in claim 7, it is characterized in that, this current source is the first current source, this driver is current mode driver, its separately include transistor to and the second current source, this second current source is serially connected with between this transistor pair and another power line, and this transistor is to being electrically connected to this two output.
9. output circuit as claimed in claim 1, it is characterized in that, this load and this input transistors are respectively the first load and the first input transistors, this Das Vorderradfahrwerkmit Vorderradantrieb separately has the second load and second input transistors of serial connection, this buffer circuit controls this second input transistors when controlling this first input transistors and cutting out and opens, and this buffer circuit increases the impedance of this second load when reducing this impedance of this first load.
10. one kind is applicable to the control method of the output circuit of integrated circuit, this output circuit includes Das Vorderradfahrwerkmit Vorderradantrieb and the driver of signal crossfire, this driver is in order to be electrically connected to two outputs outside this integrated circuit to carry out signal output, this Das Vorderradfahrwerkmit Vorderradantrieb includes load and the input transistors of serial connection, wherein, have contact between this load and this input transistors and be electrically connected to this driver, this control method includes:
According to internal signal, reduce the impedance of this load; And
After this impedance reducing this load, according to this internal signal, control this input transistors and close.
11. control methods as claimed in claim 10, it is characterized in that, this load is the first load, and this input transistors is the first input transistors, and this Das Vorderradfahrwerkmit Vorderradantrieb separately includes the second load and second input transistors of serial connection, and this control method separately includes:
According to this internal signal, increase the impedance of this second load; And
After this impedance increasing this second load, according to this internal signal, control this second input transistors and open.
12. control methods as claimed in claim 10, is characterized in that, separately include:
Postpone this internal signal to produce load control signal, in order to reduce this impedance of this load; And
Postpone this internal signal to produce switching signal, close in order to control this input transistors.
13. control methods as claimed in claim 12, is characterized in that, this load includes load transistor in parallel and resistance, and this load and this input transistors are series between power line and current source, and this control method separately includes:
This load transistor is controlled with this load control signal; And
This input transistors is controlled with this switching signal.
14. 1 kinds of control methods being applicable to the output circuit of integrated circuit, this output circuit includes driver and Das Vorderradfahrwerkmit Vorderradantrieb, this driver is in order to be electrically connected to two outputs outside this integrated circuit to carry out signal output, this Das Vorderradfahrwerkmit Vorderradantrieb has non-return output and oppositely exports, and this control method includes:
According to internal signal, make this voltage oppositely exported start close to after power line voltage, make the voltage of this non-return output from this power line voltage start away from; And
According to this voltage and this this driver of this voltage control oppositely exported of this non-return output;
Wherein, this this voltage oppositely exported starts the time point close to this power line voltage, early than this non-return output this voltage from this power line voltage start away from time point.
15. control methods as claimed in claim 14, it is characterized in that, this Das Vorderradfahrwerkmit Vorderradantrieb includes first and second input transistors, and current source, this first input transistors is electrically connected on this and oppositely exports between this current source, this second input transistors is electrically connected between this non-return output and this current source, and this control method separately includes:
Electrical connection first is carried between this non-return output and power line;
Electrical connection second is carried on this and oppositely exports between this power line;
Reduce the impedance of this first load and increase the impedance of this second load; And
Control this first input transistors close and control the unlatching of this second input transistors;
Wherein, control this first input transistors and close and control the time point of this second input transistors unlatching, be later than the time point of this impedance starting to reduce this first load and this impedance increasing this second load.
16. control methods as claimed in claim 15, is characterized in that, separately include:
Postpone this internal signal, to produce the first and second load control signal, in order to control this first and second load respectively; And
Postpone this internal signal, to produce first and second current switching signal, in order to control this first and second input transistors respectively.
17. control methods as claimed in claim 15, it is characterized in that, this current source is the first current source, this driver is current mode driver, this driver separately include transistor to and the second current source, this second current source is serially connected with between this transistor pair and power line, and this transistor is to being electrically connected to this two output.
18. control methods as claimed in claim 17, is characterized in that, this oppositely exports and this non-return output controls the right one of this transistor respectively.
19. 1 kinds of output circuits being applicable to integrated circuit, include:
Driver, is electrically connected to two outputs outside this integrated circuit to carry out signal output; And
Das Vorderradfahrwerkmit Vorderradantrieb, includes:
Input transistors, controls signal according to first and controls its closedown; And
Load, controls signal according to second and reduces impedance, wherein
Have contact between this input transistors and this load in order to control this driver, and this input transistors is before closing according to this first control signal, this load first reduces impedance to change the voltage of this contact according to this second control signal.
20. output circuits as claimed in claim 19, is characterized in that, more comprise:
Buffer circuit, produces this first control signal and this second control signal according to internal signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410068694.2A CN104883175B (en) | 2014-02-27 | 2014-02-27 | Output circuit and relevant control method suitable for integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410068694.2A CN104883175B (en) | 2014-02-27 | 2014-02-27 | Output circuit and relevant control method suitable for integrated circuit |
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| CN104883175A true CN104883175A (en) | 2015-09-02 |
| CN104883175B CN104883175B (en) | 2018-06-19 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057702A1 (en) * | 2005-09-13 | 2007-03-15 | Nec Electronics Corporation | Output buffer circuit |
| CN101510772A (en) * | 2009-03-19 | 2009-08-19 | 智原科技股份有限公司 | Output/input circuit with small area |
| US20090267818A1 (en) * | 2008-04-24 | 2009-10-29 | William George John Schofield | Low distortion current switch |
| CN102487278A (en) * | 2010-12-01 | 2012-06-06 | 晨星软件研发(深圳)有限公司 | Low-leakage output/input circuit and related device |
| CN103383416A (en) * | 2012-05-04 | 2013-11-06 | 南亚科技股份有限公司 | System and method for testing off-chip driver impedance |
-
2014
- 2014-02-27 CN CN201410068694.2A patent/CN104883175B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057702A1 (en) * | 2005-09-13 | 2007-03-15 | Nec Electronics Corporation | Output buffer circuit |
| US20090267818A1 (en) * | 2008-04-24 | 2009-10-29 | William George John Schofield | Low distortion current switch |
| CN101510772A (en) * | 2009-03-19 | 2009-08-19 | 智原科技股份有限公司 | Output/input circuit with small area |
| CN102487278A (en) * | 2010-12-01 | 2012-06-06 | 晨星软件研发(深圳)有限公司 | Low-leakage output/input circuit and related device |
| CN103383416A (en) * | 2012-05-04 | 2013-11-06 | 南亚科技股份有限公司 | System and method for testing off-chip driver impedance |
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| Publication number | Publication date |
|---|---|
| CN104883175B (en) | 2018-06-19 |
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