CN104883175A - Output circuit suitable for integrated circuit and related control method - Google Patents

Abstract

The present embodiment provides an output circuit suitable for an integrated circuit. The output circuit includes a driver, a pre-driver, and a buffer circuit. The driver is electrically connected to two output terminals outside the integrated circuit for outputting signals. The front driver is used for controlling the driver and comprises a load and an input transistor which are connected in series. A contact is provided between the load and the input transistor for controlling the driver. The buffer circuit controls the load and the input transistor according to an internal signal. Before controlling the input transistor to be closed, the buffer circuit reduces an impedance of the load to change the voltage of the contact.

Description

Output circuit suitable for integrated circuit and related control method

technical field

The invention relates to an output circuit of an integrated circuit, especially an output circuit capable of stably outputting a common-mode signal and a related control method.

Background technique

Communication between electronic products can be achieved through physical transmission lines and special communication specifications. Many communication standards use differential signaling for communication, which can achieve a relatively high signal transmission speed. For high-speed communication, transmission lines often need to be equipped with terminal resistors to reduce signal reflection and increase transmission speed. For example, a terminator can be provided in a receiving IC, connected between a bonding pad and a power line.

Generally, the circuit architecture in integrated circuits can be roughly divided into two categories according to their functions: core circuit and input and output circuit. The core circuit is responsible for signal processing or conversion in the integrated circuit, and the input and output circuits are used as a window or bridge for communication between the integrated circuit and external electronic components. With the evolution of semiconductor manufacturing process and the demand for computing speed, the core power supply voltage used by core circuits is often lower and lower. However, the I/O circuit must have sufficient driving force and matching requirements with external electronic components, so the I/O power supply voltage used by the I/O circuit is often much higher than the core power supply voltage. For example, the input and output supply voltage may be maintained at 3.3V, while the core supply voltage is as low as 0.9V. And when the core power supply voltage is as low as 0.9V, many problems that are unknown in the prior art occur, and need to be overcome or solved.

Contents of the invention

Embodiments provide an output circuit suitable for an integrated circuit. The output circuit includes a driver, a pre-driver, and a buffer circuit. The driver is electrically connected to two output terminals outside the integrated circuit for signal output. The front driver is used to control the driver and includes a load and an input transistor connected in series. There is a contact between the load and the input transistor for controlling the driver. The buffer circuit controls the load and the input transistor according to an internal signal. The buffer circuit lowers an impedance of the load to change the voltage of the contact before controlling the input transistor to turn off.

The embodiment further provides a control method suitable for an output circuit of an integrated circuit. The output circuit includes a pre-driver and a driver with signal streams. The driver is electrically connected to two output terminals outside the integrated circuit for signal output. The front driver includes a load and an input transistor connected in series. A contact between the load and the input transistor is electrically connected to the driver. The control method includes: reducing an impedance of the load according to an internal signal; and controlling the input transistor to turn off according to the internal signal after reducing the impedance of the load.

The embodiment further provides a control method applicable to an output circuit of an integrated circuit. The output circuit includes a driver and a front driver. The driver is electrically connected to two output terminals outside the integrated circuit for signal output. The front driver has a non-inverting output and an inverting output. The control method includes: according to an internal signal, after making a voltage of the reverse output approach a power line voltage, make a voltage of the non-reverse output start to move away from the power line voltage; and, according to the non-reverse The voltage to the output and the voltage to the inverse output control the driver. A time point at which the voltage of the inverting output begins to approach the power line voltage is earlier than a time point at which the voltage of the non-inverting output begins to diverge from the power line voltage.

Description of drawings

FIG. 1 shows a transmitter IC and a receiver IC.

Figure 2 shows some signal waveforms of the transmitter IC in Figure 1.

FIG. 3 shows an output circuit according to an embodiment of the invention.

Figure 4 shows some signal waveforms and timing relationships in Figure 3.

FIG. 5 shows another embodiment of the snubber circuit in FIG. 3 .

FIG. 6 shows another embodiment of the front driver in FIG. 3 .

FIG. 7 shows an output circuit according to another embodiment of the present invention.

Detailed ways

FIG. 1 shows an output circuit 100 in a transmitter IC electrically connected to a receiver IC 180 through transmission lines 106N and 106P. The output circuit 100 has a buffer circuit 108 , a pre-driver 102 , and a current-mode driver 104 . The current mode driver 104 is electrically connected to the two terminal resistors Rdln and Rdlp in the receiver IC 180 through the transmission lines 106N and 106P outside the transmitter IC, and the terminal resistors Rdln and Rdlp are electrically connected to the receiver IC 180 The output-input power line VIO-RX in, which is 3.3V.

According to the internal signal V _S- internal on the internal terminal S-internal, the buffer circuit 108 generates non-inverting signals V _S-non and Inversion signal V _S-inv . In this description, a logic 1 represents a relatively high voltage, and logic 0, which is the opposite of a logic 1, represents a relatively low voltage.

The front driver 102 has two NMOS transistors Nnpr and Nipr, two load resistors Rpln and Rplp, and a current source It-pr. The NMOS transistor Nnpr, the load resistor Rpln and the current source It-pr are connected in series between the core power line Vcore (0.9V) and the ground line (0V). Similarly, the NMOS transistor Nipr, the load resistor Rplp and the current source It-pr are connected in series between the core power line Vcore and the ground line. The connection point ND- between the NMOS transistor Nnpr and the load resistor Rpln is electrically connected to control the NMOS transistor Nndr in the current mode driver 104; the connection point ND+ between the NMOS transistor Nipr and the load resistor Rplp is electrically connected to control the current mode driver NMOS transistor Nidr in 104 . In short, the NMOS transistors Nnpr and Nipr can switch the current It-pr of the current source It- _pr to flow through the load resistor Rpln or Rplp, thereby determining the signals V _ND- and V _{ND+ on the connection points ND- and ND+} . Therefore, the non-inversion signal V _S-non and the inversion signal V _S-inv can be regarded as two current switching signals. The connection points ND− and ND+ can be regarded as the inverting output and the non-inverting output of the front driver 102 respectively.

The NMOS transistors Nndr and Nidr in the current mode driver 104 are electrically connected to the current source It-dr. Similarly, the NMOS transistors Nndr and Nidr can switch the current It-dr of the current source It- _dr to flow through the terminal resistor Rdln or Rdlp, thereby determining the output signals V _NO- and V _{NO+ on the output terminals NO- and NO+} .

Figure 2 shows some of the signal waveforms in Figure 1. As the non-inversion signal V _S-non and the inversion signal V _S-inv change their voltage values at time t1, that is, change their logic values, the signals V _ND- and V _ND+ in the front driver 102 start to change its voltage value. Such a change is not completed until time t4. During the period between time points t2 and t3, the signals V _ND− and V _ND+ cross. In FIG. 2 , the signals V _ND- and V _ND+ cross over the crossover voltage V _ND-CROSS . In order to have sufficient signal swing, the minimum voltage V _ND-MIN of the signals V _ND- and V _ND+ should be as low as possible. It is expected that the lower the minimum voltage value V _ND-MIN , the lower the crossover voltage V _ND-CROSS .

Please note that the current source It-dr in the current mode driver 104 needs to have enough voltage across V _DROP to maintain the current It _-dr at a desired constant value. However, as shown in Figure 2, during the period between time points t2 and t3, because the signals V _ND- and V _ND+ are low at the same time, the cross-voltage V _DROP is insufficient, causing the current I _t-dr to decrease unfortunately, It is no longer a preset value.

The unstable current I _t-dr will worsen electromagnetic interference (EMI). In FIG. 2 , the output common-mode signal V _CM represents the average value of the output signals V _NO− and V _NO+ . When the resistance values of the terminal resistors Rdln and Rdlp are both fixed at R _LOAD , the voltage of the output common-mode signal V _CM in FIG. 1 will be about (3.3-0.5*I _t-dr *R _LOAD ) volts. When the current I _t-dr is a certain value, it can be deduced that the output common-mode signal V _CM will be approximately a constant voltage. However, when the current I _t-dr becomes smaller, the output common-mode signal V _CM will increase, as shown in Figure 2. However, the unstable output common-mode signal V _CM will produce relatively large electromagnetic wave interference. In other words, the signals V _ND- and V _ND+ are low at the same time, that is, the crossover voltage V _ND-CROSS is low, which may cause undesirable electromagnetic wave interference.

FIG. 3 shows an output circuit 200 implemented according to the present invention. In one embodiment, the output circuit 200 replaces the output circuit 100 in FIG. 1 . Although not shown in FIG. 3 , in an embodiment, the output circuit 200 can be electrically connected to the receiver integrated circuit 180 through the transmission lines 106N and 106P in FIG. 1 . For the convenience of explanation, many symbols in FIG. 3 are the same as those in FIG. 1 , and the components, materials, or substances represented by them are functionally the same or similar, so they may not be repeated here. But the present invention is not limited thereto, components with the same symbol may be implemented with different circuits, materials, or structures in different embodiments.

In FIG. 3 , buffer circuit 208 provides a signal to pre-driver 202 , which provides a signal to current mode driver 104 . Therefore, the buffer circuit 208, the pre-driver 202, and the current mode driver 104 form a signal cascode structure.

Compared with the front driver 102 in FIG. 1 , the front driver 202 in FIG. 3 has more PMOS transistors Ppln and Pplp. The parallel-connected PMOS transistor Ppln and the load resistor Rpln form a load Ln; the parallel-connected PMOS transistor Pplp and the load resistor Rplp form another load Lp. The PMOS transistors Ppln and Pplp respectively have control terminals S-CHG+ and S-CHG-, on which load control signals V _S-CHG+ and V _S-CHG- are respectively provided.

Compared with the buffer circuit 108 in FIG. 1 , the buffer circuit 208 in FIG. 3 is additionally electrically connected to the control terminals S-CHG+ and S-CHG-. It can be seen from the circuit connection of the buffer circuit 208 that the load control signals V _S-CHG+ and V _S-CHG- are both generated by delaying the internal signal V _S- internal on the internal terminal S-internal, and only the load control signal V _{S- CHG+} is the logical opposite of _VS-CHG- . In other words, when the load control signal V _S-CHG+ is at a high voltage of logic 1, the load control signal V _S-CHG- will be at a low voltage of logic 0. Similarly, the non-inversion signal V _S-non and the inversion signal V _S-inv are generated by delaying the load control signals V _S-CHG- and V _S-CHG+ respectively, so the non-inversion signal V _S-non and the inversion Inverse to the logic value of signal V _S-inv .

Figure 4 shows some signal waveforms and timing relationships in Figure 3. In Figure 4, the signal delay time between the internal signal V _S-internal and the load control signal V _S-CHG+ and V _S-CHG- is about Td ₁ ; the load control signal V _S-CHG- or V _S- The signal delay time between _CHG+ and the non-inversion signal V _S-non or the inversion signal V _S-inv is about Td ₂ . It can be deduced that the signal delay time between the internal signal V _S-internal and the non-inverted signal V _S-non or the inverted signal V _S-inv is about Td ₁ +Td ₂ .

Before the time point t0, the non-inversion signal V _S-non and the inversion signal V _S-inv are respectively at a low voltage (logic 0) and a high voltage (logic 1), so almost all the current I _t-pr will be It flows through the NMOS transistor Nipr, so the signal V _ND+ is at a low voltage, and the signal V _ND- is at a high voltage, as shown in FIG. 4 .

As shown in FIG. 4 , at the time point t0 , the internal signal V _S-internal changes from a low voltage (logic 0) to a high voltage (logic 1).

At the time point _t01 after the signal delay time Td1, the load control signals V _S-CHG+ and V _S-CHG- start to change. The voltage of the load control signal V _S-CHG+ increases, and the channel impedance of the PMOS transistor Ppln increases, so the impedance of the load Ln increases. Conversely, the voltage of the load control signal V _S-CHG- decreases, so the impedance of the load Lp decreases. At time point t01, since there is almost no current flowing through the NMOS transistor Nnpr and the load Ln, the increase in the impedance of the load Ln will not affect the signal V _ND- , which remains at a high voltage, such as the core power line 0.9V for Vcore. At time point t01, since almost all of the current I _t-pr flows through the load Lp, the decrease in the impedance of the load Lp will pull up the voltage of the signal V _ND+ , making it start to approach 0.9V, as shown in FIG. 4 .

At time point t1 after the signal delay time Td ₂ , the non-inversion signal V _S-non and the inversion signal V _S-inv start to change. At this time, the impedance of the NMOS transistor Nnpr decreases, while the impedance of the NMOS transistor Nipr increases. The current I _t-pr is switched from flowing through the load Lp to flowing through the load Ln. Therefore, the signal V _ND- begins to drop from 0.9V, and the signal V _ND+ maintains an upward trend or remains at 0.9V.

The load control signals V _S-CHG- and V _S-CHG+ are equivalent to two feed-forward signals. At time t01 before the impedances of the NMOS transistors Nnpr and Nipr change, the loads Lp and Ln are changed in advance. impedance. As shown in FIG. 4 , as a result of such feedforward, the signal ND+ starts to rise at the time point t01 , and the signal ND- starts to fall at the time point t1 .

Some dotted lines in FIG. 4 reproduce the signal V _ND+ , the current I _t-dr , and the output common-mode signal V _CM in FIG. 2 for comparison. In the embodiment shown in FIG. 3 and FIG. 4, since the signal V _ND+ starts to rise at the time point t01, the crossover voltage V _ND-CROSS-NEW of the signal V _ND+ and V _ND- will be compared with that in FIG. 2 The crossover voltage V _ND-CROSS comes high. As long as the design is proper, the higher crossover voltage V _ND-CROSS-NEW can ensure that the current source It-dr in Figure 3 has enough cross-voltage V _DROP to maintain the current It _-dr and output the common-mode signal V _CM is a fixed value, as shown in Figure 4. In other words, the embodiment of FIG. 3 can improve the electromagnetic wave interference problem caused by the unstable output common-mode signal V _CM in FIG. 1 .

It can also be deduced from the illustrations in FIG. 3 and FIG. 4 that when the internal signal V _S-internal changes from a high voltage of logic 1 to a low voltage of logic 0, the time point when the signal V _ND- begins to rise will be earlier than The time point when the signal V _ND+ starts to fall, so a higher crossover voltage can be obtained. It can also stabilize the current I _t-dr and output the common mode signal V _CM .

In FIG. 3 , the non-inversion signal V _S-non is generated by the delayed load control signal V _S-CHG- , but the invention is not limited thereto. FIG. 5 shows another buffer circuit 208a, which may replace buffer circuit 208 in some embodiments. In FIG. 5 , the non-inverting signal V _S-non is generated by the delayed load control signal V _S-CHG+ , and the inverted signal V _S-inv is generated by the delayed load control signal V _S-CHG- .

FIG. 6 shows another front driver 202a, which may be used to replace the front driver 202 in FIG. 3 in some embodiments. Compared with the front driver 202 in FIG. 3 , the front driver 202 a in FIG. 6 uses NMOS transistors Npln and Nplp to change the impedances of the loads Lna and Lpa. Figure 4 can also be used to illustrate some of the signal waveforms in Figure 6. The front driver 202a in FIG. 6 can improve the problem of electromagnetic wave interference.

The output circuits exemplified above all use NMOS transistors as current switching switches. For example, the NMOS transistors Nnpr and Nipr in FIG. 1 are two current switching switches. However, the present invention is not limited thereto. FIG. 7 shows an output circuit 400 according to another embodiment of the present invention, in which many PMOS transistors are used as current switching switches. The operation principle of FIG. 7 and the effect of improving electromagnetic interference can be known by referring to the previous description, so it will not be repeated here. Of course, in some embodiments, the NMOS transistor used to change the load impedance in FIG. 7 can also be implemented by using a PMOS transistor instead.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (20)

1. An output circuit suitable for integrated circuits, comprising: a driver electrically connected to two output terminals outside the integrated circuit for signal output; A front driver, used to control the driver, includes a load connected in series and an input transistor, wherein there is a contact between the load and the input transistor to control the driver; and The buffer circuit controls the load and the input transistor according to an internal signal, wherein the buffer circuit lowers the impedance of the load to change the voltage of the contact before controlling the input transistor to turn off. 2. The output circuit according to claim 1, wherein the buffer circuit delays the internal signal for a first delay time and a second delay time to generate a load control signal and a switching signal, which are respectively used to control the load and the input transistor. 3. The output circuit according to claim 2, wherein the input transistor is a first input transistor, and the front driver further has a second input transistor, and the first and second input transistors are respectively controlled by the reverse signal and a non-inverting signal, one of the inverting signal and the non-inverting signal is generated by delaying the load control signal. 4. The output circuit as claimed in claim 2, wherein the load comprises a load transistor and a resistor connected in parallel, and the load control signal is used to control the load transistor. 5. The output circuit as claimed in claim 4, wherein the input transistor is an NMOS transistor, and the load transistor is a PMOS transistor. 6. The output circuit as claimed in claim 1, wherein the buffer circuit first increases the impedance of the load before controlling the input transistor to turn on. 7. The output circuit according to claim 1, wherein the pre-driver further comprises a current source, and the load and the input transistor are sequentially connected in series between the power line and the current source. 8. The output circuit according to claim 7, wherein the current source is a first current source, and the driver is a current mode driver, which further includes a transistor pair and a second current source, and the second current source string It is connected between the transistor pair and another power supply line, and the transistor pair is electrically connected to the two output terminals. 9. The output circuit according to claim 1, wherein the load and the input transistor are respectively a first load and a first input transistor, and the front driver further has a second load and a second input transistor connected in series, The buffer circuit controls the second input transistor to turn on while controlling the first input transistor to turn off, and the buffer circuit increases the impedance of the second load when reducing the impedance of the first load. 10. A control method applicable to an output circuit of an integrated circuit, the output circuit includes a front driver and a driver with signal serial flow, and the driver is used to electrically connect to two output terminals outside the integrated circuit for signal output, the The front driver includes a load connected in series and an input transistor, wherein a contact between the load and the input transistor is electrically connected to the driver, and the control method includes: reduce the impedance of the load, depending on the internal signal; and After reducing the impedance of the load, the input transistor is controlled to be turned off according to the internal signal. 11. The control method according to claim 10, wherein the load is a first load, the input transistor is a first input transistor, and the front driver further includes a second load and a second input transistor connected in series, The control method also includes: increasing the impedance of the second load according to the internal signal; and After increasing the impedance of the second load, the second input transistor is controlled to turn on according to the internal signal. 12. The control method according to claim 10, further comprising: delaying the internal signal to generate a load control signal for reducing the impedance of the load; and The internal signal is delayed to generate a switching signal for controlling the input transistor to be turned off. 13. The control method according to claim 12, wherein the load comprises a load transistor and a resistor connected in parallel, and the load and the input transistor are connected in series between the power line and the current source, and the control method further comprises : controlling the load transistor with the load control signal; and The input transistor is controlled with the switching signal. 14. A control method suitable for an output circuit of an integrated circuit, the output circuit includes a driver and a front driver, the driver is used to electrically connect to two output terminals outside the integrated circuit for signal output, and the front driver has a non- Reverse output and reverse output, the control method includes: According to the internal signal, after the voltage of the inverting output starts to approach the voltage of the power line, the voltage of the non-inverting output starts to move away from the voltage of the power line; and controlling the driver according to the voltage of the non-inverting output and the voltage of the inverting output; Wherein, the time point when the voltage of the inverting output starts to approach the power line voltage is earlier than the time point when the voltage of the non-inverting output starts to move away from the power line voltage. 15. The control method according to claim 14, wherein the front driver comprises first and second input transistors, and a current source, and the first input transistor is electrically connected between the reverse output and the current source Between, the second input transistor is electrically connected between the non-inverting output and the current source, and the control method further includes: electrically connecting a first load between the non-inverting output and the power line; electrically connecting a second load between the reverse output and the power line; reducing the impedance of the first load and increasing the impedance of the second load; and controlling the first input transistor to turn off and controlling the second input transistor to turn on; Wherein, the time point of controlling the first input transistor to be turned off and the second input transistor to be turned on is later than the time point of starting to decrease the impedance of the first load and increase the impedance of the second load. 16. The control method according to claim 15, further comprising: delaying the internal signal to generate first and second load control signals for controlling the first and second loads respectively; and The internal signal is delayed to generate first and second current switching signals for respectively controlling the first and second input transistors. 17. The control method according to claim 15, wherein the current source is a first current source, the driver is a current mode driver, and the driver further includes a transistor pair and a second current source, and the second current source It is connected in series between the transistor pair and the power line, and the transistor pair is electrically connected to the two output terminals. 18. The control method according to claim 17, wherein the inverting output and the non-inverting output respectively control one of the transistor pair. 19. An output circuit suitable for an integrated circuit, comprising: a driver electrically connected to two output terminals outside the integrated circuit for signal output; and Front drive, containing: an input transistor controlled to be turned off according to the first control signal; and The load reduces the impedance according to the second control signal, wherein There is a contact between the input transistor and the load to control the driver, and before the input transistor is turned off according to the first control signal, the load lowers impedance according to the second control signal to change the voltage of the contact. 20. The output circuit according to claim 19, further comprising: The buffer circuit generates the first control signal and the second control signal according to internal signals.