US20090267818A1 - Low distortion current switch - Google Patents
Low distortion current switch Download PDFInfo
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- US20090267818A1 US20090267818A1 US12/108,996 US10899608A US2009267818A1 US 20090267818 A1 US20090267818 A1 US 20090267818A1 US 10899608 A US10899608 A US 10899608A US 2009267818 A1 US2009267818 A1 US 2009267818A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
Definitions
- the present invention relates in general to electronic signal processing, and more specifically, to digital to analog signal conversion.
- FIG. 1 shows a portion of a typical current steering DAC 100 in which a digital data stream is applied to a synchronous digital output latch 101 .
- “Synchronous” means that the data on the latch input is transferred to the output in response to triggering of the latch by a clocking signal. In some applications, considerable digital processing is involved in producing such a digital data stream, but in the context of a DAC, such preceding digital circuitry need not be described.
- the latch 101 is clocked, the data present on the D-input is transferred to the Q output, and its complement is transferred to the Q-bar output.
- the outputs of latch 101 asynchronously control switch drivers 102 , which in turn control differential switching elements 103 .
- Asynchronously means that the logic state of the outputs of the switch drivers 102 and the differential switching elements 103 change state in response to their inputs changing state rather than in response to a clocking signal. For a given logic state present on the output of the latch 101 , one switch of the differential switching elements 103 will be “ON,” and the other will be “OFF”. When the logic state on the output latch 101 changes, the ON-OFF states of the differential switching element 103 provide an analog signal at output terminals 106 .
- such a current steering DAC 100 can operate at any frequency to provide an analog output corresponding to the digital data input.
- errors and noise occur throughout the system, the effects of which increase with operating frequency. These effects may be code dependent and may result in harmonic distortion and harmonic spurs in the analog output signal.
- a current switching DAC may employ multiple current switching elements. If each individual switching element is clocked from the same clock buffer, which may be desirable to minimize switching instant mismatch, the clock buffer may see a load dependent upon the number of elements switching. As the number of elements switching is related to the signal being processed, the clock may see a signal dependent load. Consequently, there may be a signal dependent clocking instant, resulting in third order distortion.
- FIG. 2 illustrates a clock driver 210 connected to switching element 240 which may be a PFET or an NFET.
- switching element 240 When clock input 205 changes state, for example from high to low, the output of the driver 210 will change from low to high, thereby turning “ON” switching element 240 .
- Switching element 240 has inherent coupling capacitance 220 between the gate to drain and coupling capacitance 230 between gate to source.
- the clock driver 210 is dependent on the data that is on nodes 250 and 255 . For example there is a difference in the current flowing into and out of the clock driver 210 when the data between node 250 and node 255 is changing and when the data is not changing. This difference in load, seen by clock driver 210 , based on the data on nodes 250 and 255 introduces third order harmonic distortion, which is not desirable.
- the output of the dummy latch is not itself used in any way, rather the dummy latch and the output latch 101 are connected and operated such that with every cycle of the clocking signal, one of the latches will change state and the other will not.
- the dummy latch maintains its logic state
- the output latch 101 maintains its logic state constant with an unchanging data signal
- the dummy latch will change logic states.
- the attempt to equalize the loading to the clock by the addition of dummy latches and the corresponding support circuitry may add to the overall complexity, overhead, mismatch, power consumption, and size of the implementation.
- FIG. 1 shows a portion of a typical current steering DAC.
- FIG. 2 shows an example of the data dependent load that a clocking driver may see.
- FIG. 3 a shows a digital control circuitry with a NAND implementation of the SR latch in accordance with an embodiment of the invention.
- FIG. 3 b shows a digital control circuitry with a NOR implementation of the SR latch in accordance with an embodiment of the invention.
- FIG. 4 a shows a truth table for a NAND implementation of an SR latch.
- FIG. 4 b shows a truth table for a NOR implementation of an SR latch.
- FIG. 5 shows exemplary waveforms related to the digital control circuitry with a NAND implementation of the SR latch in accordance with an embodiment of the invention.
- FIG. 6 a shows a complementary current switch configuration as may be used with an embodiment of the invention.
- FIG. 6 b shows input waveforms which may prevent cross-over distortion in accordance with an embodiment of the invention.
- FIG. 3 a shows a digital control circuitry with a NAND implementation of an SR latch in accordance with an embodiment of the invention.
- Such architecture may comprise a data input 310 and a complementary input 315 , clock input 320 , pre-charging switches 340 and 345 , an SR Latch 390 , comprising NAND gates 350 and 355 , and complementary current outputs 370 and 375 , controlled by switches 360 and 365 which may be supplied by current source 380 .
- Switching elements 330 and 335 are coupled to data inputs 310 and 315 accordingly.
- switching elements 330 and 335 When turned “ON,” switching elements 330 and 335 provide a path to the SR Latch 390 comprising NAND gates 350 and 355 .
- switching elements 330 and 335 may be NFETS.
- the gates of the switching elements 330 and 335 are controlled by clocking signal 320 .
- clocking signal 320 When the clock is “high,” data from input 310 and complementary input 315 is passed through switching devices 330 and 335 to NAND 350 and 355 respectively.
- the clock When the clock is “low,” data input 310 and complementary input 315 is prevented to pass through switching devices 330 and 335 .
- switching devices 340 and 345 pre-charge node Id and Idb to “high” respectively.
- switching devices 340 and 345 are PFETs.
- both input nodes Id and Idb to the SR Latch 390 are at “high.”
- data input 310 and complementary input 315 is passed to the input nodes Id and Idb, respectively, becoming the inputs to the SR Latch 390 .
- the latch 390 is a basic SR latch comprising two cross-coupled NAND gates 350 and 355 .
- the input to NAND 350 is signal Id and the output of NAND 355 (signal swb).
- the input of NAND 355 is Idb and the output of NAND 350 (signal sw).
- Outputs sw and swb are complements of each other.
- the NAND embodiment of the SR latch 390 “holds” the data stored in the SR latch 390 when inputs Id and its complement Idb are forced to “high” during the pre-charge state.
- the SR latch 390 is “reset” when Id input is “high” and the complementary input Idb is “low.”
- the “reset” forces output of NAND 350 (signal sw) to go to “low” while the complementary output at the output of NAND 355 (signal swb) goes to “high.”
- This situation may arise when the clock input 320 is “high,” and, thus, not in the pre-charge state, and the data from input 310 is “high” while complementary input 315 is “low.”
- the SR latch 390 is “set” when Id input is “low” and the complementary input Idb is “high.”
- the “set” forces output of NAND 350 (signal sw) to go to “high” while the complementary output at the output of NAND 355 (signal swb) goes to “low.” This situation may arise when the clock input 320 is “high,” and, thus, not in the pre-charge state, and the data from input 310 is “low” while complementary input 315 is “
- the output of the SR latch 390 may be coupled to differential switching elements 360 and 365 , as illustrated in FIG. 3 a .
- Current source 380 may be coupled to ground and provide the current for switching elements 360 and 365 .
- the complementary signal swb is “low,” turning “ON” switch 360 while turning “OFF” switch 365 .
- the current from current source 380 flows substantially through switch 360 and output Iout, 370 .
- the complementary signal swb is “high,” turning “OFF” switch 360 while turning “ON” switch 365 .
- the current from current source 380 flows substantially through switch 365 and output Ioutb, 375 .
- Switches 360 and 365 may be FETs or bipolar devices. In the preferred embodiment of FIG. 3 a , switches 360 and 380 are NFETs.
- FIG. 3 b illustrates digital control circuitry with a NOR implementation of the SR latch in accordance with an embodiment of the invention.
- Such architecture may comprise a data input 310 and a complementary input 315 , clock input 320 , pre-charging switches 440 and 445 , an SR Latch 490 , comprising NOR gates 450 and 455 , and complementary current outputs 370 and 375 , controlled by switches 460 and 465 which may be supplied by current source 480 .
- Switching elements 430 and 435 are coupled to data inputs 310 and 315 respectively.
- switching elements 430 and 435 When turned “ON,” switching elements 430 and 435 provide a path to the SR Latch 490 comprising NOR gates 450 and 455 .
- switching elements 430 and 435 may be PFETS.
- the gates of the switching elements 430 and 435 are controlled by clocking signal 320 .
- clocking signal 320 When the clock is “low,” data from input 310 and complementary input 315 is passed through switching devices 430 and 435 to NOR 450 and 455 respectively.
- the clock When the clock is “high,” data input 310 and complementary input 315 is prevented to pass through switching devices 430 and 435 .
- switching devices 440 and 445 pre-charge node Id and Idb to “low” respectively.
- switching devices 440 and 445 are NFETs.
- both input nodes Id and Idb to the SR Latch 490 are at “low.”
- data input 310 and complementary input 315 is passed to the input nodes Id and Idb, respectively, to the SR Latch 490 .
- the latch 490 is a basic SR latch comprising two cross-coupled NOR gates 450 and 455 .
- the input to NOR 450 is signal Id and the output of NOR 455 (signal swb).
- the input of NOR 455 is signal Idb and the output of NOR 450 (signal sw).
- the outputs sw and swb are complements of each other.
- the NOR embodiment of the SR latch 490 “holds” the data stored in the SR latch 490 when inputs Id and its complement Idb are forced to “low” during the pre-charge state.
- the SR latch 490 is “reset” when Id input is “high” and the complementary input Idb is “low.”
- the “reset” forces output of NOR 450 (signal sw) to go to “low” while the complementary output at the output of NOR 455 (signal swb) goes to “high.”
- This situation may arise when the clock input 320 is “low,” and, thus, not in the pre-charge state, and the data from input 310 is “high” while complementary input 315 is “low.”
- the SR latch 490 is “set” when Id input is “low” and the complementary input Idb is “high.”
- the “set” forces output of NOR 450 (signal sw) to go to “high” while the complementary output at the output of NOR 455 (signal
- the output of the SR latch 490 may be coupled to differential switching elements 460 and 465 , as illustrated in FIG. 3 b .
- Current source 480 may be coupled to vdd and provides the current for switching elements 460 and 480 .
- the complementary signal swb is “low,” turning “ON” switch 465 while turning “OFF” switch 460 .
- the current from current source 480 flows substantially through switch 465 and output Ioutb, 375 in such a situation.
- Switches 460 and 465 may be FETs or bipolar devices. In the preferred embodiment of FIG. 3 b , switches 460 and 480 are PFETs.
- the RS latch which may be, for example, NAND configuration 390 or NOR configuration 490
- the outputs of the RS latch will “hold” state. This may be achieved, for example, through pre-charging input nodes Id and Idb to the same logic state, which may be “high” for a NAND configured RS latch 390 or “low” for a NOR configured RS latch 490 .
- the RS latch changes state when either of the inputs Id or Idb is taken to the opposite level.
- Data input d ( 310 ) and its complement db ( 315 ) to the SR latch is each in series with a switch, controlled by the clock signal 320 .
- the switches are “OFF” the inputs Id and Idb to the SR latch ( 390 or 490 ) are pre-charged to a level that would induce the RS latch ( 390 or 490 ) to a “hold” state.
- the clock signal 320 turns “ON” the series switches, there will only be a single data transition, regardless of the previous data held by the RS latch ( 390 or 490 ). This ensures that the clock driver only sees a single data transition every clock cycle. Therefore, the clock driver is independent of the data signals 310 and 315 , thereby reducing third order harmonic distortion.
- FIG. 5 shows exemplary waveforms associated with the digital control circuitry of FIG. 3 a in accordance with an embodiment of the invention.
- Signal 510 represents the clock signal that controls the series switches 330 and 335 , as well as pre-charge switches 340 and 345 of FIG. 3 a .
- Signals 520 and 530 are the complementary data inputs d and db, each in series with switches 340 and 345 respectively.
- Signals Id ( 540 ) and Idb ( 550 ) are “high” when clock signal 510 is “low,” and thus in a pre-charge state. When the clock is “high,” the signal d ( 520 ) is forced onto Id ( 540 ) while the signal db ( 530 ) is forced onto Idb ( 550 ).
- Signals sw ( 560 ) and swb ( 570 ) are the complementary outputs of the NAND SR latch 390 .
- the signals Id ( 540 ) and Idb ( 550 ) are “high,” the data in the latch is held.
- FIG. 6 a shows closer view of the complementary current switch configuration of FIG. 3 a , as may be used in an embodiment of the invention.
- a linear sweep from “high” to “low” of signal sw at the gate of switch 360 and a proportional sweep of “low” to “high” of signal swb at the gate of switch 365 , where both sw and swb signals are equal in magnitude at the cross-over point, may create a dead-band region, where both switches 360 and 365 are “OFF,” which is undesirable.
- FIG. 6 a shows closer view of the complementary current switch configuration of FIG. 3 a , as may be used in an embodiment of the invention.
- the output of an SR latch inherently has a crossover which is about a threshold voltage above the common mode, CS, of the sw and swb signals. This high cross-over prevents dead-band, which assures smooth current transition from one switch to the other, for example switch 360 to 365 , thereby preventing crossover distortion.
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Abstract
Description
- A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever.
- The present invention relates in general to electronic signal processing, and more specifically, to digital to analog signal conversion.
- A current steering digital-to-analog converter (DAC) converts a digital data stream input into a corresponding analog signal output.
FIG. 1 shows a portion of a typicalcurrent steering DAC 100 in which a digital data stream is applied to a synchronousdigital output latch 101. “Synchronous” means that the data on the latch input is transferred to the output in response to triggering of the latch by a clocking signal. In some applications, considerable digital processing is involved in producing such a digital data stream, but in the context of a DAC, such preceding digital circuitry need not be described. When thelatch 101 is clocked, the data present on the D-input is transferred to the Q output, and its complement is transferred to the Q-bar output. - The outputs of
latch 101 asynchronously controlswitch drivers 102, which in turn controldifferential switching elements 103. “Asynchronously” means that the logic state of the outputs of theswitch drivers 102 and thedifferential switching elements 103 change state in response to their inputs changing state rather than in response to a clocking signal. For a given logic state present on the output of thelatch 101, one switch of thedifferential switching elements 103 will be “ON,” and the other will be “OFF”. When the logic state on theoutput latch 101 changes, the ON-OFF states of thedifferential switching element 103 provide an analog signal atoutput terminals 106. - In theory, such a
current steering DAC 100 can operate at any frequency to provide an analog output corresponding to the digital data input. In practice, errors and noise occur throughout the system, the effects of which increase with operating frequency. These effects may be code dependent and may result in harmonic distortion and harmonic spurs in the analog output signal. - A current switching DAC may employ multiple current switching elements. If each individual switching element is clocked from the same clock buffer, which may be desirable to minimize switching instant mismatch, the clock buffer may see a load dependent upon the number of elements switching. As the number of elements switching is related to the signal being processed, the clock may see a signal dependent load. Consequently, there may be a signal dependent clocking instant, resulting in third order distortion.
- For example,
FIG. 2 illustrates aclock driver 210 connected to switchingelement 240 which may be a PFET or an NFET. Whenclock input 205 changes state, for example from high to low, the output of thedriver 210 will change from low to high, thereby turning “ON”switching element 240. Switchingelement 240 hasinherent coupling capacitance 220 between the gate to drain and couplingcapacitance 230 between gate to source. Thus, due to coupling, theclock driver 210 is dependent on the data that is onnodes clock driver 210 when the data betweennode 250 andnode 255 is changing and when the data is not changing. This difference in load, seen byclock driver 210, based on the data onnodes - One approach to reducing code dependent noise is presented in FIG. 8 of U.S. Pat. No. 6,344,816, which describes adding an additional clocked circuit called a “dummy latch” in parallel with the
output latch 101. The output of the dummy latch is not itself used in any way, rather the dummy latch and theoutput latch 101 are connected and operated such that with every cycle of the clocking signal, one of the latches will change state and the other will not. Thus, if theoutput latch 101 changes state with the data signal, the dummy latch maintains its logic state, and if theoutput latch 101 maintains its logic state constant with an unchanging data signal, then the dummy latch will change logic states. However, the attempt to equalize the loading to the clock by the addition of dummy latches and the corresponding support circuitry, may add to the overall complexity, overhead, mismatch, power consumption, and size of the implementation. - Thus, there is a need for an efficient system and method for a low distortion current switch, which ensures that the load seen by the clock buffer is the same in every clocking cycle, while achieving low third harmonic distortion.
- The invention is illustrated in the figures of the accompanying drawings, which are meant to be exemplary and not limiting, and in which like references are intended to refer to like or corresponding parts.
-
FIG. 1 shows a portion of a typical current steering DAC. -
FIG. 2 shows an example of the data dependent load that a clocking driver may see. -
FIG. 3 a shows a digital control circuitry with a NAND implementation of the SR latch in accordance with an embodiment of the invention. -
FIG. 3 b shows a digital control circuitry with a NOR implementation of the SR latch in accordance with an embodiment of the invention. -
FIG. 4 a shows a truth table for a NAND implementation of an SR latch. -
FIG. 4 b shows a truth table for a NOR implementation of an SR latch. -
FIG. 5 shows exemplary waveforms related to the digital control circuitry with a NAND implementation of the SR latch in accordance with an embodiment of the invention. -
FIG. 6 a shows a complementary current switch configuration as may be used with an embodiment of the invention. -
FIG. 6 b shows input waveforms which may prevent cross-over distortion in accordance with an embodiment of the invention. - A system and method are provided for making the load of the clock driver independent of data, thereby reducing third order harmonic distortion.
FIG. 3 a shows a digital control circuitry with a NAND implementation of an SR latch in accordance with an embodiment of the invention. Such architecture may comprise adata input 310 and acomplementary input 315,clock input 320, pre-chargingswitches NAND gates 350 and 355, and complementarycurrent outputs switches current source 380.Switching elements data inputs switching elements NAND gates 350 and 355. In one embodiment, switchingelements switching elements signal 320. When the clock is “high,” data frominput 310 andcomplementary input 315 is passed through switchingdevices data input 310 andcomplementary input 315 is prevented to pass through switchingdevices devices devices data input 310 andcomplementary input 315 is passed to the input nodes Id and Idb, respectively, becoming the inputs to the SR Latch 390. - The
latch 390 is a basic SR latch comprising twocross-coupled NAND gates 350 and 355. The input toNAND 350 is signal Id and the output of NAND 355 (signal swb). Similarly, the input of NAND 355 is Idb and the output of NAND 350 (signal sw). Outputs sw and swb are complements of each other. The NAND embodiment of the SRlatch 390 “holds” the data stored in the SRlatch 390 when inputs Id and its complement Idb are forced to “high” during the pre-charge state. The SRlatch 390 is “reset” when Id input is “high” and the complementary input Idb is “low.” The “reset” forces output of NAND 350 (signal sw) to go to “low” while the complementary output at the output of NAND 355 (signal swb) goes to “high.” This situation may arise when theclock input 320 is “high,” and, thus, not in the pre-charge state, and the data frominput 310 is “high” whilecomplementary input 315 is “low.” Alternatively, theSR latch 390 is “set” when Id input is “low” and the complementary input Idb is “high.” The “set” forces output of NAND 350 (signal sw) to go to “high” while the complementary output at the output of NAND 355 (signal swb) goes to “low.” This situation may arise when theclock input 320 is “high,” and, thus, not in the pre-charge state, and the data frominput 310 is “low” whilecomplementary input 315 is “high.”FIG. 4 offers a truth table that summarizes the operation of a NAND configuredSR latch 390. The “set” column S, corresponds to input Id while the “reset” input R, corresponds to the complementary input Idb. Outputs Q and Q′ of the table correspond to signals sw and the complementary signal swb respectively. Thus, during the pre-chare state, S=1 (high) and R=1 (high), the outputs Q and Q′ “hold” the previous information stored in theSR latch 390. State S=0 (low), R=0 (low) is a forbidden state. Since the inputs to theSR latch 390 are either S=1 and R=1 during pre-charge or, when not in pre-charge, are complementary, state S=0, R=0 does not occur in the embodiment shown inconfiguration 300 ofFIG. 3 a. - In one embodiment, the output of the
SR latch 390 may be coupled todifferential switching elements FIG. 3 a.Current source 380 may be coupled to ground and provide the current for switchingelements switch 360 while turning “OFF”switch 365. Thus, the current fromcurrent source 380 flows substantially throughswitch 360 and output Iout, 370. Alternatively, if sw is “low,” the complementary signal swb is “high,” turning “OFF”switch 360 while turning “ON”switch 365. Now, the current fromcurrent source 380 flows substantially throughswitch 365 and output Ioutb, 375.Switches FIG. 3 a, switches 360 and 380 are NFETs. - Those skilled in the art will readily understand that the concepts described above can be applied with different devices and configurations. For example,
FIG. 3 b illustrates digital control circuitry with a NOR implementation of the SR latch in accordance with an embodiment of the invention. Such architecture may comprise adata input 310 and acomplementary input 315,clock input 320,pre-charging switches SR Latch 490, comprising NORgates current outputs switches current source 480. Switchingelements data inputs elements SR Latch 490 comprising NORgates elements elements signal 320. When the clock is “low,” data frominput 310 andcomplementary input 315 is passed through switchingdevices data input 310 andcomplementary input 315 is prevented to pass through switchingdevices devices devices SR Latch 490 are at “low.” When the clock is “low,”data input 310 andcomplementary input 315 is passed to the input nodes Id and Idb, respectively, to theSR Latch 490. - The
latch 490 is a basic SR latch comprising two cross-coupled NORgates - The NOR embodiment of the
SR latch 490 “holds” the data stored in theSR latch 490 when inputs Id and its complement Idb are forced to “low” during the pre-charge state. TheSR latch 490 is “reset” when Id input is “high” and the complementary input Idb is “low.” The “reset” forces output of NOR 450 (signal sw) to go to “low” while the complementary output at the output of NOR 455 (signal swb) goes to “high.” This situation may arise when theclock input 320 is “low,” and, thus, not in the pre-charge state, and the data frominput 310 is “high” whilecomplementary input 315 is “low.” Alternatively, theSR latch 490 is “set” when Id input is “low” and the complementary input Idb is “high.” The “set” forces output of NOR 450 (signal sw) to go to “high” while the complementary output at the output of NOR 455 (signal swb) goes to “low.” This situation may arise when theclock input 320 is “low,” and, thus, not in the pre-charge state, and the data frominput 310 is “low” whilecomplementary input 315 is “high.”FIG. 4 b offers a truth table that summarizes the operation of a NOR configuredSR latch 490. The “set” column S, corresponds to input Idb while the “reset” input R, corresponds to the complementary input Id. Outputs Q and Q′ of the table correspond to signals sw and the complementary signal swb accordingly. Thus, during the pre-chare state, S=0 (low) and R=0 (low), the outputs Q and Q′ “hold” the previous information stored in theSR latch 390. State S=1 (high), R=1 (high) is a forbidden state. Since the inputs to theSR latch 490 are S=0 and R=0 during pre-charge, or, when not in pre-charge, are complementary, state S=0, R=0 does not occur inconfiguration 400 ofFIG. 3 b. - In one embodiment, the output of the
SR latch 490 may be coupled todifferential switching elements FIG. 3 b.Current source 480 may be coupled to vdd and provides the current for switchingelements switch 465 while turning “OFF”switch 460. Thus, the current fromcurrent source 480 flows substantially throughswitch 465 and output Ioutb, 375 in such a situation. Alternatively, if sw is “low,” the complementary signal swb is “high,” turning “OFF”switch 465 while turning “ON”switch 460. Now, the current fromcurrent source 480 flows substantially throughswitch 460 and output Iout, 470.Switches FIG. 3 b, switches 460 and 480 are PFETs. - As provided for in the above description of the RS latch, which may be, for example,
NAND configuration 390 or NORconfiguration 490, there is a condition where if both inputs Id and Idb are at the same logic state, the outputs of the RS latch (390 or 490) will “hold” state. This may be achieved, for example, through pre-charging input nodes Id and Idb to the same logic state, which may be “high” for a NAND configured RS latch 390 or “low” for a NOR configured RS latch 490. The RS latch changes state when either of the inputs Id or Idb is taken to the opposite level. Data input d (310) and its complement db (315) to the SR latch is each in series with a switch, controlled by theclock signal 320. When the switches are “OFF” the inputs Id and Idb to the SR latch (390 or 490) are pre-charged to a level that would induce the RS latch (390 or 490) to a “hold” state. When theclock signal 320 turns “ON” the series switches, there will only be a single data transition, regardless of the previous data held by the RS latch (390 or 490). This ensures that the clock driver only sees a single data transition every clock cycle. Therefore, the clock driver is independent of the data signals 310 and 315, thereby reducing third order harmonic distortion. -
FIG. 5 shows exemplary waveforms associated with the digital control circuitry ofFIG. 3 a in accordance with an embodiment of the invention.Signal 510 represents the clock signal that controls the series switches 330 and 335, as well aspre-charge switches FIG. 3 a.Signals switches clock signal 510 is “low,” and thus in a pre-charge state. When the clock is “high,” the signal d (520) is forced onto Id (540) while the signal db (530) is forced onto Idb (550). Signals sw (560) and swb (570) are the complementary outputs of theNAND SR latch 390. When the signals Id (540) and Idb (550) are “high,” the data in the latch is held. When signal Id (540) is “high” while signal Idb (550) is “low,” the data is reset, forcing sw (560) to “low” and its complementary signal swb (570) to “high.” On the other hand, when signal Id (540) is “low” while signal Idb (550) is “high,” the data is set, forcing sw (560) to “high” and its complementary signal swb (570) to “low.” - One inherent benefit in using an SR latch configuration is that it reduces cross-over distortion. For example,
FIG. 6 a shows closer view of the complementary current switch configuration ofFIG. 3 a, as may be used in an embodiment of the invention. A linear sweep from “high” to “low” of signal sw at the gate ofswitch 360 and a proportional sweep of “low” to “high” of signal swb at the gate ofswitch 365, where both sw and swb signals are equal in magnitude at the cross-over point, may create a dead-band region, where bothswitches FIG. 6 b, the output of an SR latch inherently has a crossover which is about a threshold voltage above the common mode, CS, of the sw and swb signals. This high cross-over prevents dead-band, which assures smooth current transition from one switch to the other, forexample switch 360 to 365, thereby preventing crossover distortion. - Although the present invention has been described with reference to particular examples and embodiments, it is understood that the present invention is not limited to those examples and embodiments. The present invention as claimed, therefore, includes variations from the specific examples and embodiments described herein, as will be apparent to one of skill in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.
Claims (10)
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US12/108,996 US7619552B1 (en) | 2008-04-24 | 2008-04-24 | Low distortion current switch |
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US12/108,996 US7619552B1 (en) | 2008-04-24 | 2008-04-24 | Low distortion current switch |
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US12/108,996 Active US7619552B1 (en) | 2008-04-24 | 2008-04-24 | Low distortion current switch |
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