CN104882483A - Field effect transistor equipped with gamma-gate and recessed buffer layer and preparation method thereof - Google Patents
Field effect transistor equipped with gamma-gate and recessed buffer layer and preparation method thereof Download PDFInfo
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- CN104882483A CN104882483A CN201510223664.9A CN201510223664A CN104882483A CN 104882483 A CN104882483 A CN 104882483A CN 201510223664 A CN201510223664 A CN 201510223664A CN 104882483 A CN104882483 A CN 104882483A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention belongs to the technical field of field effect transistors and provides a field effect transistor equipped with a gamma-gate and a recessed buffer layer and a preparation method thereof, wherein the field effect transistor has a wide channel and a deep recess and is increased in output current and breakdown voltage and improved in frequency characteristic. An employed technical scheme is that a 4F-SiC semi-insulated substrate, a P-type buffer layer, an N-type channel layer are arranged from top to bottom; a source electrode cap layer and a drain electrode cap layer are arranged on both sides of the N-type channel layer respectively; the surface of the source electrode cap layer and the surface of the drain electrode cap layer are provided with a source electrode and a drain electrode respectively; a stepped gate electrode is disposed on a side, close to the source electrode cap layer, of the middle of the N-type channel layer; a left channel and a right channel are formed between both sides of the N-type channel layer and the gate electrode respectively; the low gate surface of the gate electrode is flush with the surface of the N-type channel layer; and a groove is disposed on the P-type buffer layer right under the low gate surface of the gate electrode.
Description
Technical field:
The invention belongs to field-effect transistor technical field, particularly relate to a kind of field-effect transistor and preparation method thereof with Γ grid and depression resilient coating.
Background technology:
SiC material has outstanding material such as broad-band gap, high breakdown electric field, high saturated electrons migration velocity, high heat conductance etc. and electrology characteristic, make it in high frequency high power device application, in the high frequency high power device application especially under the harsh environment such as high temperature, high pressure, space flight, satellite, there are very large potentiality.In SiC paramorph, the electron mobility of the 4H-SiC of the closely packed wurtzite structure of hexagonal is nearly three times of 6H-SiC, therefore 4H-SiC material is at high frequency high power device, especially occupies main status in metal-semiconductor field effect transistor (MESFET) application.
At present, most of document is devoted to the research of dual recess 4H-SiC MESFET structure and is improved on the basis of this structure.This structure is from bottom to up by 4H-SiC SI-substrate, P type resilient coating, N-type channel layer with N+ cap layers is stacking forms, based on this stack layer, the N-type channel layer of depression is formed after etching N+cap layers, the source half length of grid forms recessed grid structure to N-type channel layer sunken inside, and the N-type channel layer of depression completes by reactive ion etching RIE technology.
Although the puncture voltage of above-mentioned dual recess structure 4H-SiC MESFET increases to N-type channel layer sunken inside because of the source half length of grid, drain saturation current does not obtain substantive lifting.And in practical situations both, the process of reactive ion etching RIE can form lattice damage on surface, device drift region, cause charge carrier effective mobility in N-type channel layer to decline, and then reduce drain current, current output characteristics shows as the degeneration of saturation current.
Summary of the invention:
The present invention overcomes the deficiency that prior art exists, solve prior art Problems existing, aim to provide one there is wide raceway groove deeply to cave in and output current and puncture voltage can be improved, improve a kind of of frequency characteristic and there is field-effect transistor of Γ grid and depression resilient coating and preparation method thereof.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the field-effect transistor with Γ grid and depression resilient coating, be provided with 4H-SiC SI-substrate from top to bottom, P type resilient coating, N-type channel layer, the both sides of N-type channel layer are respectively arranged with source electrode cap layers and drain electrode cap layers, the surface of described source electrode cap layers and drain electrode cap layers is respectively arranged with source electrode and drain electrode, stair-stepping gate electrode is provided with in the middle part of N-type channel layer and near the side of source electrode cap layers, gate electrode and N-type channel layer both sides form left side raceway groove and right side channel, the low grid face of gate electrode is concordant with N-type channel layer surface, P type resilient coating immediately below the low grid face of gate electrode is provided with groove.
Further, described gate electrode is that two layers of ladder are made up of low grid and high grid, and the difference in height of described low grid and high grid is 0.05 μm.
Further, the length of P type resilient coating upper groove is 0.3 μm-0.4 μm, is highly 0.05 μm.
There is field-effect transistor of Γ grid and depression resilient coating and preparation method thereof, carry out according to following steps:
Step 1) 4H-SiC SI-substrate is cleaned, to remove substrate surface dirt;
Step 2) in the thick SiC layer of 4H-SiC SI-substrate Epitaxial growth 0.5 μm, simultaneously through diborane B
2h
6in-situ doped, forming concentration is 1.4 × 10
15cm
-3p type resilient coating;
Step 3) in the thick SiC layer of P type resilient coating Epitaxial growth 0.3 μm, simultaneously through N
2in-situ doped, forming concentration is 3 × 10
17cm
-3n-type channel layer;
Step 4) in the thick SiC layer of N-type channel layer Epitaxial growth 0.2 μm, simultaneously through N
2in-situ doped, forming concentration is 1.0 × 10
20cm
-3n
+type cap layers;
Step 5) at N
+type cap layers is carried out successively photoetching and isolation injection, form isolated area and active area;
Step 6) successively source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out to active area, form source electrode and the drain electrode of 0.5 μm long;
Step 7) to the N between source electrode and drain electrode
+type cap layers carries out twice photoetching, etching, and etch thicknesses is 0.2 μm for the first time, and formation etching depth and length are respectively the chase road of 0.2 μm and 2.2 μm; Second time etch thicknesses is 0.05 μm, etching length is with source electrode cap layers and drain electrode cap layers is inboard is respectively 0.85 μm and 1 μm for starting point, it is 0.85 μm that formation has length, and being highly that raceway groove depressed area, left side and the length of 0.05 μm is 1 μm, is highly 0.05 μm of right side channel depressed area;
Step 8) photoetching and ion implantation are carried out to N-type channel layer, it is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the depression resilient coating of 0.35 μm;
Step 9) above raceway groove and near the chase road of source electrode cap layers side, carry out photoetching, magnetron sputtering and metal-stripping, form the gate electrode of 0.7 μm long;
Step 10) formed 4H-SiC metal-semiconductor field effect transistor surface is carried out passivation, anti-carved, form electrode pad, complete the making of device.
Further, described step 7) in the preparation process of gate electrode be:
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting chase road photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, employing ICP sense coupling system carry out N
+etching, etching condition is etching power 375W, bias power 60W, operating pressure 9Pa, and etching gas selects flow to be the CF of 32sccm
4with the Ar of 8sccm, form length after etching and be 2.2 μm, be highly the recessed channel region of 0.2 μm, etch rear acetone and ultrasonic removal and etch and shelter glue.
D, repeat a, b, step c photoetching, to have length be 0.85 μm in etching formation, being highly that the raceway groove depressed area, left side of 0.05 μm is 1 μm with having length, is highly the right side channel depressed area of 0.05 μm;
Further, described step 8) preparation process of further groove is:
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting depression resilient coating photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, carry out boron ion implantation, injection condition is 300keV/2 × 10
12cm-2, temperature is 400 DEG C.With acetone and ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes; It is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the groove of 0.3 μm-0.4 μm;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of groove.
The present invention compared with prior art has following beneficial effect.
The first, drain current improves.4H-SiC MESFE device peak power output density is proportional to drain saturation current, puncture voltage and knee-point voltage.By raising the position of grid relative to channel surface, grid lower channels thickness is increased, and depletion region is reduced at raceway groove, and the raceway groove total electrical charge flowing through source-drain area can increase, and the channel thickness under grid has important impact to drain current, so the drain saturation current of this device is greatly improved.
The second, puncture voltage improves.MESFET device puncture the leakage lateral edges occurring in grid, and by raising the position of grid relative to channel surface, alleviating the leakage lateral edges electric field strength concentration phenomenon of grid, have adjusted the Electric Field Distribution of channel surface, puncture voltage is improved.
3rd, frequency characteristic is improved.By introducing groove, making the thickness of low grid lower channel constant, guaranteeing that leakage current effectively can be controlled by gate voltage, and stop depletion region to be expanded to source/drain regions, the depletion region under grid is diminished, thus make grid source, gate leakage capacitance minimizing.The grid source electric capacity reduced improves the frequency characteristic of MESFET device.
Accompanying drawing illustrates:
Below in conjunction with accompanying drawing, the present invention will be further described in detail
Fig. 1 is structural representation of the present invention.
In figure: 1 is 4H-SiC SI-substrate, 2 is P type resilient coating, and 3 is N-type channel layer, and 4 is source electrode cap layers, and 5 is drain electrode cap layers, and 6 is source electrode, and 7 is drain electrode, and 8 is left side raceway groove, and 9 is right side channel, and 10 is gate electrode, and 11 is groove.
Embodiment:
As shown in Figure 1, there is the field-effect transistor of Γ grid and depression resilient coating, be provided with 4H-SiC SI-substrate 1 from top to bottom, P type resilient coating 2, N-type channel layer 3, the both sides of N-type channel layer 3 are respectively arranged with source electrode cap layers 4 and drain electrode cap layers 5, the surface of described source electrode cap layers 4 and drain electrode cap layers 5 is respectively arranged with source electrode 6 and drain electrode 7, it is characterized in that: in the middle part of N-type channel layer 3 and near the side of source electrode cap layers 4, be provided with stair-stepping gate electrode 10, gate electrode 10 and N-type channel layer 3 both sides form left side raceway groove 8 and right side channel 9, the low grid face of gate electrode 10 is concordant with N-type channel layer 3 surface, P type resilient coating 2 immediately below the low grid face of gate electrode 10 is provided with groove 11.
Described gate electrode 10 is that two layers of ladder are made up of low grid and high grid, and the difference in height of described low grid and high grid is 0.05 μm.
The length of P type resilient coating 2 upper groove 11 is 0.3 μm-0.4 μm, is highly 0.05 μm.
Embodiment one
Prepare the field-effect transistor with Γ grid and depression resilient coating that the height of groove 11 and length are 0.05 μm and 0.35 μm.
Carry out according to following steps:
Step 1) 4H-SiC SI-substrate 1 is cleaned, to remove substrate surface dirt;
A, with the cotton balls being moistened with methyl alcohol, substrate is carefully cleaned two, three times, to remove the SiC particle of surperficial various sizes;
B, by 4H-SiC SI-substrate 1 at H
2sO
4: HNO
3in=1:1 ultrasonic 5 minutes;
C, by 4H-SiC SI-substrate 1 at 1# cleaning fluid (NaOH:H
2o
2: H
2o=1:2:5) boil 5 minutes in, then deionized water rinsing puts into 2# cleaning fluid (HCl:H again after 5 minutes
2o
2: H
2o=1:2:7) 5 minutes are boiled in, finally clean with deionized water rinsing and use N
2dry up for subsequent use.
Step 2) in the thick SiC layer of 4H-SiC SI-substrate 1 Epitaxial growth 0.5 μm, simultaneously through diborane B
2h
6in-situ doped, forming concentration is 1.4 × 10
15cm
-3p type resilient coating 2;
Specific operation process is: 4H-SiC SI-substrate 1 is put into growth room, in growth room, then passes into the high-purity hydrogen that flow is the silane of 20ml/min, the propane of 10ml/min and 80l/min, pass into the B of 2ml/min simultaneously
2h
6(H
2in be diluted to 5%), growth temperature is 1550 DEG C, and pressure is 10
5pa, lasting 6min, completes doping content and thickness is respectively 1.4 × 10
15cm
-3make with the P type resilient coating 2 of 0.4 μm-0.5 μm.
Step 3) in the thick SiC layer of P type resilient coating 2 Epitaxial growth 0.3 μm, simultaneously through N
2in-situ doped, forming concentration is 3 × 10
17cm
-3n-type channel layer 3;
Specific operation process is: 4H-SiC epitaxial wafer is put into growth room, passes into the high-purity hydrogen that flow is the silane of 20ml/min, the propane of 10ml/min and 80l/min, pass into the N of 2ml/min simultaneously in growth room
2, growth temperature is 1550 DEG C, and pressure is 10
5pa, lasting 3min, completes doping content and thickness is respectively 3 × 10
17cm
-3make with the N-type channel layer 3 of 0.3 μm.
Step 4) in the thick SiC layer of N-type channel layer 3 Epitaxial growth 0.2 μm, simultaneously through N
2in-situ doped, forming concentration is 1.0 × 10
20cm
-3n
+type cap layers;
Specific operation process is: 4H-SiC epitaxial wafer is put into growth room, passes into the high-purity hydrogen that flow is the silane of 20ml/min, the propane of 10ml/min and 80l/min, pass into the N of 20ml/min simultaneously in growth room
2, growth temperature is 1550 DEG C, and pressure is 10
5pa, continues 2min, and making doping content and thickness are respectively 1.0 × 10
20cm
-3with the N of 0.2 μm
+cap layers.
Step 5) at N
+type cap layers is carried out successively photoetching and isolation injection, form isolated area and active area;
Specific operation process is: a, employing positive photoresist, application rate: 3000R/min, and the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds at special developer solution after adopting isolation injection photolithography plate to carry out about 35 seconds uv-exposures, expose 4H-SiC, then dry 3 minutes after in 100 DEG C of baking ovens, the recipe ratio of described special developer solution is tetramethyl aqua ammonia: water=1:3;
C, carry out twice boron ion implantation, injection condition is 130keV/6 × 10
12cm
-2, 50keV/2 × 10
12cm
-2, injected rear acetone+ultrasonic depolymerization, then used the removing of photoresist by plasma 3 minutes, the isolation completed beyond active area is injected;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min.
Step 6) successively source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out to active area, form source electrode 6 and the drain electrode 7 of 0.5 μm long;
Specific operation process is: a, masking glue adopt PMMA+AZ1400 double-layer glue, require the thick > of glue 1.2 μm, PMMA glue is first coated with after slice, thin piece process is clean, speed is 4000R/min, thick about 0.5 μm of glue, then front baking 120 seconds in 200 DEG C of baking ovens, is coated with thick about 0.8 μm of AZ1400 glue again after taking-up;
B, in 90 DEG C of baking ovens front baking 90 seconds, after adopting source and drain photolithography plate to carry out 15 seconds uv-exposures, within 50 seconds, AZ1400 glue is removed with special developing liquid developing, then general exposure is carried out to PMMA glue, develop 3 minutes with toluene again, then dry 3 minutes after in 100 DEG C of baking ovens, complete source-drain area metallization window, the recipe ratio of described special developer solution is tetramethyl aqua ammonia: water=1:4;
C, adopt multi-target magnetic control sputtering platform, successively room temperature sputtering thickness be the Au multiple layer metal of Ti and 300nm of Ni, 150nm of 150nm as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10
-3pa, Ar flow 40sccm;
D, sputtered after slice, thin piece is put into 150 DEG C of special strippers of Buty, move in 130 DEG C of Buty strippers after metal comes off again, when equitemperature drops to below 80 DEG C, then slice, thin piece is moved in acetone, take out slice, thin piece and dry up with nitrogen, the last removing of photoresist by plasma 2 minutes;
E, slice, thin piece is put into rapid alloying stove, at nitrogen nitrogen atmosphere (N
2: H
2=9:1) be rapidly heated (970/1min) to alloy temperature alloy 10 minutes under protection, form source electrode 6 and drain electrode 7.
Step 7) to the N between source electrode 6 and drain electrode 7
+type cap layers carries out twice photoetching, etching, and etch thicknesses is 0.2 μm for the first time, and formation etching depth and length are respectively the chase road of 0.2 μm and 2.2 μm; Second time etch thicknesses is 0.05 μm, etching length with source electrode cap layers 4 and drain electrode cap layers 5 inboard for starting point is respectively 0.85 μm and 1 μm, it is 0.85 μm that formation has length, and being highly that left side raceway groove 8 depressed area and the length of 0.05 μm is 1 μm, is highly 0.05 μm of right side channel 9 depressed area;
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting chase road photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, employing ICP sense coupling system carry out N
+etching, etching condition is etching power 375W, bias power 60W, operating pressure 9Pa, and etching gas selects flow to be the CF of 32sccm
4with the Ar of 8sccm, form length after etching and be 2.2 μm, be highly the recessed channel region of 0.2 μm, etch rear acetone and ultrasonic removal and etch and shelter glue.
D, repeat a, b, step c photoetching, to have length be 0.85 μm in etching formation, being highly that left side raceway groove 8 depressed area of 0.05 μm is 1 μm with having length, is highly right side channel 9 depressed area of 0.05 μm
Step 8) photoetching and ion implantation are carried out to N-type channel layer (3), it is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers (4) for starting point, length is the depression resilient coating of 0.35 μm;
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting depression resilient coating photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, carry out boron ion implantation, injection condition is 300keV/2 × 10
12cm-2, temperature is 400 DEG C.With acetone and ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes; It is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the groove of 0.35 μm;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of groove 11.
Step 9) above raceway groove and near the chase road of source electrode cap layers 4 side, carry out photoetching, magnetron sputtering and metal-stripping, form the gate electrode 10 of 0.7 μm long;
Specific operation process is: a, masking glue adopt PMMA+AZ1400 double-layer glue, require the thick > of glue 1.2 μm.First be coated with PMMA glue after slice, thin piece process is clean, speed is 4000R/min, thick about 0.5 μm of glue, and then front baking 120 seconds in 200 DEG C of baking ovens, is coated with thick about 0.8 μm of AZ1400 glue again after taking-up;
B, in 90 DEG C of baking ovens front baking 90 seconds, develop with special developer solution (tetramethyl aqua ammonia: water=1:4) after adopting grid photolithography plate to carry out 15 seconds uv-exposures and remove AZ1400 glue in 50 seconds, then general exposure is carried out to PMMA glue, develop 3 minutes with toluene again, dry 3 minutes after then in 100 DEG C of baking ovens;
C, adopt multi-target magnetic control sputtering platform, successively room temperature sputtering thickness be the Au multiple layer metal of Ti and 300nm of Ni, 150nm of 150nm as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10
-3pa, Ar flow 40sccm, is heated to 150 DEG C by slice, thin piece in sputter procedure;
D, sputtered after slice, thin piece is put into 150 DEG C of special strippers of Buty, move in 130 DEG C of Buty strippers after metal comes off again, when equitemperature drops to below 80 DEG C, again slice, thin piece is moved in acetone, finally take out slice, thin piece and slowly dry up with low discharge nitrogen, finally use the removing of photoresist by plasma 3 minutes, complete the making of gate electrode 10.
Step 10) formed field effect transistor tube-surface is carried out passivation, anti-carved, form electrode pad, complete the making of device.
Specific operation process is: a, at 300 DEG C, pass into the SiH that flow is 300sccm in reative cell simultaneously
4, 323sccm NH
3with the N of 330sccm
2, by plasma enhanced CVD technique, at the Si that surface deposition 0.5 μm is thick
3n
4layer is as passivation dielectric layer;
B, passivation photoetching adopt positive photoresist, application rate 3000R/mins, require the thick > of glue 2 μm, after gluing completes in 90 DEG C of baking ovens front baking 90 seconds, then adopt and anti-carve photolithography plate and carry out 35 seconds uv-exposures, with special developing liquid developing 60 seconds, dry 3 minutes after finally in 100 DEG C of baking ovens, the recipe ratio of special developer solution was tetramethyl aqua ammonia: water=1:3;
C, Si
3n
4etching adopts RIE technique, and etching gas selects flow to be 50sccm CHF
3be 5sccm Ar with flow, carry out 3 minutes removing of photoresist by plasmas again after completing, expose metal, form source, leakage and gate electrode 6,7,10 pressure welding point, complete the making of whole device.
Embodiment two
Prepare the field-effect transistor with Γ grid and depression resilient coating that the height of groove and length are 0.05 μm and 0.3 μm.The difference of the present embodiment and embodiment one is step 8)
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting depression resilient coating photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, carry out boron ion implantation, injection condition is 300keV/2 × 10
12cm-2, temperature is 400 DEG C.With acetone and ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes; It is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the groove of 0.3 μm;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of groove 11.
Embodiment three
Prepare the field-effect transistor with Γ grid and depression resilient coating that the height of groove and length are 0.05 μm and 0.4 μm.The difference of the present embodiment and embodiment one is step 8)
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting depression resilient coating photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, carry out boron ion implantation, injection condition is 300keV/2 × 10
12cm-2, temperature is 400 DEG C.With acetone and ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes; It is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the groove of 0.4 μm;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of groove 11.
Described in summary, 4H-SiC metal-semiconductor field effect transistor of the present invention have that drain current and puncture voltage improve, the improved effect of frequency characteristic.
Above content combines embodiment accompanying drawing and has made detailed description to specific embodiments of the invention.In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
By reference to the accompanying drawings embodiments of the invention are explained in detail above, but the present invention is not limited to above-described embodiment, in the ken that those of ordinary skill in the art possess, various change can also be made under the prerequisite not departing from present inventive concept.
Claims (6)
1. there is the field-effect transistor of Γ grid and depression resilient coating, be provided with 4H-SiC SI-substrate (1) from top to bottom, P type resilient coating (2), N-type channel layer (3), the both sides of N-type channel layer (3) are respectively arranged with source electrode cap layers (4) and drain electrode cap layers (5), the surface of described source electrode cap layers (4) and drain electrode cap layers (5) is respectively arranged with source electrode (6) and drain electrode (7), it is characterized in that: in the middle part of N-type channel layer (3) and near the side of source electrode cap layers (4), be provided with stair-stepping gate electrode (10), gate electrode (10) and N-type channel layer (3) both sides form left side raceway groove (8) and right side channel (9), the low grid face of gate electrode (10) is concordant with N-type channel layer (3) surface, P type resilient coating (2) immediately below the low grid face of gate electrode (10) is provided with groove (11).
2. the field-effect transistor with Γ grid and depression resilient coating according to claim 1, is characterized in that: described gate electrode (10) is that two layers of ladder are made up of low grid and high grid, and the difference in height of described low grid and high grid is 0.05 μm.
3. the field-effect transistor with Γ grid and depression resilient coating according to claim 2, is characterized in that: the length of P type resilient coating (2) upper groove (11) is 0.35 μm, is highly 0.05 μm.
4. according to claim 3 have field-effect transistor of Γ grid and depression resilient coating and preparation method thereof, it is characterized in that: carry out according to following steps:
Step 1) 4H-SiC SI-substrate (1) is cleaned, to remove substrate surface dirt;
Step 2) in the thick SiC layer of 4H-SiC SI-substrate (1) Epitaxial growth 0.5 μm, simultaneously through diborane B
2h
6in-situ doped, forming concentration is 1.4 × 10
15cm
-3p type resilient coating (2);
Step 3) in the thick SiC layer of P type resilient coating (2) Epitaxial growth 0.3 μm, simultaneously through N
2in-situ doped, forming concentration is 3 × 10
17cm
-3n-type channel layer (3);
Step 4) in the thick SiC layer of N-type channel layer (3) Epitaxial growth 0.2 μm, simultaneously through N
2in-situ doped, forming concentration is 1.0 × 10
20cm
-3n
+type cap layers;
Step 5) at N
+type cap layers is carried out successively photoetching and isolation injection, form isolated area and active area;
Step 6) successively source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out to active area, form source electrode (6) and the drain electrode (7) of 0.5 μm long;
Step 7) to the N between source electrode (6) and drain electrode (7)
+type cap layers carries out twice photoetching, etching, and etch thicknesses is 0.2 μm for the first time, and formation etching depth and length are respectively the chase road of 0.2 μm and 2.2 μm; Second time etch thicknesses is 0.05 μm, etching length is respectively 0.85 μm and 1 μm with source electrode cap layers (4) and drain electrode cap layers (5) inboard for starting point, it is 0.85 μm that formation has length, be highly left side raceway groove (8) depressed area and the length of 0.05 μm being 1 μm, is highly 0.05 μm of right side channel (9) depressed area;
Step 8) photoetching and ion implantation are carried out to N-type channel layer (3), it is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers (4) for starting point, length is the depression resilient coating of 0.35 μm;
Step 9) above raceway groove and near the chase road of source electrode cap layers (4) side, carry out photoetching, magnetron sputtering and metal-stripping, form the gate electrode (10) of 0.7 μm long;
Step 10) formed 4H-SiC metal-semiconductor field effect transistor surface is carried out passivation, anti-carved, form electrode pad, complete the making of device.
5. field-effect transistor and preparation method thereof with Γ grid and depression resilient coating according to claim 4, is characterized in that: described step 7) in the preparation process of gate electrode be:
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting chase road photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, employing ICP sense coupling system carry out N
+etching, etching condition is etching power 375W, bias power 60W, operating pressure 9Pa, and etching gas selects flow to be the CF of 32sccm
4with the Ar of 8sccm, form length after etching and be 2.2 μm, be highly the recessed channel region of 0.2 μm, etch rear acetone and ultrasonic removal and etch and shelter glue;
D, repeat a, b, step c photoetching, to have length be 0.85 μm in etching formation, being highly that left side raceway groove (8) depressed area of 0.05 μm is 1 μm with having length, is highly right side channel (9) depressed area of 0.05 μm.
6. field-effect transistor and preparation method thereof with Γ grid and depression resilient coating according to claim 4, is characterized in that: described step 8) preparation process of further groove (11) is:
A, employing positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
After b, gluing complete in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution after adopting depression resilient coating photolithography plate to carry out about 35 seconds uv-exposures, the formula of special developer solution: tetramethyl aqua ammonia: water=1:3, dries 3 minutes after then in 100 DEG C of baking ovens;
C, carry out boron ion implantation, injection condition is 300keV/2 × 10
12cm-2, temperature is 400 DEG C, has injected rear acetone and ultrasonic depolymerization, then uses the removing of photoresist by plasma 3 minutes; It is 0.05 μm that formation has thickness, and with the inboard 0.5 μm of place of source electrode cap layers for starting point, length is the groove (11) of 0.3 μm-0.4 μm;
D, above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of groove (11).
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