CN104867901A - Substrate structure and semiconductor package - Google Patents
Substrate structure and semiconductor package Download PDFInfo
- Publication number
- CN104867901A CN104867901A CN201410089087.4A CN201410089087A CN104867901A CN 104867901 A CN104867901 A CN 104867901A CN 201410089087 A CN201410089087 A CN 201410089087A CN 104867901 A CN104867901 A CN 104867901A
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- CN
- China
- Prior art keywords
- circuit
- line
- substrate body
- semiconductor package
- isolation structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 239000011469 building brick Substances 0.000 claims description 17
- 230000000994 depressogenic effect Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 description 10
- 238000003466 welding Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
A substrate structure and a semiconductor package are provided, the substrate structure includes: a substrate body having opposing first and second surfaces; the first circuit and the second circuit are respectively formed on the first surface of the substrate body and are adjacent to each other, and the first circuit and the second circuit are respectively provided with a top surface for electrically connecting an external component; and an isolation structure formed on the first surface of the substrate body and located between the first and second circuits, so as to electrically isolate the first and second circuits by the isolation structure. Therefore, the invention can avoid the situation that two adjacent lines are mutually electrically connected to generate short circuit.
Description
Technical field
The present invention relates to a kind of board structure and semiconductor package part, refer to a kind of board structure and the semiconductor package part that adopt the projection wire of Flip-Chip Using direct-connected (BOT) technology especially.
Background technology
Because the design of electronic product is more and more advanced towards the trend of compact, multi-functional and high-frequency work usefulness, therefore circuit board or base plate for packaging also must/fine rule wide toward fine rule apart from the future development of (fineline/fine pitch).Meanwhile, because the pin count of flip-chip type semiconductor packaging part is much larger than the pin count of routing type semiconductor package part, so replace routing type semiconductor package part with flip-chip type semiconductor packaging part gradually now.
Fig. 1 is the schematic top plan view of the Flip-Chip package substrate illustrating prior art.As shown in the figure, base plate for packaging 1 comprises substrate body 10, many circuits 11 and a welding resisting layer 12.Those circuits 11 are formed in this substrate body 10, and the electrical contact 111 respectively with the end being formed at this circuit 11 puts outside electronic building brick (as semiconductor chip) for connecing, the surface that this welding resisting layer 12 is formed at this substrate body 10 exposes outside those electrical contacts 111 with those circuits 11 coated.
Because those electrical contacts 111 are positioned at the end of those circuits 11, and the size of those electrical contacts 111 is greater than the size of those circuits 11, therefore the wiring density of those circuits 11 be often limited to those electrical contacts 111 size and cannot make fine rule wide/product of fine rule distance, therefore when this base plate for packaging 1 has fixed-area, the wiring density of those circuits 11 cannot promote, and thus causes the usefulness of follow-up made semiconductor package part limited.In order to solve those problems, industry develops the direct-connected (bump-on-trace of a kind of employing projection wire then; BOT) the Flip-Chip package substrate of technology, as shown in Figure 2.
Fig. 2 is the schematic perspective view of another Flip-Chip package substrate illustrating prior art.As shown in the figure, base plate for packaging 2 comprises substrate body 20, many circuits 21 and multiple soldered ball 22.Those circuits 21 are formed in this substrate body 20, and this circuit 21 has end face 211 and at least one electrical contact 212 be positioned on this end face 211, and this soldered ball 22 is formed on the electrical contact 212 of this end face 211.End due to those circuits 21 can arrange electrical contact 111 as shown in Figure 1, therefore the wiring density of those circuits 21 is compared with the restriction of size that can not be subject to electrical contact, also can increase the magnitude setting of the soldered ball 22 on those circuits 21.
But, when for forming semiconductor chip and primer to make semiconductor package part on this base plate for packaging 2, and when reliability test is carried out to this semiconductor package part, then may make the situation producing short circuit between two adjacent circuits 21, as shown in Fig. 3 A and Fig. 3 B.
Fig. 3 A and Fig. 3 B is the cross-sectional schematic of the flip-chip type semiconductor packaging part illustrating prior art.
As shown in Figure 3A, semiconductor package part 3 comprises substrate body 31, adjacent two circuits 32, conductive projection 33, semiconductor chip 34 and primer 35.This two circuit 32 is formed in this substrate body 31, and this conductive projection 33 is formed between the end face 321 of this circuit 32 and the electronic pads 341 of this semiconductor chip 34, and this primer 35 is formed between this substrate body 31 and this semiconductor chip 34.
Because this substrate body 31 is not formed with welding resisting layer 12 as shown in Figure 1, and it is also non-very smooth on the surface of this substrate body 31, add that the spacing of this two circuit 32 is usually very little, primer 35 between this two circuit 32 cannot be sealed in this substrate body 31 completely, cause being formed with gap (gap) 351 between this two circuit 32.
As shown in Figure 3 B, when carrying out such as reliability test to this semiconductor package part 3, because the electric current put on this semiconductor package part 3 can produce heat energy by this two circuit 32, and this heat energy is understood the electric conducting material (as copper material) 352 of this two circuit (as copper cash) 32 of melt portions and overflows, and make the electric conducting material 352 of this spilling be formed at this gap 351, thus cause this two circuit 32 be electrically connected mutually and produce the situation of short circuit.
Therefore, how to overcome the problem of above-mentioned prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
Object of the present invention is for providing a kind of board structure and semiconductor package part, and it adopts the projection wire of Flip-Chip Using direct-connected (BOT) technology, and two adjacent circuits can be avoided to be electrically connected mutually and to produce the situation of short circuit.
The invention provides a kind of board structure, it comprises: substrate body, and it has relative first surface and second surface; Be formed at the adjacent first line on the first surface of this substrate body and the second circuit respectively, and this first line all has the electron-donating end face being connected external module with this second circuit; And isolation structures, it is formed on the first surface of this substrate body, and between this first line and this second circuit, with this isolation structures of mat this first line electrically isolated and this second circuit.
The present invention also provides a kind of semiconductor package part, and it comprises: substrate body, and it has relative first surface and second surface; Be formed at the adjacent first line on the first surface of this substrate body and the second circuit respectively, and this first line and this second circuit all has end face; Isolation structures, it is formed on the first surface of this substrate body, and between this first line and this second circuit, with this isolation structures of mat this first line electrically isolated and this second circuit; At least one first conductive projection, it is formed on the end face of this first line; At least one second conductive projection, it is formed on the end face of this second circuit; And electronic building brick, it is located on this first conductive projection and this second conductive projection to be electrically connected this first line and this second circuit respectively by this first conductive projection and this second conductive projection.
In above-mentioned board structure and semiconductor package part, this isolation structures can be made up of at least one protuberance, and this protuberance and this substrate body are one of the forming or are formed separately.The material of this protuberance can be insulating material, and the height of this protuberance can be less than the height of this first line or the height of this second circuit.
In above-mentioned board structure and semiconductor package part, this isolation structures can be made up of at least one depressed part, and this depressed part extends to the inside of this substrate body from the first surface of this substrate body.
In above-mentioned semiconductor package part, this electronic building brick can be semiconductor chip or wafer, and connects on the end face of end face and this second circuit being placed in this first line with flip chip.
In above-mentioned semiconductor package part, this electronic building brick can have acting surface and the first electronic pads and the second electronic pads that are formed at this acting surface respectively, this first conductive projection can be formed between the end face of this first line and this first electronic pads, and this second conductive projection can be formed between the end face of this second circuit and this second electronic pads.
Above-mentioned semiconductor package part can comprise primer, it is formed between the first surface of this substrate body and this electronic building brick, with this first line coated, the second circuit, isolation structures, the first conductive projection and the second conductive projection, and this primer can this isolation structures coated protuberance or be filled in the depressed part of this isolation structures.
As from the foregoing, in board structure of the present invention and semiconductor package part, projection wire direct-connected (BOT) technology of main employing Flip-Chip Using, and form conductive projection respectively on the end face of two adjacent circuits, and formation has the isolation structures of protuberance or depressed part between this two circuit.
Therefore, compared to prior art Fig. 1, board structure of the present invention can omit the welding resisting layer shown in Fig. 1, use make fine rule wide/board structure of fine rule distance, and reduce processing procedure and the cost of this board structure, and increase the magnitude setting of the conductive projection on this circuit.
In addition, compared to prior art Fig. 2 to Fig. 3 B, semiconductor package part of the present invention is after this electronic building brick of formation and this primer, and when carrying out the operations such as such as reliability test, this isolation structures can between this two circuit, and to reach in the electric conducting material that the gap of this primer and this substrate body is overflowed this two circuit and separate or shunting effect, therefore circuit of the present invention can not be electrically connected mutually and produces the situation of short circuit by the circuit as prior art Fig. 3 B.
Accompanying drawing explanation
Fig. 1 is the schematic top plan view of the Flip-Chip package substrate illustrating prior art;
Fig. 2 is the schematic perspective view of another Flip-Chip package substrate illustrating prior art;
Fig. 3 A and Fig. 3 B is the cross-sectional schematic of the flip-chip type semiconductor packaging part illustrating prior art;
Fig. 4 A is the cross-sectional schematic of the first embodiment illustrating board structure of the present invention;
Fig. 4 B is the cross-sectional schematic illustrating the first embodiment of semiconductor package part of the present invention according to the board structure of Fig. 4 A;
Fig. 5 A is the cross-sectional schematic of the second embodiment illustrating board structure of the present invention; And
Fig. 5 B is the cross-sectional schematic illustrating the second embodiment of semiconductor package part of the present invention according to the board structure of Fig. 5 A.
Symbol description
1,2 base plate for packaging
10,20,31,41 substrate body
11,21,32 circuits
111,212 electrical contacts
12 welding resisting layers
211,321,421,431 end faces
22 soldered balls
3,40,40' semiconductor package part
33 conductive projections
34 semiconductor chips
341 electronic padses
35,48 primers
351 gaps
352 electric conducting materials
4,4' board structure
411 first surfaces
412 second surfaces
42 first line
43 second circuits
44,44' isolation structures
441 protuberances
442 depressed parts
45 electronic building bricks
450 acting surfaces
451 first electronic padses
452 second electronic padses
46 first conductive projections
47 second conductive projections
H1, H2, H3 height.
Embodiment
Below by way of particular specific embodiment, embodiments of the present invention are described, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, for understanding and the reading of those skilled in the art, and be not used to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.
Simultaneously, quote in this specification as " on ", " one ", " first ", " second ", the term such as " surface " and " acting surface ", be also only be convenient to describe understand, and be not used to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 4 A is the cross-sectional schematic of the first embodiment illustrating board structure of the present invention.As shown in the figure, board structure 4 comprises substrate body 41, adjacent first line 42 and the second circuit 43 and isolation structures 44.
This substrate body 41 has relative first surface 411 and second surface 412.This first line 42 is formed on the first surface 411 of this substrate body 41 respectively with this second circuit 43, and this first line 42 and this second circuit 43 can have the electron-donating end face 421 and the end face 431 that are connected external module (as soldered ball or conductive projection) respectively.
This isolation structures 44 is formed on the first surface 411 of this substrate body 41, and between this first line 42 and this second circuit 43, with this isolation structures 44 of mat this first line 42 electrically isolated and this second circuit 43.
This isolation structures 44 is made up of at least one protuberance 441, and the material of this protuberance 441 can be insulating material.This protuberance 441 can be one of the forming or be formed separately with this substrate body 41, and can be identical material or unlike material.
The height H 1 of this protuberance 441 is less than the height H 2 of this first line 42 or the height H 3 of this second circuit 43.But in other embodiments, the height H 1 of this protuberance 441 also can be equal to or greater than the height H 2 of this first line 42 or the height H 3 of this second circuit 43.
In addition, the magnitude setting of this protuberance 441, width or length also can be adjusted according to the spacing of this first line 42 and this second circuit 43, width or length.
Fig. 4 B is the cross-sectional schematic illustrating the first embodiment of semiconductor package part of the present invention according to the board structure of Fig. 4 A.As shown in the figure, semiconductor package part 40 comprises substrate body 41, adjacent first line 42 and the second circuit 43, isolation structures 44, electronic building brick 45, at least one first conductive projection 46 and at least one second conductive projection 47.
This substrate body 41 has relative first surface 411 and second surface 412.This first line 42 is formed on the first surface 411 of this substrate body 41 respectively with this second circuit 43, and this first line 42 can have end face 421 and end face 431 respectively with this second circuit 43.
This isolation structures 44 is formed on the first surface 411 of this substrate body 41, and between this first line 42 and this second circuit 43, with this isolation structures 44 of mat this first line 42 electrically isolated and this second circuit 43.
This isolation structures 44 is made up of at least one protuberance 441, and the material of this protuberance 441 can be insulating material.This protuberance 441 can be one of the forming or be formed separately with substrate body 41, and is identical material or unlike material.
The height H 1 of this protuberance 441 is less than the height H 2 of this first line 42 or the height H 3 of this second circuit 43.But in other embodiments, the height H 1 of this protuberance 441 also can be equal to or greater than the height H 2 of this first line 42 or the height H 3 of this second circuit 43.
This first conductive projection 46 is formed on the end face 421 of this first line 42, and this second conductive projection 47 is formed on the end face 431 of this second circuit 43.This first conductive projection 46 or this second conductive projection 47 can be soldered ball, solder or metal column etc.
This electronic building brick 45 is located at this first conductive projection 46 with on this second conductive projection 47, to be electrically connected this first line 42 and this second circuit 43 respectively by this first conductive projection 46 and this second conductive projection 47.
This electronic building brick 45 can be semiconductor chip or wafer etc., and connects with flip chip and be placed on the end face 421 of this first line 42 and the end face 431 of this second circuit 43.Specifically, this electronic building brick 45 can have acting surface 450 and the first electronic pads 451 and the second electronic pads 452 being formed at this acting surface 450 respectively, this first conductive projection 46 is formed between the end face 421 of this first line 42 and this first electronic pads 451, and this second conductive projection 47 is formed between the end face 431 of this second circuit 43 and this second electronic pads 452.
This semiconductor package part 40 can comprise primer 48, it is formed between the first surface 411 of this substrate body 41 and the acting surface 450 of this electronic building brick 45, with protuberance 441, first conductive projection 46 of this first line 42, second circuit 43 coated, isolation structures 44 and the second conductive projection 47.
Fig. 5 A is the cross-sectional schematic of the second embodiment illustrating board structure of the present invention.The board structure 4' of Fig. 5 A is approximately identical to the board structure 4 of above-mentioned Fig. 4 A, and its Main Differences is as follows:
In fig. 5, this isolation structures 44' can be made up of at least one depressed part 442, and this depressed part 442 extends to the inside of this substrate body 41 from the first surface 411 of this substrate body 41.
In addition, the magnitude setting of this depressed part 442, the degree of depth, width or length also can according to the spacing of this first line 42 and this second circuit 43, highly, width or length and adjusted.
Fig. 5 B is the cross-sectional schematic illustrating the second embodiment of semiconductor package part of the present invention according to the board structure of Fig. 5 A.The semiconductor package part 40' of Fig. 5 B is approximately identical to the semiconductor package part 40 of above-mentioned Fig. 4 B, and its Main Differences is as follows:
In figure 5b, this isolation structures 44' can be made up of at least one depressed part 442, and this depressed part 442 extends to the inside of this substrate body 41 from the first surface 411 of this substrate body 41.Meanwhile, this primer 48 can be filled in the depressed part 442 of this isolation structures 44'.
As from the foregoing, in board structure of the present invention and semiconductor package part, projection wire direct-connected (BOT) technology of main employing Flip-Chip Using, and form conductive projection respectively on the end face of two adjacent circuits, and formation has the isolation structures of protuberance or depressed part between this two circuit.
Therefore, compared to prior art Fig. 1, board structure of the present invention can omit the welding resisting layer shown in Fig. 1, use make fine rule wide/board structure of fine rule distance, and reduce processing procedure and the cost of this board structure, and increase the magnitude setting of the conductive projection on this circuit.
In addition, compared to prior art Fig. 2 to Fig. 3 B, semiconductor package part of the present invention is after this electronic building brick of formation and this primer, and when carrying out the operations such as such as reliability test, this isolation structures can between this two circuit, and to reach in the electric conducting material that the gap of this primer and this substrate body is overflowed this two circuit and separate or shunting effect, therefore circuit of the present invention can not be electrically connected mutually and produces the situation of short circuit by the circuit as prior art Fig. 3 B.
Above-described embodiment only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore, the scope of the present invention should listed by claims.
Claims (14)
1. a board structure, it comprises:
Substrate body, it has relative first surface and second surface;
Be formed at the adjacent first line on the first surface of this substrate body and the second circuit respectively, and this first line all has the electron-donating end face being connected external module with this second circuit; And
Isolation structures, it is formed on the first surface of this substrate body, and between this first line and this second circuit, with this isolation structures of mat this first line electrically isolated and this second circuit.
2. board structure as claimed in claim 1, it is characterized in that, this isolation structures is made up of at least one protuberance, and this protuberance and this substrate body are one of the forming or are formed separately.
3. board structure as claimed in claim 2, it is characterized in that, the material of this protuberance is insulating material.
4. board structure as claimed in claim 2, it is characterized in that, the height of this protuberance is less than the height of this first line or the height of this second circuit.
5. board structure as claimed in claim 1, it is characterized in that, this isolation structures is made up of at least one depressed part, and this depressed part extends to the inside of this substrate body from the first surface of this substrate body.
6. a semiconductor package part, it comprises:
Substrate body, it has relative first surface and second surface;
Be formed at the adjacent first line on the first surface of this substrate body and the second circuit respectively, and this first line and this second circuit all has end face;
Isolation structures, it is formed on the first surface of this substrate body, and between this first line and this second circuit, with this isolation structures of mat this first line electrically isolated and this second circuit;
At least one first conductive projection, it is formed on the end face of this first line;
At least one second conductive projection, it is formed on the end face of this second circuit; And
Electronic building brick, it is located on this first conductive projection and this second conductive projection, is electrically connected this first line and this second circuit respectively by this first conductive projection and this second conductive projection.
7. semiconductor package part as claimed in claim 6, it is characterized in that, this isolation structures is made up of at least one protuberance, and this protuberance and this substrate body are one of the forming or are formed separately.
8. semiconductor package part as claimed in claim 7, it is characterized in that, the material of this protuberance is insulating material.
9. semiconductor package part as claimed in claim 7, it is characterized in that, the height of this protuberance is less than the height of this first line or the height of this second circuit.
10. semiconductor package part as claimed in claim 6, it is characterized in that, this isolation structures is made up of at least one depressed part, and this depressed part extends to the inside of this substrate body from the first surface of this substrate body.
11. semiconductor package parts as claimed in claim 6, it is characterized in that, this electronic building brick is semiconductor chip or wafer, and connects on the end face of end face and this second circuit being placed in this first line with flip chip.
12. semiconductor package parts as claimed in claim 6, it is characterized in that, this electronic building brick has acting surface and the first electronic pads and the second electronic pads that are formed at this acting surface respectively, this first conductive projection is formed between the end face of this first line and this first electronic pads, and this second conductive projection is formed between the end face of this second circuit and this second electronic pads.
13. semiconductor package parts as claimed in claim 6, it is characterized in that, this semiconductor package part also comprises primer, it is formed between the first surface of this substrate body and this electronic building brick, with this first line coated, the second circuit, isolation structures, the first conductive projection and the second conductive projection.
14. semiconductor package parts as claimed in claim 13, is characterized in that, the protuberance of this primer this isolation structures coated or be filled in the depressed part of this isolation structures.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103106216A TWI528518B (en) | 2014-02-25 | 2014-02-25 | Substrate structure and semiconductor package |
| TW103106216 | 2014-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104867901A true CN104867901A (en) | 2015-08-26 |
Family
ID=53913636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410089087.4A Pending CN104867901A (en) | 2014-02-25 | 2014-03-12 | Substrate structure and semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104867901A (en) |
| TW (1) | TWI528518B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477554A (en) * | 2020-04-23 | 2020-07-31 | 苏州英嘉通半导体有限公司 | Chip flip packaging intermediate structure and flip packaging method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200427026A (en) * | 2003-05-28 | 2004-12-01 | Via Tech Inc | Flip-chip package substrate and process thereof |
| TWI242818B (en) * | 2004-12-10 | 2005-11-01 | Advanced Semiconductor Eng | Process of mounting a passive component |
| TWI292296B (en) * | 2006-01-27 | 2008-01-01 | Au Optronics Corp | The fpc having next door to pads can prevent a short circuit |
| CN103094232A (en) * | 2011-11-02 | 2013-05-08 | 南茂科技股份有限公司 | Chip packaging structure |
| CN103515345A (en) * | 2012-06-19 | 2014-01-15 | 矽品精密工业股份有限公司 | Substrate structure and packaging structure |
-
2014
- 2014-02-25 TW TW103106216A patent/TWI528518B/en active
- 2014-03-12 CN CN201410089087.4A patent/CN104867901A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200427026A (en) * | 2003-05-28 | 2004-12-01 | Via Tech Inc | Flip-chip package substrate and process thereof |
| TWI242818B (en) * | 2004-12-10 | 2005-11-01 | Advanced Semiconductor Eng | Process of mounting a passive component |
| TWI292296B (en) * | 2006-01-27 | 2008-01-01 | Au Optronics Corp | The fpc having next door to pads can prevent a short circuit |
| CN103094232A (en) * | 2011-11-02 | 2013-05-08 | 南茂科技股份有限公司 | Chip packaging structure |
| CN103515345A (en) * | 2012-06-19 | 2014-01-15 | 矽品精密工业股份有限公司 | Substrate structure and packaging structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477554A (en) * | 2020-04-23 | 2020-07-31 | 苏州英嘉通半导体有限公司 | Chip flip packaging intermediate structure and flip packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI528518B (en) | 2016-04-01 |
| TW201533876A (en) | 2015-09-01 |
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