CN104867866A - Interconnection process for reducing k value of porous low-k material - Google Patents
Interconnection process for reducing k value of porous low-k material Download PDFInfo
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- CN104867866A CN104867866A CN201510173995.6A CN201510173995A CN104867866A CN 104867866 A CN104867866 A CN 104867866A CN 201510173995 A CN201510173995 A CN 201510173995A CN 104867866 A CN104867866 A CN 104867866A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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Abstract
The invention provides an interconnection process for reducing a k value of a porous low-k material. A semiconductor device substrate comprises a first groove formed in a front segment of the interconnection process and filler metal in the first groove. The interconnection process comprises the steps of sequentially depositing a first barrier layer and a low-k material on the semiconductor device substrate; carrying out a first ultraviolet curing process on the deposited low-k material; forming a second groove in the low-k material, and etching the first barrier layer at the bottom part of the second groove; carrying out metal filling in the second groove, and then carrying out chemical mechanical grinding on the filled metal until the surface of the low-k material; carrying out a second ultraviolet curing process on the low-k material so as to form a porous low-k material; and depositing a second barrier layer at the surface of the porous low-k material and the surface of the filled metal. The interconnection process provided by the invention uses a supporting function of interconnection through holes, avoids shrinkage of the low-k material, improves the porosity, reduces the k value, and overcomes a problem that the k value is caused to be reduced because the low-k material shrinks seriously in a traditional process.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of interconnection process reducing the k value of porous low-k material.
Background technology
Along with the development of CMOS integrated circuit fabrication process and reducing of critical size, much new materials and process is applied in device fabrication, in order to improve device performance.Porous low k material can realize the dielectric constant (dielectric constant of air is 1, so porous material can obtain very low k value) of about 2.5, and the RC that effectively can reduce integrated circuit postpones.
The formation of current porous low k material (mainly BD2:Black Diamond 2) has divided two steps: thin film deposition and ultraviolet irradiation.Thin film deposition completes in PECVD reaction chamber, can pass into organic pore-foaming agent (ATRP) in this process.The initial film that deposition obtains not is porous, and a large amount of pore-foaming agents is contained in the inside.Subsequently in ultraviolet irradiation reaction chamber, pore-foaming agent is expelled from film under ultraviolet effect, and cross-linking reaction occurs in film inside simultaneously, forms porous.Organic pore-foaming agent is more thorough by what drive out of, is more conducive to the performance improving porous low k material.
Refer to Fig. 1, existing back segment interconnection process comprises:
Step L01: deposited barrier layer and low-k material successively in semiconductor device substrates; Here, after the first groove of front and continued interconnection process is formed and fills metal, at substrate surface deposited copper diffusion impervious layer, nitrogen doped silicon carbide (NDC) is generally, then at copper diffusion barrier layer surface deposition low-k material;
Step L02: carry out ultra-violet curing technique to low-k material, to form porous low-k material; Pore-foaming agent in this process in low-k material is driven out of and is formed porous, simultaneously film generation thickness contraction.
Step L03: through photoetching and etching technics, forms the second groove in porous low-k material, and etches away the barrier layer of the second channel bottom, to expose the filling metal in the first groove;
Step L04: carry out metal filled in the second groove, then carries out cmp to porous low-k material surface to filled metal; Thus in porous low k material, form copper interconnecting line (generally speaking using the final step of cmp as certain one deck metal connecting line of formation).The fill method of metal comprises copper plating etc.First groove and interior filling metal thereof and the second groove and interior filling metal thereof form through-hole interconnection;
Step L05: at porous low-k material surface and the metal surface deposited barrier layer of filling; Here, barrier layer is nitrogen doped silicon carbide.
But in above-mentioned ultra-violet curing technique (UV Cure) process, low-k film can shrink, general shrinkage is 10%-20% (namely thickness reduces 10%-20%).The object of ultra-violet curing forms the sparse film of porous, and to obtain the lower film of k value, but contraction is the process of a densification for material, thus causes k value to raise.
Therefore, in the UV curing process needing a kind of method to make, low-k material does not shrink, thus avoids the rising of k value.
Summary of the invention
In order to overcome above problem, the present invention aims to provide a kind of interconnection process reducing the k value of porous low-k material, and period repeatedly carries out ultra-violet curing technique to porous low-k material substep.
To achieve these goals, the invention provides the interconnection process of the k value reducing porous low-k material, the semiconductor device substrate completing leading portion interconnection process carries out, semiconductor device substrates comprises the first groove of leading portion interconnection process formation and interior filling metal thereof, and it comprises the following steps:
Step 01: deposit the first barrier layer and low-k material in described semiconductor device substrates successively;
Step 02: the first ultra-violet curing technique is carried out to deposited described low-k material;
Step 03: through photoetching and etching technics, forms the second groove in described low-k material, and described first barrier etch of described second channel bottom is fallen, to expose the filling metal in described first groove;
Step 04: carry out metal filled in described second groove, then carries out cmp to described low-k material surface to filled metal; Described first groove and interior filling metal thereof and described second groove and interior filling metal thereof form through-hole interconnection;
Step 05: carry out the second ultra-violet curing technique to described low-k material, to form porous low-k material;
Step 06: deposit the second barrier layer at described porous low-k material surface and the metal surface of filling.
Preferably, in described first ultra-violet curing technique, the curing temperature of employing is 300 ~ 400 DEG C.
Preferably, the time that described second ultra-violet curing technique adopts is 5 ~ 20% of described first ultra-violet curing process time and described second ultra-violet curing process time summation.
Preferably, the described first ultra-violet curing time is 100 ~ 1000S.
Preferably, in described second ultra-violet curing technique, the curing temperature of employing is 300 ~ 400 DEG C.
Preferably, the main reactant forming described low-k material comprises: methyldiethoxysilane and α-terpinenes.
Preferably, the reaction temperature forming the employing of described low-k material is 200 ~ 400 DEG C.
Preferably, also comprise in described step 04: adopt cmp to fall the described low-k material of part.
Preferably, the material on described first barrier layer or described second barrier layer is nitrogen doped silicon carbide.
Preferably, described first groove or described second trench wall surface deposition have diffusion impervious layer.
Interconnection process of the present invention, the first ultra-violet curing technique and the second ultra-violet curing technique is carried out respectively before and after being formed at through-hole interconnection, ultra-violet curing technique makes the k value of low-k material reduce and mechanical performance rising for the first time, in the second UV curing process, utilize the supporting role of through-hole interconnection, avoid low-k material undergoing shrinkage, improve porosity and reduce k value, overcoming the problem that in traditional handicraft, low-k material generation significant shrinkage causes k value to reduce.Here, the first ultra-violet curing technique is necessary, because if do not carry out the first ultra-violet curing technique, and directly carry out subsequent technique, the mechanical strength of low-k material is difficult to the requirement meeting subsequent technique.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of existing back segment interconnection process
Fig. 2 is the schematic flow sheet of the interconnection process of the k value of the reduction porous low-k material of a preferred embodiment of the present invention
Fig. 3 ~ 8 are each step schematic diagram of the interconnection process of the k value of the reduction porous low-k material of a preferred embodiment of the present invention
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
The present invention, by improving existing interconnection process, carries out first, second ultra-violet curing technique respectively, avoids the contraction that low-k material is serious in ultra-violet curing technique, reduce the k value of porous low-k material before and after through-hole interconnection is formed.
Below in conjunction with accompanying drawing 2 ~ 8 and specific embodiment, the interconnection process to the k value of reduction porous low-k material of the present invention is described in further detail.It should be noted that, accompanying drawing all adopt simplify very much form, use non-ratio accurately, and only in order to object that is convenient, that clearly reach aid illustration the present embodiment.
In the present embodiment, refer to Fig. 2, reduce the interconnection process of the k value of porous low-k material, semiconductor device substrate carries out, comprises the following steps:
Step 01: refer to Fig. 3, semiconductor device substrates deposits the first barrier layer 03 and low-k material 04 successively;
Concrete, semiconductor device substrates can be, but not limited to the substrate for completing after leading portion interconnection process; Semiconductor device substrates comprises the filling metal 02 that leading portion interconnection process forms porous low-k material 01, first groove and Qi Nei, also has diffusion impervious layer such as Ta/TaN at the first trench wall, fills metal 02 and is formed at diffusion impervious layer surface; Low-k material 04 in this step 01 is formed in PECVD reaction chamber, its reactant comprises methyldiethoxysilane (mDEOS) and α-terpinenes (ATRP), wherein, ATRP is perforating agent, reaction temperature is 200 ~ 400 DEG C, and the thickness of the low-k material deposited is 1000 ~ 5000A.It should be noted that, the semiconductor device substrates in the present invention can be any Semiconductor substrate, as long as the semiconductor device substrates of carrying out the interconnection process of porous low-k material all can be applied in the present invention.
Step 02: refer to Fig. 4, carries out the first ultra-violet curing technique to deposited low-k material 04;
Concrete, after the first ultra-violet curing technique, form low-k material 04 '; The curing temperature that first ultra-violet curing technique adopts is 300 ~ 400 DEG C, and curing time sets according to the thickness of low-k material, such as, be 100 ~ 1000S.The present invention will realize the higher porosity of low-k material and lower k value by the first ultra-violet curing technique, and higher mechanical strength, if the time of the first ultra-violet curing technique is too short, then can not reach this effect; Therefore, in some embodiments of the invention, be greater than the curing time of the second ultra-violet curing technique curing time of the first ultra-violet curing technique.In the present embodiment, the curing time of the first ultra-violet curing technique is 80% ~ 95% of the temporal summation of the first ultra-violet curing technique and the second ultra-violet curing technique.Like this, in the first ultra-violet curing technique in the present embodiment, low-k material still can produce contraction, but the shrinkage degree in the first ultra-violet curing technique is less than the shrinkage degree of once thoroughly being solidified by low-k material.First ultra-violet curing technique can comprise multiple UV curing process, such as, adopts different curing temperatures etc.
Step 03: refer to Fig. 5, through photoetching and etching technics, forms the second groove 05, and is etched away on the first barrier layer 03 bottom the second groove 05, to expose the filling metal 02 in the first groove in low-k material 04 ';
Concrete, first, through photoetching and etching formation second groove 05; Then, at inwall and the bottom deposit diffusion impervious layer such as Ta/TaN of the second groove 05 formed; Then, the first barrier layer 03 part of the second channel bottom is etched away; Concrete technique can adopt common process, and repeats no more here.
Step 04: refer to Fig. 6, carries out metal filled in the second groove 05, then carries out cmp to low-k material 04 ' surface to filled metal 06;
Concrete, copper electroplating technology plated metal copper in the second groove 05 can be adopted; Cmp is also adopted to fall part low-k material 04 ' in this step; In the present embodiment, after cmp, the thickness of low-k material 04 ' is 1200 ~ 1800A.Here, the first groove and interior filling metal thereof and the second groove and interior filling metal thereof form through-hole interconnection;
Step 05: refer to Fig. 7, carries out the second ultra-violet curing technique to low-k material 04 ', to form porous low-k material 04 ";
Concrete, in the second ultra-violet curing technique, the curing temperature of employing is 300 ~ 400 DEG C; Perforating agent in low-k material 04 ' is thoroughly discharged by the second ultra-violet curing technique, due to the existence of through-hole interconnection, plays a supporting role to low-k material, makes it not shrink; And pore-foaming agent is separated out and cross-linking reaction still can be carried out, and this means that low-k material will obtain higher porosity and lower k value.In the present embodiment, the time that the second ultra-violet curing technique adopts is 5 ~ 20% of the first ultra-violet curing process time and the second ultra-violet curing process time summation.Second ultra-violet curing technique can comprise multiple UV curing process, such as, can adopt different curing temperatures etc.
Step 06: refer to Fig. 8, at porous low-k material 04 " surperficial metal 06 surface deposition second barrier layer 07 with filling.
Concrete, the material on the second barrier layer 07 can be, but not limited to as nitrogen doped silicon carbide.
In sum, interconnection process of the present invention, the first ultra-violet curing technique and the second ultra-violet curing technique is carried out respectively before and after being formed at through-hole interconnection, ultra-violet curing technique makes the k value of low-k material reduce and mechanical performance rising for the first time, in the second UV curing process, utilize the supporting role of through-hole interconnection, avoid low-k material undergoing shrinkage, improve porosity and reduce k value, overcoming the problem that in traditional handicraft, low-k material generation significant shrinkage causes k value to reduce.Here, the first ultra-violet curing technique is necessary, because if do not carry out the first ultra-violet curing technique, and directly carry out subsequent technique, the mechanical strength of low-k material is difficult to the requirement meeting subsequent technique.
Although the present invention discloses as above with preferred embodiment; right described embodiment is citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. one kind is reduced the interconnection process of the K value of porous low-K material, the semiconductor device substrate completing leading portion interconnection process carries out, semiconductor device substrates comprises the first groove of described leading portion interconnection process formation and interior filling metal thereof, it is characterized in that, comprises the following steps:
Step 01: deposit the first barrier layer and low-k material in described semiconductor device substrates successively;
Step 02: the first ultra-violet curing technique is carried out to deposited described low-k material;
Step 03: through photoetching and etching technics, forms the second groove in described low-k material, and described first barrier etch of described second channel bottom is fallen, to expose the filling metal in described first groove;
Step 04: carry out metal filled in described second groove, then carries out cmp to described low-k material surface to filled metal; Described first groove and interior filling metal thereof and described second groove and interior filling metal thereof form through-hole interconnection;
Step 05: carry out the second ultra-violet curing technique to described low-k material, to form porous low-k material;
Step 06: deposit the second barrier layer at described porous low-k material surface and the metal surface of filling.
2. interconnection process according to claim 1, is characterized in that, in described first ultra-violet curing technique, the curing temperature of employing is 300 ~ 400 DEG C.
3. interconnection process according to claim 1, is characterized in that, the time that described second ultra-violet curing technique adopts is 5 ~ 20% of described first ultra-violet curing process time and described second ultra-violet curing process time summation.
4. interconnection process according to claim 1, is characterized in that, the described first ultra-violet curing time is 100 ~ 1000S.
5. interconnection process according to claim 1, is characterized in that, in described second ultra-violet curing technique, the curing temperature of employing is 300 ~ 400 DEG C.
6. interconnection process according to claim 1, is characterized in that, the main reactant forming described low-k material comprises: methyldiethoxysilane and α-terpinenes.
7. interconnection process according to claim 7, is characterized in that, the reaction temperature forming the employing of described low-k material is 200 ~ 400 DEG C.
8. interconnection process according to claim 1, is characterized in that, also comprises in described step 04: adopt cmp to fall the described low-k material of part.
9. interconnection process according to claim 1, is characterized in that, the material on described first barrier layer or described second barrier layer is nitrogen doped silicon carbide.
10. interconnection process according to claim 1, is characterized in that, described first groove or described second trench wall surface deposition have diffusion impervious layer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1775861A (en) * | 2004-09-07 | 2006-05-24 | 罗门哈斯电子材料有限公司 | Composition and method |
| CN1957108A (en) * | 2004-03-31 | 2007-05-02 | 应用材料公司 | Multi-stage curing method of low k nano-porous films |
| US20090280637A1 (en) * | 2008-05-07 | 2009-11-12 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device including ultra low dielectric constant layer |
| US20100301495A1 (en) * | 2009-05-27 | 2010-12-02 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
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- 2015-04-13 CN CN201510173995.6A patent/CN104867866B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1957108A (en) * | 2004-03-31 | 2007-05-02 | 应用材料公司 | Multi-stage curing method of low k nano-porous films |
| CN1775861A (en) * | 2004-09-07 | 2006-05-24 | 罗门哈斯电子材料有限公司 | Composition and method |
| US20090280637A1 (en) * | 2008-05-07 | 2009-11-12 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device including ultra low dielectric constant layer |
| US20100301495A1 (en) * | 2009-05-27 | 2010-12-02 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
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