CN104865517B - Detect debug circuit - Google Patents
Detect debug circuit Download PDFInfo
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- CN104865517B CN104865517B CN201510324183.7A CN201510324183A CN104865517B CN 104865517 B CN104865517 B CN 104865517B CN 201510324183 A CN201510324183 A CN 201510324183A CN 104865517 B CN104865517 B CN 104865517B
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Abstract
This application provides one kind to detect debug circuit, for testing the circuit-under-test with serial line interface, including：Test input control terminal, is connected with the serial line interface of circuit-under-test；Register group, the input of serial line interface being received to carry out assignment, and receiving control signal from test input control terminal, according to assignment data and control signal, control circuit-under-test enters test pattern；With test output channel, wherein in test mode, according to the assignment of register group, open it is corresponding with measured signal tests output channel, and high-low pressure signal and current signal are distinguished and transmitted.The quantity of the circuit flexibly configurable test signal, it is simple in construction, it is easy to use, can to greatest extent do not change it is intrinsic on the basis of, carry out the debugging and test of key signal, meet quality assurance and the reliability requirement of integrated circuit.
Description
Technical field
The application is related to the detection debug circuit in a kind of IC design.It is more particularly related to all
The detection debug circuit that the circuit-under-test of such as memory device with serial line interface etc is tested.
Background technology
At present, the analog simulation in integrated circuit design process, test verification method can not be covered in whole integrated circuit
Institute of portion produced problem.This internal circuit problem is possible to be embodied in whole integrated circuit function or performance test, phenomenon
It is essentially identical.Meanwhile the particular problem present in IC interior, such as internal clock cycles are inaccurate, reference voltage value drift
Shifting etc. is also difficult to position.Therefore, in order to ensure the q＆r requirement of integrated circuit, testing efficiency is improved, in design
Test problem is considered as, design is easy to the circuit of test and debugging.
In the prior art, as modern integrated circuits scale is increasing.Although adjustable key can be surveyed in design process
Signal is more, also easier with positioning to the investigation of product problem, but excessive test lead is drawn, and not only has influence on former chip
The integral layout of port, also bring trouble to post-production test board and encapsulation.
The content of the invention
Accordingly, it is desirable to provide a kind of detection debug circuit without excessive test port carrys out the circuit progress to memory device
Detection and debugging.Thus, realize that circuit can using the serial line interface control register group of circuit-under-test the invention provides a kind of
The detection debug circuit for the property surveyed.
The detection debug circuit includes：Test input control terminal, is connected with the serial line interface of the circuit-under-test；Register
Group, the input for receiving the serial line interface receives control signal to carry out assignment, and from the test input control terminal, according to institute
Assignment data and the control signal are stated, controls the circuit-under-test to enter test pattern；With test output channel.Wherein in institute
State under test pattern, according to the assignment of the register group, the test output channel corresponding with measured signal is opened.
Above-mentioned detection debug circuit and circuit-under-test share the serial line interface of circuit-under-test, and do not change primary circuit structure or
Primary circuit is set additionally to add other structures.
In above-mentioned detection debug circuit, test input control terminal is by gating or turning off come the shape of control register group
State；Whether the strobe state decision-making circuit that register group inputs control terminal according to test enters test pattern, and passes through serial interface
Mouthful be reconfigured, by debugging end of the debugged signal output to internal circuit, complete debugging, or by detected signal export to
Test output channel；Test output channel opens the output channel of detected signal to export by the control signal of register group
The signal detected is needed when register group simulates assignment in circuit.
Investigation in order to facilitate problem carries out weight, it is necessary to which end is debugged in the input of the module to be gone wrong by register pair analysis
New assignment, output valve or the electric parameter of investigation is set to adjust back to default value to carry out the analysis of problem, the process is to deposit
Assignment of the device group to analog module in circuit-under-test.In the case of power supply not power down, by the way that test input control terminal is dragged down
Test pattern is turned off, circuit is entered normal operating conditions, now the value at the input debugging end of problem module has become in circuit
For new assigned value.
In some embodiments, when test input control terminal is turns off, the output of register group is upper electric default value, string
Line interface performs normal instructions and enters working condition；When test input control terminal is opened, into test pattern, serial port circuit
Debugging position of the serial line interface to register group carries out assignment again after state machine detects start bit, and the debugging position is to analog module
Input debugging end be controlled.Shut-off test pattern enters normal operating conditions after debugging position assignment, now according to register
Assignment the adjustable part of internal analogue circuit is debugged or detected.
In some embodiments, serial line interface is downloaded in test input control terminal gating and the effective condition of chip selection signal
Enter to go here and there code, after being loaded into last position of string code, next clock signal rising edge will in all string codes write-in registers it is right
Register group carries out assignment, to realize debugging and detection to internal circuit.
In some embodiments, register group sets initial value to be used for internal simulation under circuit normal mode when upper electric
The fixed configurations and all sense channels of shut-off of circuit module.Register group is matched somebody with somebody again by testing input control terminal
Put, test pattern can be opened, then assignment again is carried out to corresponding test path control signal, the test for wanting detection can be opened
Signal path, the production of monitoring signals.
In some embodiments, detection debug circuit may also include decoding circuit, decoding circuit and register group and survey
Output channel connection is tried, opening and shutting off for test output channel is controlled by decoding circuit.
In the above-described embodiment, the test input control terminal that circuit can be encapsulated out in unnecessary empty pin is used to enter survey
Die trial formula, it is ensured that upper electricity is correctly completed, and makes chip be in correct working condition, and not interfering with the normal of memory device makes
With the design accuracy for reducing analog circuit requires.
Brief description of the drawings
Fig. 1 is the structured flowchart of the detection debug circuit comprising an embodiment of the present invention；
Fig. 2 is the timing diagram of the reference voltage of the detection circuit-under-test of detection debug circuit shown in Fig. 1；
Fig. 3 is a kind of circuit theory diagrams of implementation of the test output channel of detection debug circuit shown in Fig. 1；
Fig. 4 is the circuit theory diagrams of another implementation of the test output channel of detection debug circuit shown in Fig. 1.
Embodiment
Embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the structured flowchart of the detection debug circuit of an embodiment of the present invention.The circuit utilizes the string of circuit-under-test
Line interface control register group, so as to be detected and debugged to circuit-under-test.
As shown in figure 1, detection debug circuit includes test input control terminal 2, register group 3 and test output channel 4.Its
In, detection debug circuit also uses the serial line interface 1 of circuit-under-test.The number of register is by circuit-under-test in register group
Need to detect or the signal number debugged determines, any number can be modified as needed.Register group 3 in the present embodiment
The shift register being linked to be for 32 registers, it is configured to serial input-parallel output.
As shown in figure 1, the serial line interface 1 of circuit-under-test is connected with detecting the register group 3 of debug circuit, for by outside
The data input of input is into register group 3 with to the register progress assignment in register group 3.Test input control terminal 2 with
Register group 3 connects, by the gating or cut-off signals of the control terminal 2 come the state of control register group 3.Register group 3 can
It is arranged in the digital circuit of circuit-under-test.Test input control terminal 2 is strobe state (high level) according to external signal control
When, circuit-under-test enters test pattern.Into after test pattern, the module of design margin can be adjusted in circuit-under-test, be needed
The key signal tested can be output.
In addition, the string code that register group 3 can be inputted by serial line interface 1 reconfigures so that measured signal export to
Test output channel 4.The output channel that output channel 4 opens measured signal according to the control signal of register group 3 is tested, with defeated
The signal detected is needed when going out register group assignment in circuit.
As shown in figure 1, chip selection signal, clock signal and data-signal (go here and there code) are inputted into digital circuit.Serially
Interface 1 is gated in test input control terminal 2 and the effective condition of chip selection signal is downloaded into string code with to the assignment of register group 3.When
Serial line interface 1 be loaded into string code last when, next clock signal rising edge by all string codes write-in register groups 3
In, the state of control register group 3.
When test input control terminal 2 turns off (low level), the output of register group 3 is upper electric default value, and serial line interface 1 is held
Row normal instructions enter working condition.When test input control terminal 2 opens (high level), into test pattern, detect
Serial line interface 1 carries out assignment again to register group 3 behind beginning position, and shut-off test pattern enters normal operating conditions after assignment, this
When the adjustable part of internal analogue circuit can be debugged or be detected according to the assignment of register group 3.
The time required to the process that output valve or parameter recalled into preset value with the digit of register in register group namely individual
Number is relevant.In the present embodiment, the process needs 34 clock cycle, including serial ports clock acquisition is to the start bit of serial input
First clock cycle, 32 clock cycle that 32 register assignments need, and register value is finally sent to inside
One clock cycle of circuit.
By the assignment of serial line interface 1, register group 3 can be entered to the internal module of circuit-under-test in a conventional manner
Row debugging, the TCH test channel of measured signal can also be opened and transmit measured signal to test output channel 4.
Fig. 2 is the timing diagram of detection reference voltage according to an embodiment of the invention.
Key component leaves certain design margin when analog module designs.By taking analog circuit as an example, including electric charge
Voltage-regulation, voltage rising time regulation, the precharge time regulation of sense amplifier and the sense amplifier reference current of pump
Regulation etc..For whole circuit detection signal may also include digital circuits section output critical mode control signal control
Read and write the key signal wiped, test charge pump high pressure, reference voltage, internal clocking, memory cell current, reference memory unit electricity
The key signals such as stream.
As shown in Fig. 2 illustrate by taking test benchmark voltage Vref as an example the detection debug circuit how detected signal value.Upper
After the completion of electricity, when test input control terminal 2 gates (high level) and chip selection signal effectively (high level), circuit enters test mould
Formula.Serial line interface 1 starts to the assignment of register group 3 after the state machine of serial port circuit detects start bit.
According to the definition of register-bit, only when the control bit TM_VREF for controlling whether detection reference voltage is 1, survey
The TCH test channel of examination reference voltage can just be opened.After terminating to the assignment of register group 3, shut-off test input control terminal exits
Test pattern.Circuit-under-test enters normal operating conditions and carries out read operation., will be from test output terminal after reference voltage starts
211 output reference voltage values.
Fig. 3 is a kind of circuit theory diagrams for implementation that output channel is tested in the present invention.Tested in the circuit diagram defeated
Go out passage output high-voltage signal.Wherein, NAND28, NAND236 are two input nand gates, and INV58, INV59, INV25 are paraphase
Device, HVINV24, HVINV26 are high pressure phase inverter, and M71 is nmos device, and M73, M74 are PMOS device.The circuit is to carry out
Enter the exterior measuring of horizontal high voltage and outer filling when erasing and write operation.During high pressure exterior measuring, by the unlatching of Hi-pot test output channel, survey
Try out high tension voltage value caused by internal charge pump；When being filled outside high pressure, high-voltage value is fed by High voltage output passage, makes internal electricity
Road works outside directly using to high voltage supply, without being powered using internal charge pump.It can thus be appreciated that Hi-pot test passage is two-way
Port.
100 ends and 101 ends are to wipe the control terminal with write operation, and 102 ends are high-pressure channel control terminal, are connected on register group
Output end.The control signal of the digital circuits section output of circuit-under-test is through 100 ends and 101 ends respectively via phase inverter INV 59
Inputted with INV 58 to NAND gate NAND 28 and carry out logical operation, the result of logical operation comes from register with the input of 102 ends
The signal of group accesses nmos device M71 grid, another way is through paraphase all the way after NAND gate NAND 236 logical operation
Device INV 25 and high pressure phase inverter HVINV 24 accesses PMOS device M73 grid, and another way is also through phase inverter INV 25 and height
Press phase inverter HVINV 26 to access PMOS device M74 grid, M71 break-make is controlled with this, will when transmission channel is not turned on
M71 is opened, and moves M71 drain potentials to zero, ensures that M73 and M74 preferably ends.When M73 and M74 is turned on, M71 shut-offs,
The conducting of two pipes is not influenceed.Internal port 110 is connected to PMOS device M73 drain electrode, and outside port 111 is connected to PMOS device M74
Drain electrode.PMOS device M73 connects nmos device M71 drain electrode with M74 source electrode.When 100 ends or 101 ends with 102 ends simultaneously
Effectively (high level) when, NAND236 outputs is low, and now M71 pipes turn off, M73 and M74 pipes are opened, and Hi-pot test passage is opened,
Internal port 111 connects with outside port 110, can enter the exterior measuring of horizontal high voltage to circuit-under-test by 110 ends and 111 ends
Or outer filling, i.e. the external output of test signal or the input of external signal.
Fig. 4 is the circuit theory diagrams for another implementation that output channel is tested in the present invention.Tested in the circuit defeated
Go out passage output low-voltage signal or current signal.Wherein NAND 6<0:7>For three input nand gates, mark<0:7>Represent there is 8
The same NAND gate in road, but input is different.INV 134<0:7>、INV 2<0:3>、INV 3<0:3>、INV 4<0:2>、INV
1<0:2>, INV 5, INV 112 be phase inverter, M23<0:7>、M0<0:2>, M63 be nmos device.The control of 201~204 ends is low
Press signal testing output.
202 Duan Jing No. tetra- gun stocks INV 2<0:3>With INV 3<0:3>Access NAND gate NAND 6<0:7>, input comes from
Four signals of register group, this four signals are four in 32 signals that register group exports in the present embodiment, can be by
User is voluntarily set according to circuit requirements.Using this four signals as decoding input to nmos device M23<0:7>Grid, can
To control the unlatching of 16 passages, that is, it is linked to be the line decoder of 4 line -16, as decoding circuit, wherein 8 passages are nmos device
M23<0:7>8 TCH test channels, remaining 8 passages are hanging.
201 ends receive the signal that the needs of digital circuit output are tested, and the test signal set in the present embodiment is
Number control signal in the circuit-under-tests such as clock signal clk, as erased, progd, ewen, ewds, porb, poweron,
Ref_en etc., these signals can be set according to the demand of different circuits.When 202 ends decode gating nmos device M23<0:7>In
When wherein all the way, test signal corresponding to 201 ends is output to 204 ends.
203 ends can distinguish three signals of receiving register group output, and reference voltage test control is arranged in the present embodiment
Signal TM_VBG, internal 1.8V voltage testers control signal TM_1d8 and logic testing control signal TM_LOGIC processed, via
Phase device INV 4<0:2>And INV1<0:2>Export respectively afterwards to nmos device M0<0:2>Grid, respectively control gating benchmark electricity
The TCH test channel M0 of the test signal of pressure, reading bias voltage and the input of 201 ends<0:2>Grid open.
204 ends can input the signal exported from analog circuit and digital circuit corresponding to 203 ends respectively, root in the present embodiment
According to voltage signal VREF, internal 1.8V voltage signals V1d8 and logical signal LOGIC on the basis of the signal of 203 ends input.When 203
Hold input above three signal in have one it is effective when, choose corresponding to 204 ends signal and by the end of test output terminal 211
Tested.
205 ends and 206 end control electric current signal test outputs.206 ends are controlled by register group, when 206 end input signals
When effective, the current signal of 205 ends output can be transmitted by nmos device M63, be tested at 211 ends.
The circuit has only used a test input and most two tests output detections it can be seen from Fig. 3 and Fig. 4
End just completes the detection and debugging of multiple unlike signals, and can believe data signal, analog signal, voltage signal and electric current
Number separately transmission, reduce design technology, it is simple in construction, it is easy to use.
Embodiments of the invention are the foregoing is only, not thereby limit the scope of patent protection of the present invention, the present invention is also
Above-mentioned various modules can additionally be improved, or be replaced using technically equivalent ones.Such as：In above-mentioned example
Signal can be replaced according to the situation of actual circuit-under-test with other signals.Other modules further optimized can also be increased
Deng.Therefore the equivalence changes that all specifications and diagramatic content with the present invention are made, or directly or indirectly apply to other correlations
Technical field, similarly all it is contained in the range of of the invention cover.
Claims (5)
1. one kind detection debug circuit, for testing the circuit-under-test with serial line interface, the detection debug circuit
Including：
Test input control terminal, is connected with the serial line interface of the circuit-under-test；
Register group, the input for receiving the serial line interface receive control to carry out assignment, and from the test input control terminal
Signal, according to the assignment data and the control signal, the circuit-under-test is controlled to enter test pattern；With
Output channel is tested, wherein
Under the test pattern, according to the assignment of the register group, the test output channel corresponding with measured signal
Open；
Effective and when chip selection signal is effective in test input control terminal, the register group is loaded into by the serial line interface to be used for
To the string code of the register group assignment, after being loaded into last position of string code, posted described in the rising edge in next clock signal
The assignment of storage is completed, to realize debugging and detection to circuit-under-test.
2. detection debug circuit according to claim 1, including a test input control terminal and most two surveys
Examination output test side.
3. detection debug circuit according to claim 1, wherein, the configuration related to the register group assignment includes：
Upper electric initial value, it is all for the fixed configurations of the internal analogue circuit module under circuit-under-test normal mode and shut-off
Sense channel；
Control terminal is inputted by the test to reconfigure register group, for opening test pattern, to the tested electricity
The internal module on road is debugged；With
Again assignment is carried out to corresponding test path control signal, for opening the TCH test channel of measured signal, monitoring signals
Production.
4. the detection debug circuit according to any one of claim 1-3, in addition to decoding circuit, the decoding circuit with
The register group is connected with the test output channel, and the unlatching of the test output channel is controlled by the decoding circuit
With shut-off.
5. a kind of circuit with serial line interface, including in digital circuit blocks and analog module, and claim 1-4
Detection debug circuit described in any one, wherein the register group is included in the digital circuit blocks, the simulation electricity
Road module is connected between the register group and the test output channel, and the signal of the register group is transmitted to the test
Output channel is debugged and detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510324183.7A CN104865517B (en) | 2015-06-12 | 2015-06-12 | Detect debug circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510324183.7A CN104865517B (en) | 2015-06-12 | 2015-06-12 | Detect debug circuit |
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| CN104865517A CN104865517A (en) | 2015-08-26 |
| CN104865517B true CN104865517B (en) | 2018-01-02 |
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| CN201510324183.7A Expired - Fee Related CN104865517B (en) | 2015-06-12 | 2015-06-12 | Detect debug circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117236239B (en) * | 2023-11-10 | 2024-02-20 | 成都翌创微电子有限公司 | Universal connectivity test method, apparatus and medium for digital circuit verification |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536486A (en) * | 2003-04-04 | 2004-10-13 | 上海华园微电子技术有限公司 | Intelligent card chip with microprocessor capable of making automatic test |
| CN1805054A (en) * | 2004-11-29 | 2006-07-19 | 因芬尼昂技术股份公司 | Method for testing semiconductor chips using register sets |
| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103903651A (en) * | 2012-12-25 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Double-line serial port build-in self-test circuit, and communication method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5194890B2 (en) * | 2008-03-05 | 2013-05-08 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
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2015
- 2015-06-12 CN CN201510324183.7A patent/CN104865517B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536486A (en) * | 2003-04-04 | 2004-10-13 | 上海华园微电子技术有限公司 | Intelligent card chip with microprocessor capable of making automatic test |
| CN1805054A (en) * | 2004-11-29 | 2006-07-19 | 因芬尼昂技术股份公司 | Method for testing semiconductor chips using register sets |
| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103903651A (en) * | 2012-12-25 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Double-line serial port build-in self-test circuit, and communication method thereof |
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| CN104865517A (en) | 2015-08-26 |
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