CN104852746A

CN104852746A - Decoder and decoding method for LDPC code

Info

Publication number: CN104852746A
Application number: CN201510278024.8A
Authority: CN
Inventors: 张锦南
Original assignee: Beijing University of Posts and Telecommunications
Current assignee: Beijing University of Posts and Telecommunications
Priority date: 2015-05-27
Filing date: 2015-05-27
Publication date: 2015-08-19
Anticipated expiration: 2035-05-27
Also published as: CN104852746B

Abstract

The present invention provides a decoder and a decoding method for an LDPC code. The decoder includes: an interconnection module, a plurality of check node units CNUs and a plurality of variable node units VNUs. Each VNU is used to receive an LDPC code to be decoded, operate on the LDPC code to be decoded, and send the LDPC code after operation to the corresponding CNU via the interconnection module. Each CNU is used to receive the LDPC codes after operation sent by the corresponding VNUs, combine the 4 LDPC codes after operation into an H matrix, and determine whether the number of rows of the H matrix is equal to a preset number of rows. If the number of rows of the H matrix is not equal to the preset number of rows, the CNU transforms the H matrix to obtain a new H matrix such that the number of rows of the new H matrix is equal to the preset number of rows, and performs iterative decoding by using the new H matrix. The decoder and the decoding method of the embodiment of the present invention are capable of converting H matrixes corresponding to various code rates to the same structure for decoding, thereby saving hardware resources.

Description

Decoder and decoding method of LDPC code

Technical Field

The present invention relates to decoding technologies, and in particular, to a decoder and a decoding method for an LDPC code.

Background

The Institute of Electrical and Electronics Engineers (IEEE) 802.11ad standard is mainly used for high-speed file transmission between home multimedia devices, provides a new scheme for wireless communication of home audio and video signals, and lays a foundation for meeting the development of the internet of things. In order to realize high-speed transmission of signals, the standard selects a 60 gigahertz (GHz) spectrum high-frequency carrier wave, and crowded 2.4GHz and 5GHz frequency bands are not used, so that the standard has high requirements on channel transmission rate. A Low Density Parity Check code (LDPC) is a "good" code whose performance is very close to the shannon limit, and has the advantages of Low decoding complexity and high throughput, so that it can implement reliable communication close to channel capacity. Because of its superior performance, LDPC codes have been adopted by the ieee802.11ad standard as channel codecs of the ieee802.11ad standard.

The hardware design of the LDPC code comprises two parts, namely an encoder and a decoder. Since the encoding algorithm is relatively simple, the hardware design of the encoder is also relatively simple. The LDPC decoding algorithm is complex and has large calculation amount, so that the decoder design needs to give consideration to various requirements such as decoding performance, area, throughput rate and the like, and the decoder has various circuit types and complex structure. In the prior art, the ieee802.11ad protocol specifies that LDPC codes have four code rates, which are 1/2, 3/4, 13/16 and 5/8, respectively, and defines H matrices corresponding to the four code rates of the LDPC codes.

However, because the H matrix structures of the four code rates are different, the decoder needs to be designed for the four code rates, so that the hardware resource consumption of the system is very large.

Disclosure of Invention

The invention provides a decoder and a decoding method of LDPC codes, which are used for solving the problem that hardware resources of a system are consumed too much in the decoding process in the prior art.

A first aspect of an embodiment of the present invention provides a decoder for an LDPC code, including: the device comprises an interconnection module, a plurality of check node update modules (CNUs) and a plurality of variable node update modules (VNUs), wherein the number of the VNUs is 4 times that of the CNUs, and each CNU corresponds to 4 different VNUs.

The VNU is connected with the interconnection module and is used for receiving a low-density parity check code (LDPC) code to be decoded, operating the LDPC code to be decoded to obtain the operated LDPC code to be decoded, and sending the operated LDPC code to be decoded to the corresponding CNU through the interconnection module;

the CNU is connected with the interconnection module and used for receiving the LDPC codes to be decoded after operation sent by the corresponding 4 VUNs, combining the 4 LDPC codes to be decoded after operation into a parity check matrix H matrix, judging whether the number of rows of the H matrix is the same as the preset number of rows, if the number of rows of the H matrix is different from the preset number of rows, converting the number of rows of the H matrix into the preset number of rows, acquiring an updated H matrix, and performing iterative decoding by adopting the updated H matrix.

A second aspect of the embodiments of the present invention provides a decoding method for an LDPC code, including:

the decoder receives a Low Density Parity Check (LDPC) code to be decoded, and operates the LDPC code to be decoded to obtain the operated LDPC code to be decoded;

the decoder combines the LDPC codes to be decoded after operation into a parity check matrix H matrix, judges whether the row number of the H matrix is the same as the preset row number, if the row number of the H matrix is different from the preset row number, the row number of the H matrix is converted into the preset row number, an updated H matrix is obtained, and iterative decoding is carried out by adopting the updated H matrix.

The CNU receives the LDPC codes to be decoded after the corresponding 4 VNUs are operated, the 4 LDPC codes to be decoded after the operation are combined into an H matrix, whether the row number of the H matrix is the same as the preset row number or not is judged, if the row number of the H matrix is different from the preset row number, the row number of the H matrix is converted into the preset row number, the updated H matrix is obtained, the updated H matrix is adopted for iterative decoding, the H matrix corresponding to various code rates is converted into the same structure for decoding, and therefore hardware resources are saved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a decoder of an LDPC code according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a decoding structure of a second decoder of the LDPC code according to the present invention;

FIG. 3 is a schematic diagram of a decoding structure of a third embodiment of a decoder for LDPC codes according to the present invention;

FIG. 4 is a schematic structural diagram of a decoder of an LDPC code according to a fourth embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a decoder of an LDPC code according to a fifth embodiment of the present invention;

FIG. 6 is a flowchart illustrating a first decoding method of an LDPC code according to the present invention;

fig. 7 is a flowchart illustrating a second decoding method of an LDPC code according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

For the convenience of understanding the technical solution of the embodiment of the present invention, first, the H matrix of the LDPC code in the ieee802.11ad protocol is described below.

In the ieee802.11ad protocol, it is specified that the LDPC code has four code rates, 1/2, 3/4, 13/16 and 5/8, and the four code rates correspond to an H matrix respectively. The H matrix is a parity check matrix of the LDPC code, in which each row represents one parity check equation, nodes in each row are referred to as check nodes, each column represents codeword information, and nodes in each column are referred to as variable nodes. The H matrix of the four code rates is composed of a plurality of sub-square matrixes, and each sub-square matrix is obtained by circularly right shifting a 42 × 42 unit matrix or is a null matrix with all data being zero. For example, a data "29" at the leftmost upper corner of the H matrix in table 1 represents a 42 × 42 unit matrix of submatrices shifted 29 times to the right; the upper right-most corner of the H matrix in table 1 is empty data, representing a 42 × 42 sub-square matrix with all data empty. For the sub-square matrix with all data being empty, during decoding, the variable node updating module VNU and the check node updating module CNU in the decoder are in an idle running state, which causes resource waste.

In the ieee802.11ad protocol, an LDPC code H matrix with a code rate of 1/2 is H336 × 672; the LDPC code H matrix with code rate 5/8 is H168 × 672, the LDPC code H matrix with code rate 13/16 is H126 × 672, and the LDPC code H matrix with code rate 3/4 is H168 × 672. That is, the H matrix structure of the four code rates is different. Therefore, in designing the LDPC decoder, it is necessary to design in consideration of the differences of the four H matrices.

The H matrices of the LDPC code for four code rates are shown in tables 1 to 4.

Table 1 is an H matrix of code rate 13/16, as shown in table 1:

TABLE 1

29	30	0	8	33	22	17	4	27	28	20	27	24	23
																37	31	18	23	11	21	6	20	32	9	12	29	10	0	13
25	22	4	34	31	3	14	15	4	2	14	18	13	13	22	24

Table 2 is an H matrix of code rate 3/4, as shown in table 2:

TABLE 2

35	19	41	22	40	41	39	6	28	18	17	3	28
															29	30	0	8	33	22	17	4	27	28	20	27	24	23
37	31	18	23	11	21	6	20	32	9	12	29		0	13
															25	22	4	34	31	3	14	15	4		14	18	13	13	22	24

Table 3 is an H matrix of code rate 5/8, as shown in table 3:

TABLE 3

20	36	34	31	20	7	41	34		10	41
															30	27		18		12	20	14	2	25	15	6
35		41		40		39		28			3	28
															29		0			22		4		28		27	24	23
	31		23		21		20		9	12			0	13
																22		34	31		14		4						22	24

Table 4 is an H matrix of code rate 1/2, as shown in table 4:

TABLE 4

40		38		13		5		18
															34		35		27			30	2	1
	36		31		7		34		10	41
																27		18		12	20				15	6
35		41		40		39		28			3	28
															29		0			22		4		28		27		23
	31		23		21		20			12			0	13
																22		34	31		14		4				13		22	24

Aiming at the characteristics of the four H matrixes, the embodiment of the invention carries out line number conversion on the four H matrixes when the decoder is designed, so that the four converted H matrixes have the same structure, and the four code rates can be stored and processed by using one structure when the decoder is designed, thereby greatly reducing the hardware resource consumption of a system, facilitating the mutual switching among the LDPC decoders with the four code rates and improving the decoding efficiency.

Fig. 1 is a schematic structural diagram of a first embodiment of a decoder for an LDPC code provided in the present invention, and as shown in fig. 1, the decoder 100 for an LDPC code includes: the system comprises an interconnection module 110, a plurality of Check Node Units (CNUs) 130, and a plurality of Variable Node Units (VNUs) 120, wherein the number of the VNUs 120 is 4 times of the number of the CNUs 130, and each CNU130 corresponds to 4 different VNUs 120.

And the interconnection module 110 is configured to connect between the VNU120 and the CNU130, and complete information transfer between the VNU120 and the CNU 130.

The VNU120 is connected to the interconnection module 110, and is configured to receive the LDPC code to be decoded, perform operation on the LDPC code to be decoded, obtain the LDPC code to be decoded after the operation, and send the LDPC code to be decoded after the operation to the corresponding CNU130 through the interconnection module 110. It should be noted that, the LDPC code to be decoded may reach the VNU120 from a plurality of inputs, and the operation on the LDPC code to be decoded may be performed by the VNU120 by summing all input data for each input and subtracting data corresponding to the input to form the LDPC code to be decoded after the operation.

And the CNU130 is connected to the interconnection module 110, and configured to receive the calculated LDPC codes to be decoded, which are sent by the 4 corresponding VNUs 120, combine the 4 calculated LDPC codes to be decoded into an H matrix, determine whether a row number of the H matrix is the same as a preset row number, convert the row number of the H matrix into the preset row number if the row number of the H matrix is different from the preset row number, obtain an updated H matrix, and perform iterative decoding using the updated H matrix.

In the transcoder 100, the number of VNUs 120 is 4 times the number of CNUs 130, and each CNU130 corresponds to 4 different VNUs 120. Preferably, the transcoder in the embodiment of the present invention may include 672 VNUs 120, and 168 CNUs 130.

Preferably, a configuration register is disposed in the decoder 100 according to the embodiment of the present invention, and a configuration interface of the configuration register is used to configure the code rate and the maximum iteration number.

Preferably, the decoder 100 sets 672 input interfaces, each of which conveys 6 bits of information.

It should be noted that the decoder of the LDPC code provided in the embodiment of the present invention can meet the decoding throughput requirement of the ieee802.11ad standard on the LDPC under the BPSK and QPSK modulation modes, and for the 16QAM modulation mode, the decoder of the LDPC code needs higher throughput to meet the standard requirement, and the parallelism can be improved by adding two LDPC decoding modules at the later stage, so that the decoding throughput requirement of the ieee802.11ad standard on the LDPC is met.

In this embodiment, the CNU receives the LDPC codes to be decoded after the corresponding 4 VNUs are operated, combines the LDPC codes to be decoded after the 4 VNUs are operated into an H matrix, determines whether the number of rows of the H matrix is the same as the preset number of rows, converts the number of rows of the H matrix into the preset number of rows if the number of rows of the H matrix is different from the preset number of rows, obtains an updated H matrix, performs iterative decoding using the updated H matrix, and realizes that H matrices corresponding to multiple code rates can be converted into the same structure for decoding, thereby saving hardware resources.

On the basis of the foregoing embodiment, if the number of rows of the H matrix is greater than the preset number of rows, the CNU130 converts the number of rows of the H matrix into the preset number of rows, specifically: and combining two non-overlapping rows of corresponding position data in the H matrix into one row, wherein the two non-overlapping rows of corresponding position data refer to that the position content of one row of data, which is not empty, is empty in the position content corresponding to the other row.

In another embodiment, if the number of rows of the H matrix is less than the preset number of rows, the CNU130 converts the number of rows of the H matrix into the preset number of rows, specifically: and supplementing the row number for the H matrix to reach the preset row number, wherein the supplemented intra-row data is the linear summation of the subsets of the rows in the original H matrix or the subsets of the rows in the original H matrix.

Specifically, in the four code rates shown in the foregoing tables 1 to 4, it is assumed that the number of rows of the H matrix of code rate 3/4 is taken as the preset number of rows:

(1) for the H matrix with code rate of 3/4, no line number conversion is needed, and the line number is equal to the preset line number.

(2) For the H matrix of code rate 5/8, as shown in table 3, the position of the fifth row where the data content is not empty is empty in the position data corresponding to the third row, and the position of the sixth row where the data content is not empty is empty in the position data corresponding to the fourth row, i.e. the corresponding position data in the fifth row and the third row are not overlapped, and the corresponding position data in the fourth row and the sixth row are not overlapped. And integrating the contents of the third row and the fifth row into a row, integrating the contents of the fourth row and the sixth row into a row, wherein the row number of the 5/8-bit rate H matrix after integration is the same as the preset row number. The 5/8 code rate H matrix after row number conversion is shown in Table 5:

TABLE 5

20	36	34	31	20	7	41	34		10	41
																30	27		18		12	20	14	2	25	15	6

35	31	41	23	40	21	39	20	28	9	12	3	28	0	13
																29	22	0	34	31	22	14	4	4	28		27	24	23	22	24

(3) For the 1/2 rate H matrix, as shown in table 4, the position data content corresponding to the position where the data content is not empty in the third row in the first row is empty, the position data content corresponding to the position where the data content is not empty in the fourth row in the second row is empty, the position where the data content is not empty in the seventh row in the fifth row is empty, and the position data content corresponding to the position where the data content is not empty in the eighth row in the sixth row is empty, that is, the corresponding position data in the first row and the third row are not overlapped, the corresponding position data in the second row and the fourth row are not overlapped, the corresponding position data in the fifth row and the seventh row are not overlapped, and the corresponding position data in the sixth row and the eighth row are not overlapped. And integrating the contents of the first row and the third row into a row, integrating the contents of the second row and the fourth row into a row, integrating the contents of the fifth row and the seventh row into a row, integrating the contents of the sixth row and the eighth row into a row, and enabling the row number of the 1/2-bit rate H matrix after integration to be the same as the preset row number. The 1/2 code rate H matrix after row number conversion is shown in Table 6:

TABLE 6

40	36	38	31	13	7	5	34	18	10	41
															34	27	35	18	27	12	20	30	2	1	15	6
35	31	41	23	40	21	39	20	28		12	3	28	0	13
															29	22	0	34	31	22	14	4	4	28		27	13	23	22	24

(4) For the H matrix with code rate of 13/16, as shown in table 1, if the number of rows is less than the preset number of rows, performing row number supplementation on the H matrix to reach the preset number of rows, where the supplemented intra-row data is a subset of the rows in the original H matrix or a linear summation of the subsets of the rows in the original H matrix.

Specifically, a sub-layer may be added to the H matrix with the code rate of 13/16 by using the linear addition and the supplementary row number of the subset of each row in the original H matrix, and a part of sub-units in the sub-layer with the code rate of 13/16 are eliminated. The 13/16 rate H matrix after row number complementation is shown in Table 7:

TABLE 7

Fig. 2 is a schematic view of a decoding structure of a decoder of an LDPC code according to a second embodiment of the present invention, where if the number of rows of the H matrix is different from the preset number of rows, a specific implementation process of the decoder to convert the number of rows of the H matrix into the preset number of rows may refer to fig. 2, specifically:

as shown in fig. 2, the CNU130 first receives LDPC codes to be decoded after operation sent by 4 VUNs corresponding to the LDPC codes to be decoded, combines the 4 LDPC codes to be decoded after operation into an H matrix 131, further determines whether a row number of the H matrix 131 is the same as a preset row number, converts the row number of the H matrix into the preset row number if the row number of the H matrix 131 is different from the preset row number, obtains an updated H matrix, and performs iterative decoding using the updated H matrix.

In a specific implementation process, the CNU130 determines that the first row of data in the H matrix 131 cannot be integrated with data in other rows, the first row of data is directly decoded in the CNU1, and the second row and the third row of data in the H matrix 131 can be integrated, so that the second row and the third row of data are decoded in the same CNU, that is, the CNU2, and during the decoding process, the CNU130 performs calculation on the two original rows of data, for example, the 1 st, 2 nd, 5 th, and 8 th data of the CNU2 in fig. 2 belong to the original first row of data, and these data are calculated in one CS132, and the 3 rd, 4 th, 6 th, and 7 th data of the CNU2 belong to the original second row of data, and these data are calculated in another CS 132. The CS132 is a basic comparison unit in the CNU 130. Correspondingly, the output data of the CNU2 is also output individually according to the line in which the data is originally located. Meanwhile, an external interface row _ signal is set in the CNU130 to identify whether the current processing is performed on the same line of information, if the current processing is performed on the same line of information, the identification is set to 1, otherwise, the identification is set to 0.

It should be noted that, since the plurality of H matrices after row number conversion have the same structure, the number of CNU modules can be uniformly designed to 168 when designing the decoder, that is, LDPC code decoding with different code rates can be performed.

By the method, the H matrixes with different line numbers are converted into the same line number, and the CNU modules with the uniform number are used for decoding, so that the problem of hardware resource waste caused by the fact that decoders with different structures need to be designed due to the fact that H matrixes with different code rates are different in the prior art is solved.

Fig. 3 is a schematic diagram of a decoding structure of a third decoder of the LDPC code provided in the present invention, as shown in fig. 3:

each CNU130 includes 16 inputs and 16 outputs, and correspondingly, the H matrix includes 16 data per row. Where each datum may refer to an element in the H matrix.

The iterative decoding performed by the CNU130 using the updated H matrix specifically includes: the CNU130 sequentially determines the minimum absolute value and the second minimum absolute value data of all input data in the 16 input received operated LDPC codes to be decoded, forms a new H matrix by using the minimum absolute value and the second minimum absolute value data, and sends the new H matrix to the corresponding 4 VNUs through the interconnection module. Correspondingly, the VNU120 is configured to receive corresponding sub-matrices in the new H matrix, sum the data received by the 4 inputs respectively, subtract the data corresponding to the input from the sum result to obtain new data, combine the new data to form a new sub-matrix, send the new sub-matrix to the CNU130 through the interconnection module, and sequentially loop to complete iterative decoding.

Further, on the basis of the above embodiment, the CNU130 sequentially determines the data with the smallest absolute value and the next smallest absolute value in all the input data in the LDPC code to be decoded received by 16 inputs after the operation, including:

and if the 16 data belonging to the same row in the updated H matrix are merged data of two rows of data in the original H matrix, the CNU is used for determining the data with the minimum absolute value and the minimum absolute value in the two rows of data in the original H matrix respectively, wherein the first 8 inputs in the 16 inputs correspond to the first row of data in the two rows of data in the original H matrix, and the last 8 inputs in the 16 inputs correspond to the second row of data in the two rows of data in the original H matrix. Or,

if the updated 16 data belonging to the same row of the H matrix are also the same row of data in the original H matrix, the CNU determines the data with the minimum absolute value and the second minimum absolute value among the 16 data, wherein the 16 inputs correspond to the 16 data in sequence.

Specifically, the CNU130 performs the check node update operation mainly for finding the data with the minimum absolute value in the nodes except for the self node in the input data, that is, finding the data with the minimum absolute value and the second minimum absolute value in the input data, and if the self node data is the minimum, calculating with the second minimum data, and if the self node data is not the minimum, calculating with the minimum data. The 16 input data are inputted to four basic comparison units CS132, respectively, and the CS132 is a basic comparison unit with four inputs and two minimum outputs. If the 16 input data belong to two rows of data in the original H matrix, the previous row of data is input in the first two CSs 132, the next row of data is input in the second two CSs 132, the first two CSs 132 and the second two CSs 132 respectively perform two-stage operation to obtain the minimum value and the second minimum value of the absolute value of each row of data, namely, the minimum value and the second minimum value of all the input data in each row are determined, so that a new H matrix is formed, and the new H matrix is output through the first 8 output interfaces and the second 8 output interfaces respectively.

If the 16 input data belong to a row of data in the original H matrix, the 4 CSs 132 perform three-stage operation together to obtain the minimum value and the second minimum value of the absolute value of the row of data, and according to the comparison between the obtained minimum value and the second minimum value and the node data, the data with the minimum value and the second minimum value in all the input data are determined to form a new H matrix and are output through 16 output interfaces. And the data output by the output interface is respectively sent to the corresponding 4 VNUs by the interconnection module.

It will be understood by those skilled in the art that, in a specific implementation, for example, using FPGA, the decoding process of CNU can be divided into two parts, namely data processing and data symbol processing, and the two parts can be implemented by using the above iterative decoding method respectively.

Further, the VNU120 includes 4 inputs and 4 outputs, and after receiving the H matrix submatrix after the iterative decoding by the CNU130 sent by the interconnection module through the 4 inputs, the VNU120 calculates the sum of all input data, subtracts the value of the input from the sum result, and uses the sum as the output corresponding to the input, and combines all output data to form a new submatrix, and sends the new submatrix to the CNU130 through the interconnection module.

Fig. 4 is a schematic structural diagram of a fourth embodiment of a decoder for an LDPC code provided in the present invention, as shown in fig. 4, on the basis of fig. 1, the decoder may further include: the decision block 140, specifically,

the VNU120 is connected to the decision module 140, and configured to send a new sub-matrix to the decision module 140 after combining new data to form a new sub-matrix;

the decision module 140 is configured to determine whether iterative decoding is completed according to the new sub-matrix, and if not, feed back iteration incomplete information to the VNU120, so that the VNU120 sends the new sub-matrix to the CNU130 according to the iteration incomplete information.

Specifically, when the VNU120 completes iterative decoding once, a new submatrix after iterative decoding is output to the decision module 140, and the decision module 140 determines whether the maximum iteration number set on the decoder 100 has been reached or whether the following formula is satisfied, and if so, stops decoding and outputs a decoding result; otherwise, incomplete information is fed back to the VNU120, so that the VNU120 sends the new sub-matrix to the CNU130 according to the iteration incomplete information to continue the iterative decoding. In particular, the decision module 140 may employ a formula

It is determined whether the maximum number of iterations set on the decoder 100 has been reached, where H represents the H matrix and X represents the^TIt should be noted that, as can be understood by those skilled in the art, the above formula mainly completes matrix multiplication, which is similar to the function of an encoder of an LDPC code, and is not described herein again.

Fig. 5 is a schematic structural diagram of a fifth embodiment of a decoder for an LDPC code provided in the present invention, and specifically, fig. 5 is a schematic structural diagram of an internal interconnection module in the decoder for an LDPC code.

The interconnection module 110 is configured to, when receiving a new H matrix sent by the CNU130, shift the originally stored H matrix corresponding to the CNU130 to store the new H matrix, and send the new H matrix to the corresponding VNU 120; accordingly, the number of the first and second electrodes,

an interconnection module 110, configured to, when receiving the new sub-matrix sent by the VNU, shift an originally stored sub-matrix corresponding to the VNU to store the new sub-matrix, and send the new sub-matrix to the corresponding CNU.

In a specific implementation process, the interconnection module 110 divides the CNUs 130 into 42 groups, each group includes 4 CNUs 130, and an input of each group of CNUs 130 is from one of 42 VNUs 120 in 16 VNUs 120. When one CNU130 completes one iterative decoding, the new H matrix after the iteration is output to the interconnection module 110, the interconnection module 110 maps the new H matrix to a backward shift register corresponding to the CNU130, the backward shift register is a barrel-shaped shift register with 42 output ports, the backward shift register shifts the originally stored H matrix to obtain a new H matrix after the iterative decoding by the CNU130, and sends the new H matrix to the VNU120, thereby completing one data transfer from the CNU130 to the VNU 120.

The interconnection module 110 divides the VNUs 120 into 16 groups, each group includes 42 VNUs 120, and after one VNU120 completes one iterative decoding, sends a new submatrix after the iteration to a corresponding forward shift register, where the forward shift register is a barrel shift register with 42 output ports, and shifts the originally stored submatrix by the forward shift register to obtain a new submatrix after the VNU120 iterative decoding, and sends the new submatrix to the CNU130, thereby completing one data transfer from the VNU120 to the CNU 130.

Fig. 6 is a flowchart illustrating a first embodiment of a decoding method of an LDPC code provided in the present invention, as shown in fig. 6, the method includes:

s101, the decoder receives the LDPC code to be decoded, and the LDPC code to be decoded is operated to obtain the operated LDPC code to be decoded.

S102, the decoder combines the LDPC codes to be decoded after operation into a parity check matrix H matrix, judges whether the row number of the H matrix is the same as the preset row number, converts the row number of the H matrix into the preset row number if the row number of the H matrix is different from the preset row number, acquires an updated H matrix, and performs iterative decoding by adopting the updated H matrix. For a specific iterative decoding process, reference may be made to the foregoing embodiment of the decoder portion, and details are not described herein again.

Fig. 7 is a flowchart illustrating a second decoding method of an LDPC code according to the present invention, in step S102, if the number of rows of the H matrix is different from the preset number of rows, the number of rows of the H matrix is converted into the preset number of rows, and as shown in fig. 7, the method for converting the number of rows of the H matrix into the preset number of rows includes:

s201, judging whether the row number of the H matrix is larger than or smaller than a preset row number, if so, executing S202, and if not, executing S203.

S202, two non-overlapping rows of corresponding position data in the H matrix are combined into one row, wherein the two non-overlapping rows of the corresponding position data indicate that the non-empty position of the data content of one row is empty at the position corresponding to the other row.

And S203, performing row number supplement on the H matrix to reach a preset row number, wherein the supplemented row number is the subset of each row in the original H matrix or the linear summation of the subsets of each row in the original H matrix.

Each component in the decoder, such as the VNU, the CNU, the interconnection module and the judgment module, are matched with each other, and the decoding process is completed specifically.

The above-mentioned method is a method executed by the above-mentioned decoder, and the specific execution content and process thereof may refer to the embodiment of the above-mentioned decoder portion, which is similar to the implementation principle and technical effect of the above-mentioned decoder portion and is not described herein again.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoder for LDPC codes, comprising: the system comprises an interconnection module, a plurality of check node update modules (CNUs) and a plurality of variable node update modules (VNUs), wherein the number of the VNUs is 4 times that of the CNUs, and each CNU corresponds to 4 different VNUs;

the CNU is connected with the interconnection module and used for receiving the 4 LDPC codes to be decoded after operation sent by the VUN, combining the 4 LDPC codes to be decoded after operation into a parity check matrix H matrix, judging whether the number of rows of the H matrix is the same as the preset number of rows, if the number of rows of the H matrix is different from the preset number of rows, converting the number of rows of the H matrix into the preset number of rows, acquiring an updated H matrix, and performing iterative decoding by adopting the updated H matrix.

2. The decoder of claim 1, wherein if the number of rows of the H matrix is greater than the preset number of rows, the CNU converts the number of rows of the H matrix to the preset number of rows, including:

combining two non-overlapping rows of corresponding position data in the H matrix into one row, wherein the two non-overlapping rows of the corresponding position data indicate that the non-empty position of the data content in one row is empty at the position corresponding to the other row; or,

if the number of rows of the H matrix is less than the preset number of rows, the CNU converts the number of rows of the H matrix into the preset number of rows, including:

and supplementing the row number for the H matrix to reach the preset row number, wherein the supplemented intra-row data is the subset of each row in the original H matrix or the linear summation of the subsets of each row in the original H matrix.

3. The transcoder of claim 1, wherein each VNU comprises 4 inputs and outputs, wherein the corresponding CNU comprises 16 inputs and 16 outputs, and wherein the H matrix comprises 16 data per row;

the step of performing iterative decoding by the CNU using the updated H matrix specifically includes:

the CNU is specifically configured to determine minimum absolute value and second-smallest absolute value data in all input data in the LDPC code to be decoded received by the 16 inputs after the operation, form a new H matrix by using the minimum absolute value and second-smallest absolute value data, and send the new H matrix to the corresponding 4 VNUs through the interconnection module;

and the VNU is used for receiving the corresponding sub-matrixes in the new H matrix, summing the data respectively received by the 4 inputs, subtracting the data corresponding to the input from the summation result to obtain new data, combining the new data to form a new sub-matrix, sending the new sub-matrix to the CNU through the interconnection module, and sequentially and circularly finishing iterative decoding.

4. The decoder according to claim 3, wherein the CNU determines the data with the smallest absolute value and the second smallest absolute value in all the input data in the LDPC code to be decoded after the operation received by the 16 inputs in turn, specifically:

if the 16 data belonging to the same row in the updated H matrix are merged data of two rows of data in the original H matrix, the CNU is used for determining the data with the minimum absolute value and the second minimum absolute value in the two rows of data in the original H matrix respectively, wherein the first 8 inputs in the 16 inputs correspond to the first row of data in the two rows of data in the original H matrix, and the last 8 inputs in the 16 inputs correspond to the second row of data in the two rows of data in the original H matrix; or,

if the 16 data belonging to the same row in the updated H matrix are also the same row data in the original H matrix, the CNU determines the data with the minimum absolute value and the second minimum absolute value among the 16 data, wherein the 16 inputs correspond to the 16 data in sequence.

5. The decoder of claim 3, further comprising: a decision module;

the VNU is connected with the judgment module and is used for sending the new sub-matrix to the judgment module after the new data are combined to form a new sub-matrix;

and the judging module is used for judging whether iterative decoding is finished according to the new sub-matrix, and if not, feeding back iteration unfinished information to the VNU so that the VNU sends the new sub-matrix to the CNU according to the iteration unfinished information.

6. The transcoder of any of claims 3-5, wherein the interconnection module is configured to, when receiving the new H matrix sent by the CNU, shift an originally stored H matrix corresponding to the CNU to store the new H matrix, and send the new H matrix to the corresponding VNU; accordingly, the number of the first and second electrodes,

the interconnection module is configured to, when receiving the new sub-matrix sent by the VNU, shift the originally stored sub-matrix corresponding to the VNU to store the new sub-matrix, and send the new sub-matrix to the corresponding CNU.

7. A method for decoding an LDPC code, comprising:

8. The method of claim 7, wherein converting the number of rows of the H matrix into the preset number of rows if the number of rows of the H matrix is different from the preset number of rows comprises:

if the number of rows of the H matrix is greater than the preset number of rows, combining two non-overlapping rows of corresponding position data in the H matrix into one row, wherein the two non-overlapping rows of corresponding position data indicate that the position content of a non-empty position of one row of data content is empty in the position content corresponding to the other row; or,

and if the row number of the H matrix is less than the preset row number, performing row number supplement on the H matrix to achieve the preset row number, wherein the supplemented row number data is the subset of the rows in the original H matrix or the linear summation of the subsets of the rows in the original H matrix.