CN101834614A - Multielement LDPC code coding method and device capable of saving storage resource - Google Patents

Abstract

The invention discloses a multielement LDPC code coding device which mainly solves the problem that the existing multielement LDPC code coding device has high complexity and occupies more storage resources. The device comprises a load module, a variable node updating module, a verification node updating module, a route module, an unload module and a control logic module, wherein the load module receives and stores a demodulation information vector output by a demodulator; the variable node updating module reads data from the load module and the route module and updates all variable nodes; the verification node updating module reads an information vector from the route module and updates a verification node; the route module stores the mutually transmitted information of the variable node and the verification node as well as the interconnection relation between the variable node and the verification node; the unload module verifies the coding result and outputs information; and the control logic module sends a control signal to each module. The invention utilizes iteration time differences to save 50% of overall storage resources so as to realize low requirement and high efficiency of the coding device for the storage resources.

Description

Save the multielement LDPC code coding method and the device of storage resources

Technical field

The present invention relates to communication system, belong to the fec arrangement in the digital communication system, a kind of interpretation method of multielement LDPC code particularly is provided, can in being the communication system of multielement LDPC code, adopt channel coding method, being particularly useful for the adaptive coding modulation is the system of broadband wireless communication of core, to satisfy the requirement of high-speed and high-efficiency.

Background technology

The LDPC sign indicating number is that a class check matrix is the linear block codes of sparse matrix, is proposed in 1962 by Gallager the earliest, and decoder has used the iterative decoding algorithm of low complex degree.Owing to be subjected to the restriction of computing capability at that time, the LDPC sign indicating number once once had been considered to a kind of impracticable sign indicating number, was ignored by people in very long a period of time.To the develop rapidly of appearance, particularly level of hardware of Turbo code at the beginning of the nineties in last century, the excellent properties of LDPC sign indicating number just is familiar with by people again.1996, the LDPC long code that MacKay and Neal point out to have the random configuration of linear decoding complexity can be equal to Turbo code.Luby in 1997 etc. have expanded the regular LDPC sign indicating number of Gallager, have proposed the more superior irregular LDPC codes of performance.At present, most of research work and patent of invention are at binary LDPC sign indicating number.Some structural type binary ldpc decoders with high speed, fast decoding algorithm, low memory demands have been widely applied in the various communication systems, as 3GPP2,802.16e, 802.11n or the like.

1998, Davey and MacKay studied multielement LDPC code, and the result shows that its performance is better than binary LDPC sign indicating number, but this is to exchange for bigger coding and decoding complexity.2005, people such as Shu Lin proposed severally to construct the method for polynary quasi-cyclic LDPC code based on finite field, and its coding gain surpasses the RS sign indicating number that adopts identical code length and code check under the algebraic decoding algorithm.

Compare with binary LDPC sign indicating number, multielement LDPC code not only have a better error-correcting performance, and the antiburst error ability strong, be fit to high rate data transmission.But the research work of existing multielement LDPC is done lessly relatively, has a lot of problems: comprise higher memory space and complicated aspects such as cataloged procedure.Especially on the decoding problem of multielement LDPC code, the territory at multielement LDPC symbol place is GF (q), wherein q=2 ^mBecause the multielement LDPC code decoding algorithm is on symbol level, so the implementation complexity of the sum-product algorithm of standard can increase sharply along with the increase of m.On the other hand,, wish to increase m again, therefore just formed the disequilibrium of multielement LDPC code between decoding algorithm complexity and error-correcting performance for improving the burst-correcting ability of multielement LDPC code.

Summary of the invention

The objective of the invention is in order to overcome the deficiencies in the prior art, a kind of multielement LDPC code coding method and equipment of saving storage resources is provided, balance with decoding complexity and error-correcting performance in the realization multielement LDPC code, under the decoding complexity fixation case, reduction is to the high power capacity demand of memory space in the decoding equipment, so that make the multielement LDPC code on GF (q) territory obtain better application in real system.

For achieving the above object, the present invention proposes a kind of multielement LDPC decoder of saving storage resources, comprising:

Load-on module is used for receiving and storing soft information;

The variable node update module, be used to receive the check-node information transmitted and with it by super column operations, upgrade the information of variable node, and the self information after will upgrading is transferred to the check-node update module;

The check-node update module, be used to receive the variable node information transmitted and with it by the computing of being out of the line, upgrade the information of check-node, and the message transmission after will upgrading is to the variable node update module;

Routing module, the interconnected information that is used for storing check matrix H variable node and check-node, the operation relation when being transferred to variable node update module and check-node update module as iteration;

Unload module is used to receive and adjudicate every information sequence c that takes turns after variable node update module interative computation is finished, if cH ^T=0 sets up, and then the information bit among the decode results c is exported; If reach maximum iteration time, cH no matter ^TWhether=0 set up, and all the information bit among the decode results c will be exported;

Control logic module is used for to described each module communicating control information it being under the normal work schedule, guarantees the correctness that data flow.

For achieving the above object, a kind of multielement LDPC interpretation method of saving storage resources that the present invention proposes comprises the steps:

(1) load-on module receives and stores the demodulating information vector of transferring device output;

(2) the variable node update module reads the demodulating information vector from load-on module, and with the n in the vector _mIndividual big real-valued and corresponding thresholding passes to check-node, n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place;

(3) the check-node update module reads information vector from routing module, at first information vector is done the thresholding displacement, do contrary thresholding displacement afterwards to the information vector computing of being out of the line, and to operation result, at last operation result is inserted the memory space in the routing module;

(4) the variable node update module reads information vector from routing module, surpass column operations after, operation result is inserted memory space in the routing module, and will upgrade the back all the decoding sequence c that forms of variable node information pass to Unload module;

(5) Unload module is adjudicated decoding sequence c, if satisfy cH ^T=0 or reach maximum iteration time, then will decipher the information bit output in the sequence, and write down current round iterations; Otherwise, forward step (3) to.

Technological merit of the present invention is:

1) between initializing variable node updates module and check-node update module, during the memory space depth vector, only stores the part value m in the confinement exponent number q value, can save very big storage resources.Utilize method of the present invention, be reduced to originally 1/2 as the degree of depth that will store vector, can save 25% of total storage resources.

2) utilize variable node update module and the iteration time of check-node update module in the process of iterative computation poor, can only need a memory space to be used for the operation result of storage of variables node updates module and check-node update module in realization.Any module with the data in the single port memory space take out carry out related operation after, the data that computing draws are backfilled to respectively in the identical address in the former same memory space, can be used for another module and carry out next interative computation and insert data.Because variable node update module and check-node update module need data quantity stored very big in the process of iterative computation, adopt method of the present invention can reduce the required storage resources of interative computation greatly.Under the situation that storage resources is fixed, the storage resources under saving can be distributed to the table tennis memory space in the load-on module, so that receive and store the softer information of multiframe.If do not distribute to load-on module, single the method can reduce 25% of total storage resources again.

In sum, adopt decoding equipment proposed by the invention and implementation method can save 50% of storage resources aggregate demand, therefore implementation method of the present invention has bigger practical significance.

Description of drawings

Fig. 1 is a multielement LDPC code translator general structure schematic diagram of the present invention;

Fig. 2 is the load-on module memory construction schematic diagram in the multielement LDPC code translator of the present invention;

Fig. 3 is a variable node update module structural representation in the multielement LDPC code translator of the present invention;

Fig. 4 is a descending device structural representation in the multielement LDPC code translator of the present invention;

Fig. 5 is a verification node updates modular structure schematic diagram in the multielement LDPC code translator of the present invention;

Fig. 6 is that there is storage organization schematic diagram in the module on the road in the multielement LDPC code translator of the present invention;

Fig. 7 is a multielement LDPC interpretation method flow chart of the present invention;

Fig. 8 is the multielement LDPC code check matrix partitioned organization schematic diagram that the present invention adopts.

Embodiment

With reference to Fig. 1, multielement LDPC code translator of the present invention mainly is made up of load-on module, variable node update module, check-node update module, routing module, control logic module and Unload module.Wherein:

Load-on module is used for receiving and storing soft information, reads for the variable node update module.The structure of this module as shown in Figure 2, its memory space zone is divided into two parts RAM1 and the RAM2 of identical size, distinguish the highest order that these two parts mainly depend on write address W_ADD or read address R_ADD, highest order is 0 o'clock, be illustrated in RAM1 is partly carried out the write or read operation, otherwise, then be illustrated in RAM2 partly carried out the write or read operation.When RAM1 is partly write data buffering, read the RAM2 partial data and decipher; When RAM2 is partly write data buffering, read the RAM1 partial data and decipher; The work of reading when so alternately finishing the buffer-stored of data and iterative decoding.Here be noted that decoding, need be to writing memory space again to liking the multielement LDPC code on GF (q) territory after the data descending.Finish frame data bufferings, promptly write the RAM1 part after, send a memory location address information and receive signal and give control logic module.Send the decoding commencing signal by control logic module; Simultaneously write address is pointed to RAM2, be about to the soft information cache of an ensuing frame and go into the RAM2 part; Read the address and point to RAM1, promptly wait for the soft information of next frame and begin the decoding of the soft information of this frame.

The variable node update module, be used to realize that initialization, variable node upgrade and three functions of decoding judgement, the data that it needs are the initial soft information of storing in the load-on module from two aspects on the one hand, are the information that check-node passes to variable node on the other hand.This variable node update module is only being carried out initialization in the iteration first, and each iteration is afterwards only carried out variable node renewal and decoding judgement.Described function of initializing only need be with the n in the initial soft information vector _mIndividual big real-valued and corresponding thresholding passes to check-node, wherein, and n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place.Described variable node update functions need calculate the information vector that all variable nodes pass to check-node, the calculating that wherein a certain variable node passes to the information vector of coupled check-node needs two parts information vector, a part is the information vector that the check-node that links to each other with this variable node except that this check-node transmits, and another part is an initial solution adjusting information vector vector.The process that these information vectors is surpassed column operations is: at first therefrom optional two information vectors are as the input of super column operations, two of each super column operations afterwards are input as the result of previous operation and the information vector that any one had neither part nor lot in computing, so all participated in super column operations, and the result of super column operations for the last time passes to corresponding check-node until all information vectors.The structure of super column operations as shown in Figure 3, its two input vector MEM_VI and MEM_VA comprise real-valued vectorial R respectively _VIAnd R _VAAnd corresponding thresholding vector α _VIAnd α _VA, be output as vectorial R _VBAnd corresponding thresholding vector α _VB, all vector lengths are n _m, n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place, and concrete operation is as follows:

for?all(j?from?0?to?n _m-1)do

if(α _VI[j]∈α _VA)then

k：α _VA[k]＝α _VI[j]

$S\⇐\left\{R_{\mathrm{VI}}\right[j]+R_{\mathrm{VA}}[k],{\mathrm{\α}}_{\mathrm{VI}}[j\left]\right\}$

else

$S\⇐\left\{R_{\mathrm{VI}}\right[j]+\mathrm{\γ},{\mathrm{\α}}_{\mathrm{VI}}[j\left]\right\}$

end?if

end?for

for?all(i?from?0?to?n _m-1)do

$\mathrm{if}\left({\mathrm{\α}}_{\mathrm{VA}}\right[i]\∉S)\mathrm{then}$

$S\⇐\left\{R_{\mathrm{VA}}\right[i]+\mathrm{\γ},{\mathrm{\α}}_{\mathrm{VA}}[i\left]\right\}$

end?if

end?for

In the following formula Be meant data are sent into sorting unit.The structure of this sorting unit as shown in Figure 4, it comprises n _m≤ q comparator and register, q is the size in GF (q) territory at multielement LDPC code place, whether each register root is upgraded according to the real-valued comparative result decision of the real-valued and register of input, if the input real-valued greater than the real-valued of this register and less than its left side register value, then input is updated to the value of this register, if the input real-valued greater than the real-valued of this register and greater than its left side register value, then the value with its left side register is updated to the value of this register, otherwise does not upgrade this register.Described decoding decision function is that maximum real-valued corresponding thresholding and passes to Unload module with c as court verdict c among the information vector of all check-node transmission that will link to each other with variable node and the result that demodulating information vector vector surpasses column operations.

The check-node update module, be used to finish thresholding displacement, check-node renewal and three functions of contrary thresholding displacement, the thresholding that it at first docks in the breath vector of collecting mail is done the thresholding displacement, calculate the information vector that check-node passes to variable node afterwards, finally the thresholding in the information vector of transmitting is done contrary thresholding displacement.Described thresholding permutation function is that the thresholding that receives in the vector is done territory comultiplication computing with its thresholding corresponding in check matrix, and cover the thresholding that receives in the vector with operation result, in order to reduce territory comultiplication computing, thresholding in the check matrix and all elements on the territory are done the territory comultiplication one by one, the result is stored among the ROM, then thresholding displacement only need be read the value of storing among the ROM, ROM to read the address identical with the thresholding size that needs to replace.Described check-node update functions need calculate the information vector that all check-nodes pass to variable node, wherein a certain check-node passes to the calculating of the information vector of coupled variable node, the information vector that only needs the variable node that links to each other with this check-node outside this variable node to transmit.To the be out of the line process of computing of these information vectors be: at first therefrom optional two information vectors are as the input of the computing of being out of the line, two of the computing of at every turn being out of the line afterwards are input as the result of previous operation and the information vector that any one had neither part nor lot in computing, so pass to the relevant variable node until all information vectors all participated in being out of the line result of the computing and the computing of will being out of the line for the last time.Be out of the line computing as shown in Figure 5, and its two input vector MEM_CI and MEM_CA comprise real-valued vectorial R respectively _CIAnd R _CAAnd corresponding thresholding vector α _CIAnd α _CA, be output as real-valued vectorial R _CBAnd corresponding thresholding vector α _CB, all vector lengths are n _m, n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place, and concrete operation adopts the following computing of being out of the line:

for?all(i?from?0?to n _m-1)do

$S\⇐\left\{R_{\mathrm{CA}}\right[i]+R_{\mathrm{CI}}[0],{\mathrm{\α}}_{\mathrm{CA}}[i]\⊕{\mathrm{\α}}_{\mathrm{CI}}[0],i,0\}$

end?for

for?all(i?from?0?to?n _m-1)do

i＝indexA[0]

j＝indexI[0]+1

$\mathrm{if}\left({\mathrm{\α}}_{\mathrm{CA}}\right[i]\⊕{\mathrm{\α}}_{\mathrm{CI}}[j]\∉B)\mathrm{then}$

$S\⇐\left\{R_{\mathrm{CA}}\right[i]+R_{\mathrm{CI}}[j],{\mathrm{\α}}_{\mathrm{CA}}[i]\⊕{\mathrm{\α}}_{\mathrm{CI}}[j],i,j\}$

end?if

end?for

In the following formula

Be meant data are sent into order module.Described contrary thresholding permutation function is to division arithmetic on the territory of transmitting thresholding and its corresponding thresholding in check matrix in the information vector, and operation result covers the thresholding of transmitting in the information vector, in order to reduce division arithmetic on the territory, thresholding in the check matrix and all elements on the territory are done division on the territory one by one, and the result is stored among the ROM, then contrary thresholding displacement only need be read the value of storing among the ROM, and the thresholding size of reading in address and the transmission information vector of ROM is identical.

Routing module is used to finish the interconnected information of transmission and two functions in memory allocated space.The function of the interconnected information of described transmission is that the interconnected information between variable node and the check-node is passed to variable node update module and check-node update module respectively.The interconnected information that this routing module passes to the variable node update module comprises two aspect contents, is the check-node number that links to each other with each variable node on the one hand, is the position of each check-node in check matrix H on the other hand; The interconnected information that this routing module passes to the check-node update module comprises two aspect contents, is the variable node number that links to each other with each check-node on the one hand, is the position of each variable node in check matrix H on the other hand.The function in described memory allocated space is to be all the information vector memory allocated zones in the iterative process, concrete rule is: several information vectors that check-node passes to same variable node must be stored in different storage areas, simultaneously, variable node several information vectors of passing to same check-node must be stored in different storage areas.In order to save storage resources, this routing module is stored in identical storage area with the operation result of variable node update module and check-node update module.Storage organization as shown in Figure 6, storage area is divided into continuous basic unit of storage, the degree of depth of each basic unit of storage is n _m, n _m≤ q, q is the size in GF (q) territory at multielement LDPC code place, to reading with storing process of basic unit of storage be: the variable node update module reads information vector and is used for computing from basic unit of storage, the information vector that computing draws is backfilled to same basic unit of storage, the check-node update module just can directly read information vector and carries out computing from basic unit of storage like this, computing is backfilled to operation result same basic unit of storage after finishing equally.

Control logic module is used for the work of each module of scheduling decoder.This Logic control module receives the status signal that other module is returned, and sends control signal corresponding according to different state informations to other module.After one frame demodulating information vector finished receiving, this Logic control module sent " iteration first " signal to the variable node update module; After the variable node update module was finished renewal, this Logic control module sent " verification decode results " signal to Unload module; After the check-node update module was finished renewal, this Logic control module sent " beginning to upgrade " signal to the variable node update module; If Unload module is returned " verification is unsuccessful " signal, this Logic control module sends " beginning computing " signal to check-node, if Unload module is returned " verification succeeds " signal, this Logic control module begins the next frame data are deciphered.

Unload module is used to judge cH ^TWhether=0 set up, if cH ^T=0 establishment or current iteration number of times are maximum iteration time, then the information bit among the c are exported; Otherwise output information not.

With reference to Fig. 7, interpretation method of the present invention comprises the steps:

Step 1, load-on module receive and store the demodulating information vector of transferring device output.

1.1 load-on module receives N demodulating information vector, each demodulating information vector comprises q real number value and corresponding thresholding thereof, and N is the code length of multielement LDPC code, and q is the size in GF (q) territory at multielement LDPC code place;

1.2 load-on module is before storage demodulating information vector, q the real number value that the demodulating information vector will be comprised earlier put into storage area again according to descending.

Step 2, initialization, promptly the variable node update module passes to check-node with the demodulating information vector;

2.1 the variable node update module reads the n of demodulating information vector from load-on module _mIndividual big real-valued and corresponding thresholding, n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place;

2.2 the variable node update module is put into the information vector of reading the storage area of routing module.

Step 3, the check-node update module is finished the renewal of all check-nodes.

3.1, the check-node update module reads j≤N the information vector that check-node is required simultaneously from routing module, to be updated finishing read j the information vector that check-node is required once more simultaneously, all information vectors of storing in routing module all are read out, and N is the code length of multielement LDPC code;

3.2, the check-node update module is done displacement to the thresholding in the information vector that reads, at first information vector in check matrix corresponding thresholding as multiplier, afterwards with information vector in each thresholding on the territory, multiply each other, use the thresholding in the multiplied result coverage information vector at last;

3.3 the check-node update module is calculated the information vector that j check-node passes to variable node simultaneously.A certain check-node passes to the calculating of the information vector of coupled variable node, the information vector that only needs the variable node that links to each other with this check-node outside this variable node to transmit.To the be out of the line process of computing of these information vectors be: at first therefrom optional two information vectors are as the input of the computing of being out of the line, two of the computing of at every turn being out of the line afterwards are input as the result of previous operation and the information vector that any one had neither part nor lot in computing, so all participate in being out of the line the result of the computing and the computing of will being out of the line for the last time as the information vector that passes to variable node until all information vectors;

3.4, the check-node update module is done contrary thresholding displacement to the information vector that passes to variable node, at first this information vector in check matrix corresponding thresholding as divisor, afterwards with information vector in each thresholding on the territory, be divided by, at last with the thresholding in the vector of coverage information as a result that is divided by;

3.5 the check-node update module is put into the memory space of routing module to the information vector that passes to variable node, the information vector that passes to the different check node is put into different storage areas.

Step 4, the variable node update module is finished the renewal of variable node.

4.1, the variable node update module reads i≤N the information vector that variable node is required simultaneously from routing module, to be updated finishing read i the information vector that check-node is required once more simultaneously, all information vectors of storing in routing module all are read out, and N is the code length of multielement LDPC code;

4.2 the variable node update module is upgraded the information vector that i variable node passes to check-node simultaneously.The calculating that wherein a certain variable node passes to the information vector of coupled check-node needs two parts information vector, a part is the information vector that the check-node that links to each other with this variable node except that this check-node transmits, and another part is an initial solution adjusting information vector vector.The process that these information vectors is surpassed column operations is: at first therefrom optional two information vectors are as the input of super column operations, two of each super column operations afterwards are input as the result of previous operation and the information vector that any one had neither part nor lot in computing, so all participated in super column operations, and the result of super column operations for the last time is as the information vector that passes to check-node until all information vectors.

4.3 the variable node update module is put into routing module to the information vector that passes to variable node, and will decipher sequence c and pass to Unload module;

Step 5, verification and output.

5.1, calculate cH ^TAnd judgement cH ^TWhether=0 set up;

5.1, if cH ^T=0 sets up or reaches maximum iteration time, and the information bit that then will decipher in the sequence is exported, and writes down current round iterations; Otherwise, forward step 3 to.

Embodiment

With reference to Fig. 8, the check matrix of the multielement LDPC code on the GF that the embodiment of the invention adopted (64), the code length of this multielement LDPC code are 174 symbols, and code check is 1/2, and oblique line is wherein represented non-zero entry in the matrix.

This check matrix H is divided into 18 identical 29*29 basic matrixs, wherein has the non-zero entry on GF (64) territory in 14 basic matrixs, and the non-zero entry in same basic matrix is unique, and non-zero entry is arranged with accurate loop structure in matrix.

Variable node is divided into six: P0, P1, P2, S0, S1 and S2.Wherein P0, P1 and P2 are check part, and their degree is respectively 2,2 and 1; S0, S1 and S2 are message part, and degree is 3; Non-zero entry on the GF of P0 correspondence (64) territory is 1 and 2; Non-zero entry on the GF of P1 correspondence (64) territory is 1 and 2; Non-zero entry on the GF of P2 correspondence (64) territory is 1; Non-zero entry on the GF of S0 correspondence (64) territory is 6,12 and 5; Non-zero entry on the GF of S1 correspondence (64) territory is 32,48 and 40; Non-zero entry on the GF of S2 correspondence (64) territory is 3,5 and 15.

Check-node is divided into three: H0, H1 and H2, its degree is respectively 4,5 and 5.

The iterative decoding step:

A receives 174 demodulating information vectors by load-on module, and each demodulating information vector comprises 64 real-valued and 64 thresholdings, with real-valued corresponding one by one with thresholding; And 64 real number values that the demodulating information vector is comprised are put into storage area again according to descending;

B, the variable node update module reads 32 big real-valued and corresponding thresholdings of demodulating information vector from load-on module, and the information vector of reading is put into the storage area of routing module;

C, the check-node update module reads the information vector that 3 check-nodes need simultaneously, and 3 check-nodes belong to H0, H1 and H2 respectively, read the information vector that 3 check-nodes need after to be updated the finishing again, and all information vectors of storing in routing module all are read out;

D, the check-node update module is partly done the thresholding displacement to the thresholding in the information vector that reads, here be that example is illustrated only with the information vector of transmitting between check-node among the H0 and the variable node among the P0, non-zero entry on GF (64) territory in check-node among the H0 and the variable node corresponding check matrix among the P0 is 1, thresholding in the information vector that the check-node update module reads all with 1 multiplication of doing on GF (64) territory, the thresholding in the multiplied result coverage information vector;

E, the check-node update module is simultaneously to H0, check-node among H1 and the H2 upgrades, here be that the example that is updated to of the check-node among 4 the H0 is illustrated only with degree, the renewal of this check-node need calculate respectively and pass to P0, S0, the information vector of variable node among S1 and the S2, for example, the computational process that this check-node passes to the information vector of variable node among the P0 is: at first finish the computing of being out of the line from the information vector of S0 and S1, afterwards with operation result with from the information vector of S2 do be out of the line computing and with its result as the information vector that passes to the variable node among the P0;

F, the check-node update module is done contrary thresholding displacement to the information vector that check-node passes to variable node, here the information vector that only passes to the variable node transmission among the P0 with the check-node among the H0 is that example is illustrated, non-zero entry on GF (64) territory in check-node among the H0 and the variable node corresponding check matrix among the P0 is 1, all thresholdings in the information vector are all done division on a GF (64) territory with this non-zero entry, and with original thresholding in the vector of coverage information as a result that is divided by;

G, the check-node update module is put into the renewal result of check-node the memory space of routing module, here the example that is stored as that only passes to the information vector of variable node with the check-node among the H0 is illustrated, check-node among the H0 variable node in P0, S0, S1 and S2 respectively respectively transmits an information vector, the check-node update module is put into the different storage area of routing module to these information vectors, and covers the information vector that the check-node update module has read;

H, the variable node update module reads the information vector that the check-node update module is transmitted from memory space, the check-node update module reads the information vector that 6 variable nodes need simultaneously, and 6 variable nodes belong to P0, P1, P2, S0, S1 and S2 respectively, read the information vector that 6 check-nodes need after to be updated the finishing again, all information vectors of storing in routing module all are read out;

I, the variable node update module is calculated the information vector that above-mentioned 6 variablees pass to check-node simultaneously, here only with degree be 3 S0 in variable node be that example is illustrated, the renewal of this variable node need calculate the information vector that passes to the check-node among H0, H1, the H2 respectively, for example, this check-node passes to the computational process of the information vector of check-node among the H0 and is: at first finish the computing of being out of the line from the information vector of H1 and H2; Afterwards operation result and demodulating information vector are done be out of the line computing and with its result as the information vector that passes to the variable node among the H0; Finish at last from the information vector of H0 and transmission be out of the line computing and with maximum real-valued corresponding thresholding among the result as the decoding court verdict;

J, the variable node update module is put into the renewal result of variable node the memory space of routing module, here the example that is stored as that only passes to the information vector of check-node with the variable node among the S0 is illustrated, variable node among the S0 check-node in H0, H1, H2 respectively respectively transmits an information vector, the check-node update module is put into the different storage area of routing module to these information vectors, and covers the information vector that has read; The decoding sequence c that the variable node update module is formed the decoding court verdict of all variable nodes passes to Unload module;

K calculates cH by Unload module ^TAnd judgement cH ^TWhether=0 set up, if cH ^T=0 sets up or reaches maximum iteration time, and the information bit that then will decipher among the sequence c is exported, and writes down current round iterations; Otherwise iteration is proceeded.

Claims (6)

1. multielement LDPC decoder of saving storage resources comprises:

Load-on module is used to receive and store the demodulating information vector of demodulator output;

The variable node update module, be used to receive the check-node information transmitted and with it by super column operations, operation result deposits memory space in, the depth vector of this memory space is lower than the exponent number of finite field gf (q); Upgrade the information of variable node, and the self information after will upgrading is transferred to the check-node update module;

The check-node update module, be used to receive the variable node information transmitted and with it by the computing of being out of the line, operation result deposits memory space in, the depth vector of this memory space is lower than the exponent number of finite field gf (q); Upgrade the information of check-node, and the self information after will upgrading is transferred to the variable node update module;

Routing module, the interconnected information that is used for storing check matrix H variable node and check-node, the operation relation when being transferred to variable node update module and check-node update module as iteration;

Unload module is used to receive and adjudicate every decoding sequence c that takes turns after variable node update module interative computation is finished, if cH ^T=0 sets up, and then will decipher the information bit output among the sequence c; If reach maximum iteration time, cH no matter ^TWhether=0 set up, all will be with the information bit output among the decoding sequence c;

Control logic module is used for to described each module communicating control information it being under the normal work schedule, guarantees the correctness that data flow.

2. the multielement LDPC code decoding equipment of saving storage resources according to claim 1 is characterized in that: the soft information that load-on module will receive is sent into memory by the numerical value descending.

3. a multielement LDPC interpretation method of saving storage resources comprises the steps:

(1) load-on module receives and stores the demodulating information vector of transferring device output;

(2) the variable node update module reads the demodulating information vector from load-on module, and with the n in the vector _mIndividual big real-valued and corresponding thresholding passes to check-node, n _m≤ q, q are the size in GF (q) territory at multielement LDPC code place;

(3) the check-node update module reads information vector from routing module, at first information vector is done the thresholding displacement, do contrary thresholding displacement afterwards to the information vector computing of being out of the line, and to operation result, at last operation result is inserted the memory space in the routing module;

(4) the variable node update module reads information vector from routing module, surpass column operations after, operation result is inserted memory space in the routing module, and will upgrade the back all the decoding sequence c that forms of variable node information pass to Unload module;

(5) Unload module is adjudicated decoding sequence c, if satisfy cH ^T=0 or reach maximum iteration time, then will decipher the information bit output in the sequence, and write down current round iterations; Otherwise, forward step (3) to.

4. multielement LDPC code coding method according to claim 3 is characterized in that the described check-node update module of step (3) by the computing of being out of the line, and adopts the multidiameter delay structure.

5. multielement LDPC code coding method according to claim 3 is characterized in that the described variable node update module of step (4) by super column operations, adopts the multidiameter delay structure.

6. multielement LDPC code coding method according to claim 3 is characterised in that described check-node update module of step (3) and the described variable node update module of step (4) insert memory space with operation result, fills in according to the following rules:

After arbitrary folk prescription module arithmetic is finished, operation result is backfilled to the data address that participates in the node updates computing in the same memory space;

After arbitrary folk prescription module finished to upgrade computing, the opposing party wiped the content in the memory space and continues to use same memory space to deposit in.

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