CN104851872A - Integrated circuit structure and making method thereof - Google Patents
Integrated circuit structure and making method thereof Download PDFInfo
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- CN104851872A CN104851872A CN201410053488.4A CN201410053488A CN104851872A CN 104851872 A CN104851872 A CN 104851872A CN 201410053488 A CN201410053488 A CN 201410053488A CN 104851872 A CN104851872 A CN 104851872A
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- integrated circuit
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- circuit structure
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Abstract
The invention discloses an integrated circuit structure and a making method thereof, so the short circuit problem between a metal fuse and a substrate can be solved in a metal fusion process; the integrated circuit structure comprises the substrate, an insulation protection layer, the metal fuse and an isolation metal part; the metal fuse, the substrate and the insulation protection layer are all insulated; the isolation metal part is arranged between the metal fuse and the substrate, and insulated from the metal fuse and the substrate; the metal fuse is exposed in a room formed by etching a preset zone of the insulation protection layer; the size of the preset zone is smaller than or equal to the size of one surface, opposite to the insulation protection layer, of the isolation metal part.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of integrated circuit structure and preparation method thereof.
Background technology
In integrated circuits, be usually provided with several metal fuses, metal fuse is the metallic resistance being arranged in integrated circuit.Take specific method, metal fuse can be made to fuse, namely the object of open circuit is reached, and when fusing does not occur metal fuse, it is conducting, namely by not fusing or blown metal fuse, can reach the adjustment function of integrated circuit or the object of parameter, the process of this adjustment is referred to as " trimming ".
(shown in this Fig. 1 is the planar structure schematic diagram of integrated circuit structure as shown in Figures 1 and 2; Figure 2 shows that the sectional drawing of the schematic diagram of planar structure shown in Fig. 1 along AB line) structure; the material that in prior art, integrated circuit structure comprises substrate 101, insulating protective layer 102 and dielectric layer 103(dielectric layer generally adopts silica; for isolating metal layer and substrate), metal fuse 104; wherein metal fuse 104 is bonding jumpers of certain length, width, and metal fuse 104 is between substrate 101 and insulating protective layer 102.For making metal fuse 104 when generation fusing, its metal can fully play, and needs to etch insulating protective layer 102, makes in the exposed space carrying out etching formation to insulating protective layer 102 of metal fuse 104.
Because insulating protective layer 102 etching technics has higher Selection radio to metal level; and it is very low to the Selection radio of dielectric layer 103; therefore in insulating protective layer 102 etching technics; the dielectric layer 103 in the region except metal fuse 104 overlay area also can be etched away in the lump; expose substrate 101, as shown in Figure 2.
When integrated circuit trims, part metals fuse fast by solid state transformed for liquid, be then gaseous state by liquid conversion fast again.In the process, the metal fuse of the overwhelming majority has vapored away in a gaseous form, but also may there is the metal fuse of small part by failing during liquid conversion gaseous state to transform in time, its molten metal penetrates into the surface of substrate, when the molten metal penetrating into substrate surface is more, can be short-circuited between metal fuse and substrate, after making to trim, the qualification rate of integrated circuit declines.
Summary of the invention
Embodiments provide a kind of integrated circuit structure and preparation method thereof, in order to solve in the process of metal fuse fusing, the problem be short-circuited between metal fuse and substrate.
Embodiments provide a kind of integrated circuit structure, this integrated circuit structure comprises:
Substrate, insulating protective layer, metal fuse and isolating metal parts;
This metal fuse and substrate and insulating protective layer all insulate; These isolating metal parts are arranged between metal fuse and substrate, and these isolating metal parts and above-mentioned metal fuse and substrate all insulate;
This metal fuse is exposed to carry out the presumptive area of insulating protective layer etching in the space of formation, and the size of this presumptive area is not more than the isolating metal parts size laminated relative to insulation protection.
Such scheme utilizes between metal fuse and substrate, arranges isolating metal parts, and these isolating metal parts and metal fuse and substrate all insulate, thus when integrated circuit trims, metal fuse by solid state transformed for liquid state be converted into gaseous state again time, even if there is the molten metal of the metal fuse of small part to permeate downwards, also can not touches substrate and cause short circuit between metal fuse and substrate.Improve integrated circuit trim after qualification rate.
Preferably, integrated circuit structure can comprise multiple metal fuse, a predeterminable area of all corresponding isolating metal parts of each metal fuse and corresponding above-mentioned insulating protective layer;
The size of the predeterminable area that each metal fuse is corresponding is not more than isolating metal parts corresponding to this metal fuse size laminated relative to above-mentioned insulation protection.
Preferably, integrated circuit structure comprises multiple metal fuse, a predeterminable area of the corresponding insulating protective layer of each metal fuse, and arranges isolating metal parts;
Comprise the size of the overall area of predeterminable area corresponding to all metal fuses, be not more than the size that isolating metal parts are laminated relative to insulation protection.
Based on above-mentioned any embodiment; preferably; integrated circuit structure includes at least two metal layers between above-mentioned substrate and insulating protective layer; these isolating metal parts are formed by the wherein layer of metal layer of said integrated circuit structure, and this metal fuse is formed by the other layer of metal layer wherein of integrated circuit structure.
Based on above-mentioned any embodiment, preferably, predeterminable area is rectangle.
Based on above-mentioned any embodiment, preferably, isolating metal parts are laminated relative to insulation protection is plane.
Based on above-mentioned any embodiment, preferably, isolating metal parts are laminated relative to insulation protection is curved surface.
Based on the inventive concept same with constructive embodiment, the embodiment of the present invention additionally provides a kind of manufacture method of integrated circuit structure, and the method comprises:
Substrate is formed first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively;
Etch the predeterminable area of insulating protective layer, make in the exposed space formed after etching of metal fuse, the size of this presumptive area is not more than the isolating metal parts size laminated relative to insulation protection.
Such scheme utilizes between metal fuse and substrate, makes isolating metal parts, and these isolating metal parts are all insulated by first medium layer, second dielectric layer and metal fuse and substrate, thus when integrated circuit trims, metal fuse by solid state transformed for liquid state be converted into gaseous state again time, even if there is the molten metal of the metal fuse of small part to permeate downwards, also can not touches substrate and cause short circuit between metal fuse and substrate.Improve integrated circuit trim after qualification rate.
Preferably, substrate is formed first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively, specifically comprises:
Substrate is formed first medium layer, the first metal layer, second dielectric layer, the second metal level and insulating protective layer successively; And the first metal layer comprises isolating metal parts, the second metal level comprises metal fuse.
Accompanying drawing explanation
Fig. 1 is the planar structure schematic diagram of integrated circuit structure in prior art;
Fig. 2 is for the schematic diagram of planar structure shown in Fig. 1 is along the sectional drawing of AB line;
The planar structure schematic diagram of the integrated circuit structure that Fig. 3 provides for the embodiment of the present invention;
Shown in Fig. 3 that Fig. 4 provides for the embodiment of the present invention, planar structure schematic diagram is along the sectional drawing of AB line;
Fig. 5 comprises the first sectional drawing of multiple metal fuse for integrated circuit structure that the embodiment of the present invention provides;
Fig. 6 comprises the second sectional drawing of multiple metal fuse for integrated circuit structure that the embodiment of the present invention provides;
The manufacture method flow chart of the integrated circuit structure that Fig. 7 provides for the embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of integrated circuit structure, in order to solve exist in prior art when integrated circuit trims, metal fuse fusing process in, the problem be short-circuited between metal fuse and substrate.
Below in conjunction with accompanying drawing, embodiments of the present invention is further illustrated.The following drawings is only a kind of example, does not do concrete restriction to structure, shape.
Embodiments provide a kind of integrated circuit structure, as shown in Figure 3 and shown in Fig. 4, this integrated circuit structure comprises:
Substrate 101, insulating protective layer 102, dielectric layer 103, metal fuse 104 and isolating metal parts 105.
This metal fuse 104 all insulate with substrate 101 and insulating protective layer 102.
These isolating metal parts 105 are arranged between metal fuse 104 and substrate 101, and these isolating metal parts 105 all insulate with above-mentioned metal fuse 104 and substrate 101; These isolating metal parts 105 also not any with other current potential are connected.
Metal fuse 104 is exposed to be carried out the presumptive area of insulating protective layer 102 etching in the space of formation, and the size of this presumptive area is not more than the size of isolating metal parts 105 relative to insulating protective layer 102 one side.
Above-mentioned isolating metal parts 105 refer to relative to the size of insulating protective layer 102 one side: isolating metal parts 105 are perpendicular to area insulating protective layer 102 direction projected on insulating protective layer 102.The size of so-called presumptive area is not more than the size of isolating metal parts 105 relative to insulating protective layer 102 one side; refer to that presumptive area falls in the scope of the projection of isolating metal parts 105 on insulating protective layer 102, and projecting direction is the direction perpendicular to insulating protective layer 102.
The size that can arrange predeterminable area equals the size of isolating metal parts 105 relative to insulating protective layer 102 one side; certainly can arrange and be less than the size (as shown in Figure 3, dotted line frame is the actual sizes of isolating metal parts 105 relative to insulating protective layer 102 one side) of isolating metal parts 105 relative to insulating protective layer 102 one side
Preferably, if integrated circuit structure comprises in multiple metal fuse 104(embodiment of the present invention for 3 metal fuses), then isolating metal parts 105 can be set in integrated circuit structure, multiple isolating metal parts 105 also can be set:
The first implementation (corresponding to arranging multiple isolating metal parts 105), as shown in Figure 5: all corresponding isolating metal parts 105 of each metal fuse 104 and corresponding above-mentioned insulating protective layer 102.
The size of the predeterminable area of each metal fuse 104 correspondence is not more than the size of isolating metal parts 105 relative to above-mentioned insulating protective layer 102 one side of this metal fuse 104 correspondence.Thus make the substrate 101 being positioned at predeterminable area be isolated metal parts 105 completely to cover and not exposed.
The second implementation (correspond to and only arrange isolating metal parts 105), as shown in Figure 6: a predeterminable area of the corresponding insulating protective layer 102 of each metal fuse 104, and arranges isolating metal parts 105;
Comprise the size of the overall area of the predeterminable area of all metal fuse 104 correspondences, be not more than the size of isolating metal parts 105 relative to insulating protective layer 102 one side.Thus make the substrate being positioned at predeterminable area be isolated metal parts 105 completely to cover and not exposed.
The third implementation (corresponding to arranging multiple isolating metal parts 105): multiple metal fuse 104 is divided into groups; often organize the corresponding isolating metal parts 105 of metal fuse 104; and the size of the overall area of the predeterminable area of metal fuse 104 correspondence in comprising every group, is not more than the size of isolating metal 105 relative to insulating protective layer 102 one side of this group correspondence.
Such as: the metal fuse of distribution comparatively dense can be divided into one group, can divide into groups as required, the concrete embodiment of the present invention does not do concrete restriction yet.
Preferably, predeterminable area is rectangle (predeterminable area when etching in the structure shown in Fig. 3 is for rectangle).
Based on above-mentioned any embodiment, preferably, this isolating metal parts 105 shape is cuboid (the isolating metal parts 105 shown in Fig. 3 and Fig. 4 is for cuboid).The size of above-mentioned isolating metal parts 105 refers to that isolating metal parts 105 are relative to the length of insulating protective layer 102 rectangular surfaces and width.Thickness in embodiments of the present invention for isolating metal parts 105 does not do concrete restriction.
Certainly these isolating metal parts 105 also can be other structures, and isolating metal parts 105 can be simultaneously curved surfaces relative to insulating protective layer 102 also can be plane.
The structure of the embodiment of the present invention to isolating metal parts 105 is not specifically limited, and only need ensure that the size of isolating metal parts 105 is not less than the size of predeterminable area.
Such scheme utilizes and arrange isolating metal parts 105 between metal fuse 104 and substrate 101, and these isolating metal parts 105 insulate with metal fuse 104 and substrate 101, thus when integrated circuit trims, metal fuse 104 is converted into gaseous state by solid state transformed again for liquid state, even if there is the molten metal of the metal fuse 104 of small part to permeate downwards, also can not touches substrate 101 and cause short circuit between metal fuse 104 and substrate 101.Improve integrated circuit trim after qualification rate.
Based on above-mentioned any embodiment; preferably; integrated circuit structure includes at least two metal layers between above-mentioned substrate 101 and insulating protective layer 102; these isolating metal parts 105 are formed by the wherein layer of metal layer of said integrated circuit structure, and this metal fuse 104 is formed by the other layer of metal layer wherein of integrated circuit structure.
Such as, integrated circuit comprises 2 layers of metal level altogether, if it is 10um that second layer metal layer can be adopted to make metal fuse 104(long, wide is 0.5um), to the predeterminable area of insulating protective layer 102 (for rectangular area in the embodiment of the present invention, length can be set to 9.5um, width is set to 11um) carry out etching in the space of formation, then arrange between metal fuse 104 and substrate 101 in the isolating metal parts 105(embodiment of the present invention formed by first layer metal layer for the isolating metal parts of rectangular structure), isolating metal parts 105 can be set to 15um relative to the length of the rectangular surfaces of insulating protective layer 102, width can be set to 16um.
According to this example, metal fuse 104 can be not exclusively exposed relative to the one side of insulating protective layer 102.
Owing to there is higher Selection radio to the etching technics of insulating protective layer 102 to metal level; and it is low to the selection and comparison of dielectric layer 103; therefore isolating metal parts 105 are set between metal fuse 104 and substrate 101; when preventing from etching the predeterminable area of insulating protective layer 102; dielectric layer 103 is etched until substrate; thus when avoiding trimming metal fuse have solid state transformed for liquid state be converted into gaseous state again time; even if there is the molten metal of the metal fuse 104 of small part to permeate downwards, also can not touches substrate 101 and cause short circuit between metal fuse 104 and substrate 101.Improve integrated circuit trim after qualification rate.
Based on the inventive concept same with constructive embodiment, the embodiment of the present invention additionally provides a kind of integrated circuit structure manufacture method, and as shown in Figure 7, the method comprises:
701: on substrate, form first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively;
702: etch the predeterminable area of insulating protective layer, make in the exposed space formed after etching of metal fuse, the size of this presumptive area is not more than the isolating metal parts size laminated relative to insulation protection.
Such scheme utilizes between metal fuse and substrate, makes isolating metal parts, and these isolating metal parts are all insulated by first medium layer, second dielectric layer and metal fuse and substrate, thus when integrated circuit trims, metal fuse by solid state transformed for liquid state be converted into gaseous state again time, even if there is the molten metal of the metal fuse of small part to permeate downwards, also can not touches substrate and cause short circuit between metal fuse and substrate.Improve integrated circuit trim after qualification rate.
Preferably, substrate is formed first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively, specifically comprises:
Substrate is formed first medium layer, the first metal layer, second dielectric layer, the second metal level and insulating protective layer successively; And the first metal layer comprises isolating metal parts, the second metal level comprises metal fuse.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. an integrated circuit structure, is characterized in that, comprising:
Substrate, insulating protective layer, metal fuse and isolating metal parts:
Described metal fuse and described substrate and described insulating protective layer all insulate;
Described isolating metal parts are arranged between described metal fuse and described substrate, and described isolating metal parts and described metal fuse and described substrate all insulate;
Described metal fuse is exposed to carry out the presumptive area of insulating protective layer etching in the space of formation, and the size of described presumptive area is not more than the described isolating metal parts size laminated relative to described insulation protection.
2. integrated circuit structure as claimed in claim 1, it is characterized in that, described integrated circuit structure comprises multiple metal fuse, a predeterminable area of the corresponding isolating metal parts of each metal fuse and corresponding described insulating protective layer;
The size of the predeterminable area that each metal fuse is corresponding is not more than isolating metal parts corresponding to this metal fuse size laminated relative to described insulation protection.
3. integrated circuit structure as claimed in claim 1, it is characterized in that, described integrated circuit structure comprises multiple metal fuse, a predeterminable area of the corresponding described insulating protective layer of each metal fuse, and arranges isolating metal parts;
Comprise the size of the overall area of predeterminable area corresponding to all metal fuses, be not more than the size that described isolating metal parts are laminated relative to described insulation protection.
4. integrated circuit structure as claimed in claim 1; it is characterized in that; described integrated circuit structure includes at least two metal layers between described substrate and insulating protective layer; described isolating metal parts are formed by the wherein layer of metal layer of described integrated circuit structure, and described metal fuse is formed by the other layer of metal layer wherein of described integrated circuit structure.
5. the integrated circuit structure as described in any one of Claims 1 to 4, is characterized in that, described predeterminable area is rectangle.
6. the integrated circuit structure as described in any one of Claims 1 to 4, is characterized in that, described isolating metal parts are laminated relative to described insulation protection is plane.
7. the integrated circuit structure as described in any one of Claims 1 to 4, is characterized in that, described isolating metal parts are laminated relative to described insulation protection is curved surface.
8. a manufacture method for integrated circuit structure, is characterized in that, comprising:
Substrate is formed first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively;
Etch the predeterminable area of insulating protective layer, make in the exposed space formed after etching of described metal fuse, the size of described presumptive area is not more than the described isolating metal parts size laminated relative to described insulation protection.
9. manufacture method as claimed in claim 8, is characterized in that, describedly on substrate, forms first medium layer, isolating metal parts, second dielectric layer, metal fuse and insulating protective layer successively, specifically comprises:
Substrate is formed first medium layer, the first metal layer, second dielectric layer, the second metal level and insulating protective layer successively; Described the first metal layer comprises isolating metal parts, and described second metal level comprises metal fuse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410053488.4A CN104851872B (en) | 2014-02-17 | 2014-02-17 | A kind of integrated circuit structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410053488.4A CN104851872B (en) | 2014-02-17 | 2014-02-17 | A kind of integrated circuit structure and preparation method thereof |
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| CN104851872A true CN104851872A (en) | 2015-08-19 |
| CN104851872B CN104851872B (en) | 2018-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410053488.4A Active CN104851872B (en) | 2014-02-17 | 2014-02-17 | A kind of integrated circuit structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630664A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Fuse-wires structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372556B1 (en) * | 1999-10-20 | 2002-04-16 | Samsung Electronics Co., Ltd. | Semiconductor device having a fuse and fabricating method therefor |
| US20040080022A1 (en) * | 2002-10-29 | 2004-04-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN1901170A (en) * | 2005-07-21 | 2007-01-24 | 台湾积体电路制造股份有限公司 | Semiconductor device |
-
2014
- 2014-02-17 CN CN201410053488.4A patent/CN104851872B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372556B1 (en) * | 1999-10-20 | 2002-04-16 | Samsung Electronics Co., Ltd. | Semiconductor device having a fuse and fabricating method therefor |
| US20040080022A1 (en) * | 2002-10-29 | 2004-04-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN1901170A (en) * | 2005-07-21 | 2007-01-24 | 台湾积体电路制造股份有限公司 | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630664A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Fuse-wires structure and forming method thereof |
| CN108630664B (en) * | 2017-03-17 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure and forming method thereof |
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| Publication number | Publication date |
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| CN104851872B (en) | 2018-02-13 |
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Effective date of registration: 20220720 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 5 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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