CN104851396A - Buffer circuit, panel module and display driving method - Google Patents

Buffer circuit, panel module and display driving method Download PDF

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Publication number
CN104851396A
CN104851396A CN201410050201.2A CN201410050201A CN104851396A CN 104851396 A CN104851396 A CN 104851396A CN 201410050201 A CN201410050201 A CN 201410050201A CN 104851396 A CN104851396 A CN 104851396A
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China
Prior art keywords
impact damper
positive
negative
source
voltage
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CN201410050201.2A
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CN104851396B (en
Inventor
林介安
卓均勇
程智修
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Novatek Microelectronics Corp
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Novatek Microelectronics Corp
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Priority to CN201410050201.2A priority Critical patent/CN104851396B/en
Priority to CN201710971773.8A priority patent/CN107680547B/en
Publication of CN104851396A publication Critical patent/CN104851396A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Abstract

The invention provides a buffer circuit, a panel module and a display driving method. The buffer circuit comprises a positive buffer and a negative buffer. The positive buffer receives a first power supply voltage and a second power supply voltage so that the positive buffer outputs a positive reference voltage to a positive resistor string. The second power supply voltage is smaller than the first power supply voltage. The negative buffer receives the second power supply voltage and a third power supply voltage, so that the negative buffer outputs a negative reference voltage to a negative resistor string. The third power supply voltage is smaller than the second power supply voltage.

Description

Buffer circuit, panel module and display drive method
Technical field
The present invention relates to a kind of electronic installation, and in particular to a kind of buffer circuit, panel module and display drive method.
Background technology
Along with the universalness of display product, the Related product of the liquid crystal display that is seen everywhere arround life now.To enable liquid crystal display correctly display frame, then the digital signal of image data must be converted to by digital analog converter (Digitalto Analog Converter, DAC) simulating signal being enough to drive liquid crystal molecule.In the process of digital signal revolving die analog signal, digital analog converter must use the gamma reference voltage on several not coordination rank.
Please refer to Fig. 1, Fig. 1 illustrates the schematic diagram into positive polarity resistance string, negative polarity resistance string, positive polarity impact damper and negative polarity impact damper.Because liquid crystal molecule has the consideration of the reverse of polarity, so general driving chip has the voltage that positive polarity resistance string 32 and negative polarity resistance string 33 represent its positive-negative polarity respectively.Positive polarity resistance string 32 and negative polarity resistance string 33 are also called gamma resistance.Voltage on positive polarity resistance string 32 is provided by positive polarity buffer amplifier 35, and the voltage on negative polarity resistance string 33 is provided by negative polarity buffer amplifier 36.
The diverse location of different positive polarity buffer amplifiers 35 on positive polarity resistance string 32 defines its dividing point, and the diverse location of different negative polarity buffer amplifiers 36 on negative polarity resistance string 33 defines its dividing point.Each dividing point enters the output voltage values and the polarity that are determined driving chip in digital analog converter by input signal again.Because resistance value and its current drain are inversely proportional to, general driving chip can exhaust the grade of hundreds of micromicroampere to number milliampere on positive polarity resistance string 32 and negative polarity resistance string 33, whole driving chip current drain face is occupied to the ratio of most.
Summary of the invention
The present invention relates to a kind of buffer circuit, panel module and display drive method.
According to the present invention, a kind of buffer circuit is proposed.Buffer circuit comprises positive polarity impact damper and negative polarity impact damper.Positive polarity buffer inputs first supply voltage and second source voltage, make positive polarity impact damper output cathode reference voltage to positive polarity resistance string.Second source voltage is less than the first supply voltage.Negative polarity buffer inputs second source voltage and the 3rd supply voltage, make negative polarity impact damper output negative pole reference voltage to negative polarity resistance string.3rd supply voltage is less than second source voltage.
According to the present invention, a kind of panel module is proposed.Panel module comprises panel, positive polarity resistance string, negative polarity resistance string, buffer circuit and driving circuit.Buffer circuit comprises positive polarity impact damper and negative polarity impact damper.Positive polarity buffer inputs first supply voltage and second source voltage, make positive polarity impact damper output cathode reference voltage to positive polarity resistance string.Second source voltage is less than the first supply voltage.Negative polarity buffer inputs second source voltage and the 3rd supply voltage, make negative polarity impact damper output negative pole reference voltage to negative polarity resistance string.3rd supply voltage is less than second source voltage.Driving circuit drives panel according to the first reference voltage and the second reference voltage.
According to the present invention, a kind of display drive method is proposed.Display drive method comprises: the first supply voltage needed for supply positive polarity impact damper and second source voltage, and make positive polarity impact damper output cathode reference voltage, second source voltage is less than the first supply voltage; Second source voltage needed for supply negative polarity impact damper and the 3rd supply voltage, make negative polarity impact damper output negative pole reference voltage, the 3rd supply voltage is less than second source voltage; And drive panel according to positive polarity reference voltage and negative polarity reference voltage.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the schematic diagram into positive polarity resistance string, negative polarity resistance string, positive polarity impact damper and negative polarity impact damper.
Fig. 2 illustrates the schematic diagram into a kind of panel module according to the first embodiment.
Fig. 3 illustrates the schematic diagram into a kind of buffer circuit according to the first embodiment.
Fig. 4 illustrates as positive polarity resistance string couples three positive polarity impact dampers and negative polarity resistance string couples the schematic diagram of three negative polarity impact dampers.
Fig. 5 illustrates the schematic diagram into a kind of buffer circuit according to the second embodiment.
Fig. 6 illustrates the schematic diagram into a kind of panel module according to the 3rd embodiment.
Fig. 7 illustrates as coupling n positive polarity impact damper according to m positive polarity resistance string of the 4th embodiment and m negative polarity resistance string couples the schematic diagram of n negative polarity impact damper.
Fig. 8 illustrates as a kind of schematic diagram being provided supply voltage VMID by supply voltage output circuit according to the 5th embodiment.
Fig. 9 illustrates the schematic diagram into a kind of panel module according to the 6th embodiment.
Figure 10 illustrates the schematic diagram into a kind of panel module according to the 7th embodiment.
Figure 11 illustrates the process flow diagram into a kind of display drive method according to the 8th embodiment.
[symbol description]
1,3: panel module
8: source driving chip
81: resistance string
11: panel
12,12a, 32: positive polarity resistance string
13,13a, 33: negative polarity resistance string
14a, 14b, 14c: buffer circuit
15,15a ~ 15n, 35: positive polarity impact damper
16,16a ~ 16n, 36: negative polarity impact damper
16: negative polarity impact damper
17: driving circuit
141: supply voltage output circuit
151,152,161,162: power end
153,163: output terminal
154: positive input level
155: positive output level
156,166: selector switch
164: negative input level
165: negative output level
201 ~ 203: step
1411: middle compression buffer
1541,1542,1641,1642: current source
1543,1544,1545,1546,1643,1644,1645,1646: input transistors
C m: electric capacity
GOP: impact damper
VDD, VMID, VGND: supply voltage
VIP, VIP1 ~ VIPn, VIN, VIN1 ~ VINn: input voltage
VPG: positive polarity reference voltage
VNG: negative polarity reference voltage
P9A, N9A, P9B, N9B, P9C, N9C, P9P, N9P, P9N, N9N: output transistor
I 1, I 2, I 3, I 4, I a, I b, I c, I d, I e, I f, I aP~ I nP, I aN~ I nN, I 1P~ I np, I 1N~ I nN: electric current
R 1, R 2, R 1P~ R nP, R 1N~ R nN: divider resistance
Embodiment
First embodiment
Illustrate the schematic diagram into a kind of panel module according to the first embodiment referring to Fig. 2 and Fig. 3, Fig. 2, Fig. 3 illustrates the schematic diagram into a kind of buffer circuit according to the first embodiment.Panel module 1 comprises panel 11, positive polarity resistance string 12, negative polarity resistance string 13, buffer circuit 14a and driving circuit 17.Positive polarity resistance string 12 and negative polarity resistance string 13 are such as gamma resistance.Buffer circuit 14a comprises positive polarity impact damper 15 and negative polarity impact damper 16.Positive polarity impact damper 15 and negative polarity impact damper 16 are such as gamma operational amplifier (Gamma OP).Driving circuit 17 is such as source driving chip.
Positive polarity impact damper 15 receives supply voltage VDD and supply voltage VMID, makes positive polarity impact damper 15 according to input voltage VIP output cathode reference voltage VPG to positive polarity resistance string 12.Supply voltage VMID is less than supply voltage VDD.Negative polarity impact damper 16 receives supply voltage VMID and supply voltage VGND, makes negative polarity impact damper 16 according to input voltage VIN output negative pole reference voltage VNG to negative polarity resistance string 13.Supply voltage VGND is less than supply voltage VMID, and supply voltage VGND equals ground voltage in fact.That is supply voltage VMID is between supply voltage VDD and supply voltage VGND.Driving circuit 17 drives panel 11 according to positive polarity reference voltage VPG and negative polarity reference voltage VNG.
Furthermore, positive polarity impact damper 15 comprises power end 151, power end 152, output terminal 153, positive input level 154 and positive output level 155.Power end 151 receives supply voltage VDD, and power end 152 receives supply voltage VMID.Output terminal 153 is coupled to positive polarity resistance string 12.Positive input level 154 couples positive output level 155.Power end 151 and power end 152 are coupled to positive output level 155, to supply supply voltage VDD needed for positive polarity impact damper 15 and supply voltage VMID.Negative polarity impact damper 16 comprises power end 161, power end 162, output terminal 163, negative input level 164 and negative output level 165.Power end 161 receives supply voltage VMID, and power end 162 receives supply voltage VGND.Output terminal 163 is coupled to negative polarity resistance string 13.Negative input level 164 couples negative output level 165.Power end 161 and power end 162 are coupled to negative output level 165, to supply supply voltage VMID needed for negative polarity impact damper 16 and supply voltage VGND.
Positive output level 155 comprises output transistor P9P and output transistor N9P, and output transistor N9P couples output transistor P9P.Power end 151 is coupled to the source electrode of output transistor P9P to supply supply voltage VDD to positive output level 155.Power end 152 is coupled to the source electrode of output transistor N9P to supply supply voltage VMID to positive output level 155.Negative output level 165 comprises output transistor P9N and output transistor N9N, and output transistor N9N couples output transistor P9N.Power end 161 couples the source electrode of output transistor P9N to supply supply voltage VMID to negative output level 165.Power end 162 couples the source electrode of output transistor N9N to supply supply voltage VGND to negative output level 165.When positive output level 155 is identical with the size of current of negative output level 165, then there is the effect that electric current re-uses.
Please refer to Fig. 4, Fig. 4 illustrates as positive polarity resistance string couples three positive polarity impact dampers and negative polarity resistance string couples the schematic diagram of three negative polarity impact dampers.Positive polarity impact damper 15a, positive polarity impact damper 15b and positive polarity impact damper 15c respectively according to input voltage VIP1, input voltage VIP2 and input voltage VIP3 output cathode reference voltage VPG1, positive polarity reference voltage VPG2 and positive polarity reference voltage VPG3 to positive polarity resistance string 12.Negative polarity impact damper 16a, negative polarity impact damper 16b and negative polarity impact damper 16c respectively according to input voltage VIN 1, input voltage VIN 2 and input voltage VIN 3 output negative pole reference voltage VNG1, negative polarity reference voltage VNG2 and negative polarity reference voltage VNG3 to negative polarity resistance string 13.
Positive polarity impact damper 15a comprises output transistor P9A and output transistor N9A.Positive polarity impact damper 15b comprises output transistor P9B and output transistor N9B.Positive polarity impact damper 15c comprises output transistor P9C and output transistor N9C.Negative polarity impact damper 16a comprises output transistor P9D and output transistor N9D.Negative polarity impact damper 16b comprises output transistor P9E and output transistor N9E.Negative polarity impact damper 16c comprises output transistor P9F and output transistor N9F.
Positive polarity resistance string 12 comprises divider resistance R 1and divider resistance R 2, and divider resistance R 1couple divider resistance R 2.Negative polarity resistance string 13 comprises divider resistance R 1and divider resistance R 2, and divider resistance R 1couple divider resistance R 2.Positive polarity impact damper 15a, positive polarity impact damper 15b, positive polarity impact damper 15c, negative polarity impact damper 16a, negative polarity impact damper 16b and negative polarity impact damper 16c be output current I respectively a, electric current I b, electric current I c, electric current I d, electric current I e, and electric current I f.Electric current I 1and electric current I 2flow through the divider resistance R of positive polarity resistance string 12 respectively 1and divider resistance R 2.Electric current I 3and electric current I 4flow through the divider resistance R of negative polarity resistance string 13 respectively 2and divider resistance R 1.
Positive polarity resistance string 12 can take out a road electric current I from supply voltage VDD a, electric current I aflow through positive polarity resistance string 12 via output transistor P9A and flow to supply voltage VMID by output transistor N9C again.Negative polarity resistance string 13 can take out a road electric current I from supply voltage VMID d, electric current I dflow through negative polarity resistance string 13 via output transistor P9D and flow to supply voltage VGND by output transistor N9F again.If positive polarity resistance string 12 is identical with the resistance of negative polarity resistance string 13, and positive polarity resistance string 12 is identical with the head and the tail both end voltage difference of negative polarity resistance string 13, then the voltage of positive polarity resistance string 12 and electric current and negative polarity resistance string 13 symmetrical.Under all operating in the framework of supply voltage VDD and supply voltage VGND compared to positive polarity impact damper 15a, positive polarity impact damper 15b, positive polarity impact damper 15c, negative polarity impact damper 16a, negative polarity impact damper 16b and negative polarity impact damper 16c, the present embodiment can save the electric current of about half.If positive polarity resistance string 12 with negative polarity resistance string 13 asymmetric or bias point is inconsistent time, then has a road electric current and make up the gap from supply voltage VMID, or unnecessary electric current flows out from supply voltage VMID.No matter therefore whether positive polarity resistance string 12 is identical with the resistance of negative polarity resistance string 13, no matter also whether positive polarity resistance string 12 is identical with the head and the tail both end voltage difference of negative polarity resistance string 13, above-described embodiment all can reach the object of low-power consumption.
Second embodiment
The schematic diagram into a kind of buffer circuit according to the second embodiment is illustrated referring to Fig. 2 and Fig. 5, Fig. 5.Second embodiment and the first embodiment main difference part are that power end 151 and power end 152 are coupled to the positive input level 154 of buffer circuit 14b, to supply supply voltage VDD needed for positive polarity impact damper 15 and supply voltage VMID.Power end 161 and power end 162 are coupled to the negative input level 164 of buffer circuit 14b, to supply supply voltage VMID needed for negative polarity impact damper 16 and supply voltage VGND.
Positive input level 154 comprises current source 1541, current source 1542, input transistors 1543, input transistors 1544, input transistors 1545 and input transistors 1546.Input transistors 1543 and input transistors 1544 are coupled to current source 1541, and input transistors 1545 and input transistors 1546 are coupled to current source 1542.Power end 152 couples current source 1541 to supply supply voltage VMID to positive input level 154.Power end 151 is coupled to current source 1542 to supply supply voltage VDD to positive input level 154.
Negative input level 164 comprises current source 1641, current source 1642, input transistors 1643, input transistors 1644, input transistors 1645 and input transistors 1646.Input transistors 1643 and input transistors 1644 are coupled to current source 1641, and input transistors 1645 and input transistors 1646 are coupled to current source 1642.Power end 162 couples current source 1641 to supply supply voltage VGND to negative input level 164.Power end 161 couples current source 1642 to supply supply voltage VMID to negative input level 164.
3rd embodiment
Please refer to Fig. 6, Fig. 6 illustrates the schematic diagram into a kind of panel module according to the 3rd embodiment.3rd embodiment and the first embodiment main difference part are: the buffer circuit 14c of panel module 3 also comprises selector switch 156 and selector switch 166.Selector switch 156 exports supply voltage VMID or supply voltage VGND to positive polarity impact damper 15, and selector switch 166 exports supply voltage VMID or supply voltage VDD to negative polarity impact damper 16.When selector switch 156 output supply voltage VMID is to positive polarity impact damper 15, and selector switch 166 output supply voltage VMID is to negative polarity impact damper 16, then can reach the object of low-power consumption.
4th embodiment
Please refer to Fig. 7, Fig. 7 illustrates as coupling n positive polarity impact damper according to m positive polarity resistance string of the 4th embodiment and m negative polarity resistance string couples the schematic diagram of n negative polarity impact damper.Positive polarity impact damper 15a to positive polarity impact damper 15n is respectively according to input voltage VIP1 to input voltage VIPn output cathode reference voltage VPG1 to positive polarity reference voltage VPGn to m positive polarity resistance string 12a.The positive integer that n and m is greater than 1.Positive polarity resistance string 12a comprises divider resistance R 1Pto divider resistance R nP, and m positive polarity resistance string 12a is in parallel mutually.Negative polarity impact damper 16a to negative polarity impact damper 16n is respectively according to input voltage VIN 1 to input voltage VIN n output negative pole reference voltage VNG1 to negative polarity reference voltage VNGn to m negative polarity resistance string 13a.Negative polarity resistance string 13a comprises divider resistance R 1Nto divider resistance R nN, and m negative polarity resistance string 13a is in parallel mutually.Positive polarity impact damper 15a to positive polarity impact damper 15n and negative polarity impact damper 16a to negative polarity impact damper 16n is output current I respectively aPto I nPand electric current I aNto electric current I nN.Electric current I 1Pto I nPflow point piezoresistance R respectively 1Pto R nP.Electric current I 1Nto I nNflow through divider resistance R respectively 1Nto R nN.
5th embodiment
Please refer to Fig. 7 and Fig. 8, Fig. 8 illustrates as a kind of schematic diagram being provided supply voltage VMID by supply voltage output circuit according to the 5th embodiment.5th embodiment and the 4th embodiment main difference part are that the buffer circuit of the 5th embodiment also comprises supply voltage output circuit 141.Supply voltage output circuit 141 comprises middle compression buffer 1411 and electric capacity C m.So its implementation is not limited to this, and in other embodiments, supply voltage output circuit 141 also can be realized by linear voltage regulator (Low Drop Out, LDO) or buck converter (Back Converter).
6th embodiment
Please refer to Fig. 2 and Fig. 9, Fig. 9 illustrates the schematic diagram into a kind of panel module according to the 6th embodiment.Be built in source driving chip 8 in the resistance string 81 that aforementioned positive electrode resistance string and negative polarity resistance string can illustrate as Fig. 9, and be built in source driving chip 8 in aforementioned positive electrode impact damper and the negative polarity impact damper impact damper GOP that can illustrate as Fig. 9.
7th embodiment
Please refer to Fig. 2 and Figure 10, Figure 10 illustrates the schematic diagram into a kind of panel module according to the 7th embodiment.Be built in source driving chip 8 in the resistance string 81 that aforementioned positive electrode resistance string and negative polarity resistance string can illustrate as Fig. 9, the impact damper GOP that aforementioned positive electrode impact damper and negative polarity impact damper then can illustrate as Figure 10 not in be built in source driving chip 8.In other words, the impact damper GOP that aforementioned positive electrode impact damper and negative polarity impact damper then can illustrate as Figure 10 is arranged at outside source driving chip 8.
8th embodiment
Please refer to Fig. 2 and Figure 11, Figure 11 illustrates the process flow diagram into a kind of display drive method according to the 8th embodiment.Display drive method comprises the steps: first as shown by step 201, and the supply voltage VDD needed for supply positive polarity impact damper 15 and supply voltage VMID, makes positive polarity impact damper 15 output cathode reference voltage VPG.Then as shown in step 202, the supply voltage VMID needed for supply negative polarity impact damper 16 and supply voltage VGND, makes negative polarity impact damper 16 output negative pole reference voltage VNG.And then as depicted at step 203, panel 11 is driven according to positive polarity reference voltage VPG and negative polarity reference voltage VNG.
In sum, although the present invention is with preferred embodiment openly as above, so itself and be not used to limit the present invention.Those skilled in the art of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the appending claims person of defining.

Claims (16)

1. a buffer circuit, comprising:
One positive polarity impact damper, in order to receive one first supply voltage and a second source voltage, make this positive polarity impact damper export positive polarity reference voltage to positive polarity resistance string, this second source voltage is less than this first supply voltage; And
One negative polarity impact damper, in order to receive this second source voltage and one the 3rd supply voltage, make this negative polarity impact damper export negative polarity reference voltage to negative polarity resistance string, the 3rd supply voltage is less than this second source voltage.
2. buffer circuit, wherein this positive polarity impact damper as claimed in claim 1, comprising:
One first power end, in order to receive this first supply voltage;
One second source end, in order to receive this second source voltage; And
One first output terminal, is coupled to this positive polarity resistance string.
3. buffer circuit, wherein this negative polarity impact damper as claimed in claim 2, comprising:
One the 3rd power end, in order to receive this second source voltage;
One the 4th power end, in order to receive the 3rd supply voltage; And
One second output terminal, is coupled to this negative polarity resistance string.
4. buffer circuit as claimed in claim 3, wherein this positive polarity impact damper also comprises a positive input level and a positive output level, this positive input level couples this positive output level, this first power end and this second source end couple this positive output level, this negative polarity impact damper comprises a negative input level and a negative output level, this negative input level couples this negative output level, and the 3rd power end and the 4th power end couple this negative output level.
5. buffer circuit as claimed in claim 4, wherein this positive output level comprises one first output transistor and one second output transistor, this second output transistor couples this first output transistor, and this first power end couples the source electrode of this first output transistor, this second source end couples the source electrode of this second output transistor, this negative output level comprises one the 3rd output transistor and one the 4th output transistor, 4th output transistor couples the 3rd output transistor, and the 3rd power end couples the source electrode of the 3rd output transistor, 4th power end couples the source electrode of the 4th output transistor.
6. buffer circuit as claimed in claim 3, wherein this positive polarity impact damper also comprises a positive input level and a positive output level, this positive input level couples this positive output level, this first power end and this second source end couple this positive input level, this negative polarity impact damper comprises a negative input level and a negative output level, this negative input level couples this negative output level, and the 3rd power end and the 4th power end couple this negative input level.
7. buffer circuit as claimed in claim 6, wherein this positive input level comprises one first current source, one second current source, one first input transistors, one second input transistors, one the 3rd input transistors and one the 4th input transistors, this first input transistors and this second input transistors are coupled to this first current source, 3rd input transistors and the 4th input transistors are coupled to this second current source, this second source end couples this first current source, this first power end couples this second current source, this negative input level comprises one the 3rd current source, one the 4th current source, one the 5th input transistors, one the 6th input transistors, one the 7th input transistors and one the 8th input transistors, 5th input transistors and the 6th input transistors are coupled to the 3rd current source, 7th input transistors and the 8th input transistors are coupled to the 4th current source, 4th power end couples the 3rd current source, 3rd power end couples the 4th current source.
8. buffer circuit as claimed in claim 1, also comprises:
One first selector switch, in order to export this second source voltage or the 3rd supply voltage to this positive polarity impact damper; And
One second selector switch, in order to export this second source voltage or this first supply voltage to this negative polarity impact damper.
9. buffer circuit as claimed in claim 1, is wherein built in one source pole driving chip in this positive polarity resistance string, this negative polarity resistance string, this positive polarity impact damper and this negative polarity impact damper.
10. buffer circuit as claimed in claim 1, is wherein built in one source pole driving chip in this positive polarity resistance string and this negative polarity resistance string, and this positive polarity impact damper and this negative polarity impact damper not in be built in this source driving chip.
11. buffer circuits as claimed in claim 1, also comprise:
One supply voltage output circuit, in order to provide this second source voltage.
12. buffer circuits as claimed in claim 11, wherein this supply voltage output circuit comprises compression buffer and an electric capacity in one, and this electric capacity couples compression buffer in this.
13. buffer circuits as claimed in claim 11, wherein this supply voltage output circuit is linear voltage regulator (Low Drop Out, LDO).
14. buffer circuits as claimed in claim 11, wherein this supply voltage output circuit is buck converter (Back Converter).
15. 1 kinds of panel modules, comprising:
One panel;
One positive polarity resistance string;
One negative polarity resistance string;
One buffer circuit, comprising:
One positive polarity impact damper, in order to receive one first supply voltage and a second source voltage, make this positive polarity impact damper export a positive polarity reference voltage to this positive polarity resistance string, this second source voltage is less than this first supply voltage; And
One negative polarity impact damper, in order to receive this second source voltage and one the 3rd supply voltage, make this negative polarity impact damper export a negative polarity reference voltage to this negative polarity resistance string, the 3rd supply voltage is less than this second source voltage; And
One drive circuit, in order to drive this panel according to this positive polarity reference voltage and this negative polarity reference voltage.
16. 1 kinds of display drive methods, comprising:
Supply one first supply voltage needed for a positive polarity impact damper and a second source voltage, make this positive polarity impact damper export a positive polarity reference voltage, this second source voltage is less than this first supply voltage;
Supply this second source voltage needed for a negative polarity impact damper and one the 3rd supply voltage, make this negative polarity impact damper export a negative polarity reference voltage, the 3rd supply voltage is less than this second source voltage; And
A panel is driven according to this positive polarity reference voltage and this negative polarity reference voltage.
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