CN103383841B - Reduce the source class drive unit of latch assembly quantity - Google Patents
Reduce the source class drive unit of latch assembly quantity Download PDFInfo
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- CN103383841B CN103383841B CN201310274886.4A CN201310274886A CN103383841B CN 103383841 B CN103383841 B CN 103383841B CN 201310274886 A CN201310274886 A CN 201310274886A CN 103383841 B CN103383841 B CN 103383841B
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Abstract
The present invention proposes a kind of source class drive unit reducing latch assembly quantity, and it comprises a main latch unit and at least one servant's latch unit.Described main latch unit has a transmission lock, one first phase inverter, one second phase inverter, one first activation lock and one second activation lock, and the output terminal of described second phase inverter is connected to the input end of described first phase inverter.Described at least one servant's latch unit has a transmission lock, one the 3rd phase inverter and one the 4th phase inverter.Wherein, when described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described at least one servant's latch unit simultaneously.
Description
Technical field
The present invention relates to source class technical field of driving, espespecially a kind of source class drive unit reducing latch assembly quantity.
Background technology
Fig. 1 is the use schematic diagram of an available liquid crystal display module, and it comprises an application processor (application processor) 110, LCD MODULE 120 and a LCD screen 130.Described application processor 110 can receive a signal signal of video signal from a memory storage (not shown), and is sent to source class drive unit 123 by timing control unit 121 via a data bus 127.Described source class drive unit 123 first by data latching, and coordinates lock level drive unit 125, to drive LCD screen 130, and plays described signal signal of video signal by described LCD screen 130.
Fig. 2 is the Organization Chart of an existing source electrode driving device 123.First controlled via breech lock enable signal (S) and an anti-phase breech lock enable signal (SB) by first order latch unit 210, to capture and the numerical data of D1 ~ D6 on temporary described data bus 127.Then after delivering to second level latch unit 220 again, again through level shifter (level shifter) 230, finally convert the digital voltage of D1 ~ D6 on described data bus 127 to analog voltage by digital to analog converter (DAC) 240 and export.
Fig. 3 is the circuit diagram of an existing latch unit 210,220.When breech lock enable signal (S) be a noble potential VPP, anti-phase breech lock enable signal (SB) be an electronegative potential VGG time, latch unit 210,220 is sampling mode (sample mode), and transistor MPT, MNT can allow the voltage on input end D pass through.When breech lock enable signal (S) be described electronegative potential VGG, anti-phase breech lock enable signal (SB) for described noble potential VPP time, latch unit 210,220 is Holdover mode (hold mode), transistor MPT and MNT closes, in order to forbid that the voltage on input end D passes through, transistor MPHZ and MNHZ conducting simultaneously, by the voltage breech lock passed through time sampling mode (sample mode).But when LCD MODULE resolution increase time in, source lock drive unit 125 uses the quantity of latch unit also by rapid increase.Therefore, still there is the space needing to improve in existing source class drive unit.
Summary of the invention
Technical matters solved by the invention is the source class drive unit providing a minimizing latch assembly quantity, can reduce the number of transistor in source class drive unit, and cpable of lowering power consumption.
According to characteristic of the present invention, the present invention proposes a kind of source class drive unit reducing latch assembly quantity, it comprises: a main latch unit, it has one first transmission lock, one first phase inverter, one second phase inverter connected successively, and the one first activation lock be connected respectively with described second phase inverter and one second activation lock.Described first transmission lock is in order to receive one first input signal, and the output terminal of described second phase inverter is connected to the input end of described first phase inverter.At least one servant's latch unit, each servant's latch unit described has one second transmission lock, one the 3rd phase inverter and one the 4th phase inverter connected successively, the output terminal of described 4th phase inverter is connected to the input end of described 3rd phase inverter, described second transmission lock is in order to receive one second input signal, and described first activation lock is connected described 4th phase inverter respectively with described second activation lock.When described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described at least one servant's latch unit simultaneously.
According to another characteristic of the present invention, the present invention proposes a kind of source class drive unit reducing latch assembly quantity, and it comprises a main latch unit, and it has one first activation lock and one second activation lock.First to N number of servant's latch unit, and described first activation lock and described second activation lock are connected to described first servant's latch unit respectively to described N number of servant's latch unit, described N be greater than 1 integer.Described main latch unit and described first is connected in parallel to N number of servant's latch unit, respectively in order to receive first to N+1 input signal.When described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described first simultaneously to N servant's latch unit.
The present invention's latch unit of falling forward shares the first activation lock and the second activation lock of main latch unit, and servant's latch unit does not need to have activation lock, but still can perform original function.Effectively can save the area of component count and source class drive unit, thus reach the effect reduced costs.
Accompanying drawing explanation
Fig. 1 is the use schematic diagram of an available liquid crystal display module.
Fig. 2 is the Organization Chart of an existing source lock drive unit.
Fig. 3 is the circuit diagram of an existing latch unit.
Fig. 4 is a kind of circuit diagram reducing the source class drive unit of latch assembly quantity of the present invention.
Fig. 5 is a kind of emulation schematic diagram reducing the source class drive unit of latch assembly quantity of the present invention.
Fig. 6 A is the schematic diagram that the present invention's 6 latch units connect.
Fig. 6 B is the circuit diagram that the present invention's 6 latch units connect.
[symbol description]
Embodiment
Describe the present invention below in conjunction with accompanying drawing.
Fig. 4 is a kind of circuit diagram reducing the source class drive unit 400 of latch assembly quantity of the present invention.Described source class drive unit 400 comprises a main latch unit 410 and at least one servant's latch unit 420.Described main latch unit 410 has one first transmission lock 411,1 first phase inverter 413,1 second phase inverter 415,1 first activation lock (MP4) and one second activation lock (MN4), and the output terminal FB1 of described second phase inverter 415 is connected to the input end of described first phase inverter 413.
Described at least one servant's latch unit 420 has one second transmission lock 421, the 3rd phase inverter 423 and one the 4th phase inverter 425.
Wherein, when described first activation lock (MP4) and described second activation lock (MN4) receive a breech lock enable signal (S) and one anti-phase breech lock enable signal (SB) respectively, drive described main latch unit 410 and described at least one servant's latch unit 420 to perform breech lock.That is when breech lock enable signal (S) is an electronegative potential (VGG), and anti-phase breech lock enable signal (SB) is when being a noble potential (VPP), described main latch unit 410 and described at least one servant's latch unit 420 perform breech lock.
As shown in Figure 4, first transmission lock 411 of described main latch unit 410 is connected to one first input signal (D1), the input end of the first phase inverter 413 of described main latch unit 410 is connected to the first transmission lock 411 of described main latch unit 410, in order to by anti-phase for described first input signal (D1), the input end of the second phase inverter 415 of described main latch unit 410 is connected to the output terminal of the first phase inverter 413 of described main latch unit 410, the output terminal (FB1) of the first phase inverter 413 is connected to the input end of the first phase inverter 413 of described main latch unit 410, in order to form described main latch unit 410, first activation lock (MP4) of described main latch unit 410 and the second activation lock (MN4) are connected to the second phase inverter 415 of described main latch unit 410.
Second transmission lock 421 of described at least one servant's latch unit 420 is connected to one second input signal (D2), the input end of the 3rd phase inverter 423 of described at least one servant's latch unit 420 is connected to the output terminal of the second transmission lock 421 of described at least one servant's latch unit 420, with by anti-phase for described second input signal (D2), the input end of the 4th phase inverter 425 of described at least one servant's latch unit 420 is connected to the output terminal of the 3rd phase inverter 423 of described at least one servant's latch unit 420, the output terminal (FB2) of described 4th phase inverter 425 is connected to the input end of the 3rd phase inverter 423 of described at least one servant's latch unit 420, to form described at least one servant's latch unit 420, first activation lock (MP4) of described main latch unit 410 and the second activation lock (MN4) are connected to the 4th phase inverter 425 of described at least one servant's latch unit 420.
First transmission lock 411 of described main latch unit 410 is made up of one first PMOS transistor (MP1) and one first nmos pass transistor (MN1), and the first phase inverter 413 of described main latch unit 410 is made up of one second PMOS transistor (MP2) and one second nmos pass transistor (MN2).Second phase inverter 415 of described main latch unit 410 is made up of one the 3rd PMOS transistor (MP3) and one the 3rd nmos pass transistor (MN3), first activation lock of described main latch unit 410 is one the 4th PMOS transistor (MP4), and the second activation lock of described main latch unit is one the 4th nmos pass transistor (MN4).
Second transmission lock 421 of described at least one servant's latch unit 420 is made up of one the 5th PMOS transistor (MP5) and one the 5th nmos pass transistor (MN5), 3rd phase inverter 423 of described at least one servant's latch unit 420 is made up of one the 6th PMOS transistor (MP2) and one the 6th nmos pass transistor (MN6), and the 4th phase inverter 425 of described at least one servant's latch unit 420 is made up of one the 7th PMOS transistor (MP7) and one the 7th nmos pass transistor (MN7).
The source electrode of described first PMOS transistor (MP1) connects to receive described first input signal (D1), its gate is connected to described anti-phase breech lock enable signal (SB), the drain of described first nmos pass transistor (MN1) is connected to described first input signal (D1), its gate connects to receive described breech lock enable signal (S), and its source electrode is connected to the drain of described first PMOS transistor (MP1).
The source electrode of described second PMOS transistor (MP2) is connected to a noble potential (Vpp), its gate is connected to the drain of described first PMOS transistor (MP1), the drain of described second nmos pass transistor (MN2) is connected to the drain of described second PMOS transistor (MP2), its gate is connected to the drain of described first PMOS transistor (MP1), and its source electrode is connected to an electronegative potential (VGG).
The source electrode of described 4th PMOS transistor (MP4) is connected to described noble potential (VPP), its gate connects to receive described breech lock enable signal (S), the source electrode of described 4th nmos pass transistor (MN4) is connected to described electronegative potential (VGG), and its gate connects to receive described anti-phase breech lock enable signal (SB).
The source electrode of described 3rd PMOS transistor (MP3) is connected to the drain of described 4th PMOS transistor (MP4), its gate is connected to the drain of described second PMOS transistor (MP2), its drain is connected to drain and one first output terminal (OUT1) of described first PMOS transistor (MP1), the source electrode of described 3rd nmos pass transistor (MN3) is connected to the drain of described 4th nmos pass transistor (MN4), its gate is connected to the drain of described second PMOS transistor (MP2), its drain is connected to the drain of described 3rd PMOS transistor (MP3).
The source electrode of described 5th PMOS transistor (MP5) connects to receive described second input signal (D2), its gate connects to receive described anti-phase breech lock enable signal (SB), the drain of described 5th nmos pass transistor (MN5) connects to receive described second input signal (D2), its gate connects to receive described breech lock enable signal (S), and its source electrode is connected to the drain of described 5th PMOS transistor (MP5).
The source electrode of described 6th PMOS transistor (MP6) is connected to described noble potential (VPP), its gate is connected to the drain of described 5th PMOS transistor (MP5), the drain of described 6th nmos pass transistor (MN6) is connected to the drain of described 6th PMOS transistor (MP6), its gate is connected to the drain of described 5th PMOS transistor (MP5), and its source electrode is connected to described electronegative potential (VGG).
The source electrode of described 7th PMOS transistor (MP7) is connected to the drain of described 4th PMOS transistor (MP4), its gate is connected to the drain of described 6th PMOS transistor (MP6), its drain is connected to drain and one second output terminal (OUT2) of described 5th PMOS transistor (MP5), the source electrode of described 7th nmos pass transistor (MN7) is connected to the drain of described 4th nmos pass transistor (MN4), its gate is connected to the drain of described 6th PMOS transistor (MP6), its drain is connected to the drain of described 7th PMOS transistor (MP7).
The structure that the transistor that the main latch unit of the present invention 410 and at least one servant's latch unit 420 also can take other those of ordinary skill in the art to know is formed.
Fig. 5 is a kind of emulation schematic diagram reducing the source class drive unit 400 of latch assembly quantity of the present invention.When breech lock enable signal (S) be an electronegative potential (VGG), anti-phase breech lock enable signal (SB) be a noble potential (VPP) time, described main latch unit 410 and described at least one servant's latch unit 420 perform breech lock.As shown in Figure 5, in oval A place, described breech lock enable signal (S) becomes an electronegative potential (VGG), now the first input signal (D1) and the second input signal (D2) are noble potential (VPP), thus the output terminal (FB2) of the output terminal (FB1) of described main latch unit 410 and described at least one servant's latch unit 420 all latched be noble potential (VPP).In oval B place, described breech lock enable signal (S) becomes noble potential (VPP), main latch unit 410, servant's latch unit 420 are sampling mode (sample mode), therefore output terminal (FB1) and output terminal (FB2) react the current potential of the first input signal (D1) and the second input signal (D2).In oval C place, described breech lock enable signal (S) becomes again electronegative potential (VGG), now the first input signal (D1) and the second input signal (D2) are electronegative potential (VGG), thus the output terminal (FB2) of the output terminal (FB1) of described main latch unit 410 and described at least one servant's latch unit 420 all latched be electronegative potential (VGG).
From the analog result of Fig. 5, although the present invention decreases the first activation lock and the second activation lock of described at least one servant's latch unit 420, but still original function can be performed.Effectively can save the area of component count and source class drive unit, thus reach the effect reduced costs.
Owing to comprising latch unit identical in a large number in source class drive unit, the present invention can reduce the number of transistor in latch unit, therefore effectively can reduce layout area.
To export in the source class drive unit of existing 6 single red/green/analog voltage of blue channel (R/G/B channel) needs 6 latch units to lock the numerical data of getting 6, but the present invention only need retain the first activation lock (MP4) and the second activation lock (MN4) of one of them latch unit, then the first activation lock (MP4) of all the other 5 latch units and the second activation lock (MN4) are removed, connected mode as shown in Figure 6A.Fig. 6 A is the schematic diagram that the present invention's 6 latch units connect.Fig. 6 B is the circuit diagram that the present invention's 6 latch units connect.As shown in Figure 6B, the described first activation lock (MP4) of described main latch unit 410 and described second activation lock (MN4) can control the breech lock of described servant's latch unit 420, therefore 10 transistors can be saved at the source class drive unit of 6, when resolution 960 × 540 of LCD MODULE 120, entirety at least needs 960 × 3(to comprise R/G/B) the source class drive unit of individual 6, and then 28800 (=960 × 3 × 10) individual transistor can be saved altogether.
From aforementioned explanation, a kind of source class drive unit reducing latch assembly quantity of the present invention its can comprise a main latch unit and first to N number of servant's latch unit.Described main latch unit has a transmission lock, one first phase inverter, one second phase inverter, one first activation lock and one second activation lock, and the output terminal of described second phase inverter is connected to the input end of described first phase inverter.Described first has a transmission lock, one the 3rd phase inverter and one the 4th phase inverter to each servant's latch unit of N number of servant's latch unit, when described first activation lock and described second activation lock are connected to described first respectively to described 4th phase inverter of N number of servant's latch unit; Wherein, when described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described first simultaneously to N number of servant's latch unit.
Meanwhile, when single red/green/blue channel (R/G/B channel) required by GTG (gray level) become 8 from 6 time, the technology of the present invention can save 14 transistors.When becoming 12 from 6, the technology of the present invention can save 22 transistors.When the GTG (gray level) that screen resolution is larger, required is higher, the savable transistor size of the technology of the present invention is more.
Again, due to the decreased number of bulk crystal pipe, it can reduce overall power consumption effectively, therefore the technology of the present invention is applicable to need in the handheld apparatus of low-power consumption especially.
Above-described embodiment is citing for convenience of description only, and the interest field that the present invention advocated from should being as the criterion with described in claim, but not is only limitted to above-described embodiment.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (11)
1. reduce a source class drive unit for latch assembly quantity, it is characterized in that, comprise:
One main latch unit, it has one first transmission lock, one first phase inverter, one second phase inverter connected successively, and the one first activation lock to be connected with one end of described second phase inverter, the one second activation lock that is connected with the other end of described second phase inverter, described first transmission lock is in order to receive one first input signal, and the output terminal of described second phase inverter is connected to the input end of described first phase inverter; And
At least one servant's latch unit, each servant's latch unit has one second transmission lock, one the 3rd phase inverter and one the 4th phase inverter connected successively, the output terminal of described 4th phase inverter is connected to the input end of described 3rd phase inverter, described second transmission lock is in order to receive one second input signal, and described first activation lock is connected described 4th phase inverter respectively with described second activation lock;
When described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described at least one servant's latch unit simultaneously.
2. the source class drive unit reducing latch assembly quantity as claimed in claim 1, it is characterized in that, described first transmission lock is made up of one first PMOS transistor and one first nmos pass transistor, the source electrode of described first PMOS transistor is in order to receive described first input signal, its gate is connected to described anti-phase breech lock enable signal, and the drain of described first nmos pass transistor is connected to described first input signal, its gate is in order to receive described breech lock enable signal, and its source electrode is connected to the drain of described first PMOS transistor.
3. the source class drive unit reducing latch assembly quantity as claimed in claim 2, it is characterized in that, described first phase inverter is made up of one second PMOS transistor and one second nmos pass transistor, the source electrode of described second PMOS transistor is connected to a noble potential, its gate is connected to the drain of described first PMOS transistor, the drain of described second nmos pass transistor is connected to the drain of described second PMOS transistor, its gate is connected to the drain of described first PMOS transistor, and its source electrode is connected to an electronegative potential.
4. the source class drive unit reducing latch assembly quantity as claimed in claim 3, it is characterized in that, described second phase inverter is made up of one the 3rd PMOS transistor and one the 3rd nmos pass transistor, the source electrode of described 3rd PMOS transistor is connected to described first activation lock, its gate is connected to the drain of described second PMOS transistor, its drain is connected to drain and one first output terminal of described first PMOS transistor, the source electrode of described 3rd nmos pass transistor is connected to described second activation lock, its gate is connected to the drain of described second PMOS transistor, its drain is connected to the drain of described 3rd PMOS transistor.
5. the source class drive unit reducing latch assembly quantity as claimed in claim 4, it is characterized in that, described first activation lock is one the 4th PMOS transistor, described second activation lock is one the 4th nmos pass transistor, the source electrode of described 4th PMOS transistor is connected to described noble potential, its gate is in order to receive described breech lock enable signal, its drain is connected to the source electrode of described 3rd PMOS transistor, and the source electrode of described 4th nmos pass transistor is connected to described electronegative potential, its gate is in order to receive described anti-phase breech lock enable signal, its drain is connected to the source electrode of described 3rd nmos pass transistor.
6. the source class drive unit reducing latch assembly quantity as claimed in claim 5, it is characterized in that, second transmission lock of described servant's latch unit is made up of one the 5th PMOS transistor and one the 5th nmos pass transistor, the source electrode of described 5th PMOS transistor is in order to receive described second input signal, its gate is in order to receive described anti-phase breech lock enable signal, and the drain of described 5th nmos pass transistor receives described second input signal, its gate receives described breech lock enable signal, and its source electrode is connected to the drain of described 5th PMOS transistor.
7. the source class drive unit reducing latch assembly quantity as claimed in claim 6, it is characterized in that, described 3rd phase inverter is made up of one the 6th PMOS transistor and one the 6th nmos pass transistor, the source electrode of described 6th PMOS transistor is connected to described noble potential, its gate is connected to the drain of described 5th PMOS transistor, the drain of described 6th nmos pass transistor is connected to the drain of described 6th PMOS transistor, its gate is connected to the drain of described 5th PMOS transistor, and its source electrode is connected to described electronegative potential.
8. the source class drive unit reducing latch assembly quantity as claimed in claim 7, it is characterized in that, described 4th phase inverter is made up of one the 7th PMOS transistor and one the 7th nmos pass transistor, the source electrode of described 7th PMOS transistor is connected to the drain of described 4th PMOS transistor, its gate is connected to the drain of described 6th PMOS transistor, its drain is connected to drain and one second output terminal of described 5th PMOS transistor, the source electrode of described 7th nmos pass transistor is connected to the drain of described 4th nmos pass transistor, its gate is connected to the drain of described 6th PMOS transistor, its drain is connected to the drain of described 7th PMOS transistor.
9. reduce a source class drive unit for latch assembly quantity, it is characterized in that, comprise:
One main latch unit, it has one first activation lock and one second activation lock; And
First to N number of servant's latch unit, described first activation lock is connected to described first servant's latch unit one end to described N number of servant's latch unit, described second activation lock is connected to described first servant's latch unit to the other end of described N number of servant's latch unit, described N be greater than 1 integer;
Described main latch unit and described first is connected in parallel to N number of servant's latch unit, respectively in order to receive first to N+1 input signal;
When described first activation lock and described second activation lock receive a breech lock enable signal and an anti-phase breech lock enable signal respectively, perform breech lock in order to drive described main latch unit and described first simultaneously to N servant's latch unit.
10. the source class drive unit reducing latch assembly quantity as claimed in claim 9, it is characterized in that, described main latch unit has one first transmission lock, one first phase inverter, one second phase inverter connected successively, and the one first activation lock to be connected respectively with described second phase inverter and one second activation lock, described first transmission lock is in order to receive one first input signal, and the output terminal of described second phase inverter is connected to the input end of described first phase inverter.
The 11. source class drive units reducing latch assembly quantity as claimed in claim 10, it is characterized in that, described servant's latch unit has one second transmission lock, one the 3rd phase inverter and one the 4th phase inverter connected successively, and the output terminal of described 4th phase inverter is connected to the input end of described 3rd phase inverter; Described first to the described second transmission lock of N servant's latch unit respectively in order to receive second to N+1 input signal, described first activation lock and described second activation lock are connected described first respectively to the 4th phase inverter of N servant's latch unit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159680A (en) * | 1995-09-05 | 1997-09-17 | 三菱电机株式会社 | Trigger circuit, scanning route and storage circuit |
| CN101042845A (en) * | 2006-03-20 | 2007-09-26 | 三菱电机株式会社 | Image display device |
| CN101114414A (en) * | 2006-07-27 | 2008-01-30 | 三星电子株式会社 | Driving apparatus for display device and display device including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101528750B1 (en) * | 2009-01-07 | 2015-06-15 | 삼성전자주식회사 | Display device and driving circuit of the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159680A (en) * | 1995-09-05 | 1997-09-17 | 三菱电机株式会社 | Trigger circuit, scanning route and storage circuit |
| CN101042845A (en) * | 2006-03-20 | 2007-09-26 | 三菱电机株式会社 | Image display device |
| CN101114414A (en) * | 2006-07-27 | 2008-01-30 | 三星电子株式会社 | Driving apparatus for display device and display device including the same |
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