CN104835800A - Integrated circuit fuse structure and manufacturing method thereof - Google Patents
Integrated circuit fuse structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN104835800A CN104835800A CN201410045514.9A CN201410045514A CN104835800A CN 104835800 A CN104835800 A CN 104835800A CN 201410045514 A CN201410045514 A CN 201410045514A CN 104835800 A CN104835800 A CN 104835800A
- Authority
- CN
- China
- Prior art keywords
- metal
- titanium
- fuse
- layer
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides an integrated circuit (IC) fuse structure and a manufacturing method thereof. The method comprises the steps of: forming a contact aperture on a BPSG layer of a silicon substrate; forming a Ti metal layer on the surfaces of the contact aperture and the BPSG layer; forming a TiN layer on the surface of the Ti metal layer; forming a metal plug in the contact aperture; etching the TiN layer on the outside of the metal plug and exposing the Ti metal layer under the TiN layer; forming a metal layer on the surfaces of the metal plug and the exposed Ti metal layer; and photoetching and respectively etching the metal layer and the Ti metal layer under the metal layer into a metal strip and a Ti metal strip to form a fuse structure. The IC fuse structure does not include TiN materials, and can not form a metal molten mass or metal residuals in a fusing process, thereby effectively avoiding failure of a fuse fusing function, and furthermore guaranteeing product yield and qualified rate.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of fuse-wires structure and manufacture method thereof of integrated circuit.
Background technology
Integrated circuit (integrated circuit, IC) be a kind of microelectronic device or parts, it adopts certain technique by together with the elements such as transistor required in a circuit, diode, resistance, electric capacity and inductance and wire interconnects, be produced on a fritter or a few fritter semiconductor wafer or dielectric substrate, then be encapsulated in a shell, become the microstructure with required circuit function.All elements on it structurally form a whole by integrated circuit, thus make electronic component stride forward major step towards aspects such as microminaturization, low-power consumption, intellectualities.At present, in semi-conductor industry great majority application be integrated circuit based on silicon.
Fuse (fuse) is the important technology used during integrated circuit is produced, and it has a narrow portion usually, specifically comprises metal fuse and polysilicon fuse.As the key structure in integrated circuit, it revises its attribute by the fusing of larger immediate current, thus in order to the resistance/capacitance trimming (trim) integrated circuit, the precision guaranteeing voltage/current a reference source and the overall performance improving IC.Metal fuse is substantially identical with the operation principle of polysilicon fuse, and it is all use probe to draw to connect big current fusing, once just irrecoverable after fusing.Due to fuse-wires structure to realize cost low, therefore use comparatively general.
In IC manufacturing process, the raising of interconnection technique to finished product rate plays critical effect, and conventional interconnection material generally includes metallic aluminium, copper etc.Contact metal connector (is generally tungsten metal plug, be called for short tungsten plug) as the interconnection technique of wherein a kind of key, its manufacture method usually as shown in Figure 1 to Figure 3, specifically comprise: (not shown) after 1) conveniently technique forms contact hole on the silicon oxide layer 1 of silicon substrate, at surface deposition one deck titanium (Ti) metal level 2 of contact hole and silicon oxide layer 1 as contact layer, in order to avoid the oxidation of subsequent metal aluminium or tungsten; 2) deposit one deck titanium nitride layer 3(TiN on titanium coating 2) as diffusion impervious layer and adhesion layer, to spread to silicon substrate in order to effectively to prevent aluminium or tungsten and improve the adhesive capacity of tungsten and silicon oxide layer; 3) deposition tungsten on titanium nitride layer 3, finally uses back quarter (etch back) or tungsten process chemistry mechanical lapping (WCMP) to remove the outside unnecessary tungsten of contact hole, thus forms tungsten plug in contact hole inside.As shown in Figure 4, after formation tungsten plug, continue deposit layer of metal layer 4, and the titanium nitride layer 3 of photoetching, etching sheet metal 4 and below thereof and titanium coating 2, fuse-wires structure 8 can be formed.
Above-mentioned fuse-wires structure 8 generally includes silicon substrate, the titanium bar 5 be positioned on the silicon oxide layer 1 of silicon substrate, the bonding jumper 7 that covers the titanium nitride bar 6 on described titanium bar 5 and cover on described titanium bar 6.But; containing titanium nitride material in this fuse-wires structure 8; its fusing point is up to 2950 DEG C; even if also cannot distil completely under larger electric current and evaporate into steam; therefore usually can cause being formed when fusing to this fuse-wires structure 8 disconnecting thoroughly; thus make the disabler of fuse-wires structure, cause the rate of finished products of product and qualification rate to reduce.
Summary of the invention
The invention provides a kind of fuse-wires structure and manufacture method thereof of integrated circuit, fuse-wires structure of the present invention is not containing titanium nitride material, and therefore it effectively can improve the fusing effect of fuse, avoids the fuse function of fuse-wires structure to lose efficacy.
The manufacture method of the fuse-wires structure of a kind of integrated circuit provided by the invention, comprises the steps:
The silicon oxide layer of silicon substrate forms contact hole;
Titanium coating is formed at described contact hole and described silicon oxide layer surface;
Titanium nitride layer is formed on described titanium coating surface;
Metal plug is formed in described contact hole;
Etch the titanium nitride layer of described metal plug outside and the titanium coating exposed below described titanium nitride layer;
At described metal plug and the described titanium coating forming metal layer on surface exposed;
Photoetching, and respectively the titanium coating below described metal level and its is etched into bonding jumper and titanium bar, form fuse-wires structure.
Silicon oxide layer of the present invention can for being formed as the silicon oxide layer undoping and/or adulterate on silicon substrate, and it can be formed by this area conventional method.Further, the thickness of described silicon oxide layer can be 1000 ~ 10000
According to manufacture method provided by the invention, described on the silicon oxide layer of silicon substrate, form contact hole before, also comprise:
Form grid, source electrode and drain electrode on a silicon substrate;
The silicon substrate being formed with described grid, source electrode and drain electrode is formed the silicon oxide layer undoping and/or adulterate.
Further, after adopting conventional method to form grid, source electrode and drain electrode on a silicon substrate, can by the plain silicon oxide layer of deposit one deck in the surface of silicon being formed with grid, source electrode and drain electrode, then on described plain silicon oxide layer deposit one deck doped with the silicon oxide layer (BPSG) of boron and phosphorus, silicon oxide layer described in formation, it comprises the silicon oxide layer undoping and adulterate.
According to manufacture method provided by the invention, in described contact hole, form metal plug, specifically comprise:
Depositing metal tungsten on described titanium nitride layer;
Remove the tungsten of described contact hole outside, thus form tungsten plug in described contact hole.
According to manufacture method provided by the invention, described metal level is aluminum metal layer.
Further, the thickness of described titanium coating is 100 ~ 2000
the thickness of described titanium nitride layer is 100 ~ 2000
Further, the thickness of described metal level is 0.4 ~ 4um.
The present invention also provides a kind of fuse-wires structure of integrated circuit, and comprise silicon substrate, titanium bar and bonding jumper, described silicon substrate is provided with silicon oxide layer, and described titanium bar is arranged on described silicon oxide layer, and described bonding jumper covers on described titanium bar.
Further, the thickness of described titanium bar is 100 ~ 2000
the thickness of described bonding jumper is 0.4 ~ 4um.
Further, described bonding jumper has the first narrow portion, and described titanium bar has the second narrow portion, and described second narrow portion is positioned at immediately below described first narrow portion, and described second narrow portion and described first narrow portion have identical width and length.Particularly, described first narrow portion is the part that on described bonding jumper, the relatively described bonding jumper of width reduces, and described second narrow portion is the part that on described titanium bar, the relatively described titanium bar of width reduces.
Further, described width is 0.1 ~ 10um, such as 0.8 ~ 2um, and described length is 1 ~ 20um, such as 5 ~ 10um.
The manufacturing approach craft of the fuse-wires structure of integrated circuit provided by the present invention is simple, be easy to operation, and not containing titanium nitride material in the fuse-wires structure that described manufacture method is formed, it can not form Metal Melting melt body or metal residual in fusing process, therefore, it is possible to avoid fuse failure disabler, thus ensure rate of finished products and the qualification rate of product preferably.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the manufacturing process schematic diagram of the fuse-wires structure manufacture method of prior art integrated circuit;
Fig. 5 to Fig. 7 is the manufacturing process schematic diagram of the fuse-wires structure manufacture method of the integrated circuit of one embodiment of the invention;
Fig. 8 is the plan structure schematic diagram of the fuse-wires structure of the integrated circuit of one embodiment of the invention;
Reference numeral:
1, silicon oxide layer; 2, titanium coating; 3, titanium nitride layer; 4, metal level; 5, titanium bar; 6, titanium nitride bar; 7, bonding jumper; 8, the fuse-wires structure of prior art integrated circuit; 9, the fuse-wires structure of integrated circuit of the present invention; 10, narrow portion.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with drawings and Examples of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment
The fuse-wires structure manufacture method of integrated circuit of the present invention comprises the steps:
Step 1, on the silicon oxide layer of silicon substrate, form contact hole;
Particularly, described silicon oxide layer can for the silicon oxide layer undoping and/or adulterate, it can be formed on a silicon substrate by this area conventional method, such as: grid can be formed on a silicon substrate, source electrode and drain electrode after, continue be formed with grid, the plain silicon oxide layer of deposit one deck in the surface of silicon of source electrode and drain electrode, in order to form protection to device surface, then on described plain silicon oxide layer deposit one deck doped with the silicon oxide layer (BPSG) of boron and phosphorus, in order to carry out elementary planarization to surface of silicon, thus form the silicon substrate with described silicon oxide layer, now described silicon oxide layer is the dielectric layer comprising plain silicon oxide layer and the silicon oxide layer doped with boron and phosphorus,
The thickness of described silicon oxide layer can be general thickness (1000 ~ 10000
), the thickness of such as described plain silicon oxide layer can be 2000
the thickness of the described silicon oxide layer doped with boron and phosphorus can be 8000
thus form that to have thickness be 10000
the silicon substrate of silicon oxide layer;
At the upper spin coating photoresist of the silicon oxide layer (being specially the silicon oxide layer doped with boron and phosphorus) of above-mentioned silicon substrate, after exposure, development are formed and have the mask of contact hole graph, utilize plasma etching, thus form contact hole on described silicon oxide layer.
Step 2, described contact hole and described silicon oxide layer surface formed titanium coating;
Particularly, as shown in Figure 1, at surface sputtering one deck titanium coating 2 of described contact hole (not shown) and said silicon oxide 1, its thickness can be general thickness (100 ~ 2000
), such as 100
in order to prevent the oxidation of subsequent deposition metal and to reduce contact resistance.
Step 3, form titanium nitride layer on described titanium coating surface;
Particularly, as shown in Figure 2, at surface sputtering one deck titanium nitride layer 3 of described titanium coating 2, its thickness can be general thickness (100 ~ 2000
), such as 200
for as the barrier layer of subsequent metal connector and adhesive layer.
Step 4, in described contact hole, form metal plug;
Particularly, deposit layer of metal tungsten on described titanium nitride layer 3, after making tungsten fill whole contact hole, the tungsten of grinding and polishing or time described contact hole outside of removal at quarter, thus in described contact hole, form metal plug (i.e. tungsten plug).
Step 5, etch described metal plug outside titanium nitride layer and the titanium coating exposed below described titanium nitride layer;
Particularly, as shown in Figure 5, using plasma etches the outside titanium nitride layer 3 of described metal plug (namely tungsten plug, not shown) and the titanium coating 2 exposed below described titanium nitride layer 3.
Step 6, at described metal plug and the described titanium coating forming metal layer on surface exposed;
Particularly, as shown in Figure 6, at described metal plug (i.e. tungsten plug, not shown) and the forming metal layer on surface 4 of the described titanium coating 2 exposed, its thickness can be general thickness (0.4 ~ 4um), such as 4um, its material can be conventional interconnection material, such as metallic aluminium.
Step 7, photoetching, and respectively the titanium coating below described metal level and its is etched into bonding jumper and titanium bar, form fuse-wires structure;
Particularly, as shown in Figure 7, spin coating photoresist on described metal level 4, after exposure, development form the mask of fuse-wires structure, utilize plasma that metal level 4 and the titanium coating 2 below it are etched into bonding jumper 7 and titanium bar 5 respectively, thus form fuse-wires structure 9;
As shown in Figure 8, in the fuse-wires structure 9 that the present embodiment is formed, bonding jumper 7 and titanium bar 5 are completely overlapping, and described bonding jumper 7 has the first narrow portion (part that the relatively described bonding jumper 7 of the width namely on described bonding jumper 7 reduces), described titanium bar 5 has the second narrow portion (part that the relatively described titanium bar 5 of the width namely on described titanium bar 5 reduces), described second narrow portion is positioned at immediately below described first narrow portion, and described second narrow portion and described first narrow portion have identical width and length (namely described first narrow portion just in time covers the top of described second narrow portion completely), described width can be 0.1 ~ 10um, such as 0.8 ~ 2um, described length is 1 ~ 20um, such as 5 ~ 10um, described first narrow portion and described second narrow portion form the narrow portion 10 of fuse-wires structure 9 jointly, described narrow portion 10 is conducive to the fusing of fuse-wires structure 9.The size of narrow portion 10 can be arranged according to actual needs, such as in the present embodiment, the width of described narrow portion 10 is that the width of 1um(and described first narrow portion and described second narrow portion is 1um), the length of narrow portion 10 is that the length of 10um(and described first narrow portion and described second narrow portion is 10um).
The fuse-wires structure 9 of the integrated circuit that said method is formed comprises silicon substrate, titanium bar 5 and bonding jumper 7(and is specially aluminum metal bar), described silicon substrate is provided with silicon oxide layer 1, described titanium bar 5 is arranged on described silicon oxide layer 1, and described bonding jumper 7 covers on described titanium bar 5 (namely bonding jumper 7 to be positioned at directly over titanium bar 5 and the location overlap of bonding jumper 7 and titanium bar 5); Wherein, the thickness of described titanium bar 5 is 100
the thickness of described bonding jumper 7 is 4um, described bonding jumper 7 has the first narrow portion, and described titanium bar 5 has the second narrow portion, and described second narrow portion is positioned at immediately below described first narrow portion, and the width of described first narrow portion and described second narrow portion is 1um, and length is 10um.
Not containing titanium nitride material in the fuse-wires structure 9 of integrated circuit of the present invention, it can distil and evaporate into steam under conventional current (as 500mA), Metal Melting melt body or metal residual can not be formed in fusing process, therefore, it is possible to avoid the defects such as fuse failure disabler, it has better effect when trimming the resistance/capacitance of integrated circuit, therefore, it is possible to guarantee the precision of voltage/current a reference source and improve the overall performance of integrated circuit, thus ensure rate of finished products and the qualification rate of product.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a manufacture method for the fuse-wires structure of integrated circuit, is characterized in that, comprises the steps:
The silicon oxide layer of silicon substrate forms contact hole;
Titanium coating is formed at described contact hole and described silicon oxide layer surface;
Titanium nitride layer is formed on described titanium coating surface;
Metal plug is formed in described contact hole;
Etch the titanium nitride layer of described metal plug outside and the titanium coating exposed below described titanium nitride layer;
At described metal plug and the described titanium coating forming metal layer on surface exposed;
Photoetching, and respectively the titanium coating below described metal level and its is etched into bonding jumper and titanium bar, form fuse-wires structure.
2. manufacture method according to claim 1, is characterized in that, described on the silicon oxide layer of silicon substrate, form contact hole before, also comprise:
Form grid, source electrode and drain electrode on a silicon substrate;
The silicon substrate being formed with described grid, source electrode and drain electrode is formed the silicon oxide layer undoping and/or adulterate.
3. manufacture method according to claim 1, is characterized in that, forms metal plug, specifically comprise in described contact hole:
Depositing metal tungsten on described titanium nitride layer;
Remove the tungsten of described contact hole outside, thus form tungsten plug in described contact hole.
4. manufacture method according to claim 1, is characterized in that, described metal level is aluminum metal layer.
5. the manufacture method according to Claims 1-4, is characterized in that, the thickness of described titanium coating is 100 ~ 2000
the thickness of described titanium nitride layer is 100 ~ 2000
6. the manufacture method according to Claims 1-4, is characterized in that, the thickness of described metal level is 0.4 ~ 4um.
7. a fuse-wires structure for integrated circuit, is characterized in that, comprise silicon substrate, titanium bar and bonding jumper, described silicon substrate is provided with silicon oxide layer, and described titanium bar is arranged on described silicon oxide layer, and described bonding jumper covers on described titanium bar.
8. fuse-wires structure according to claim 7, is characterized in that, the thickness of described titanium bar is 100 ~ 2000
the thickness of described bonding jumper is 0.4 ~ 4um.
9. the fuse-wires structure according to claim 7 or 8, it is characterized in that, described bonding jumper has the first narrow portion, described titanium bar has the second narrow portion, described second narrow portion is positioned at immediately below described first narrow portion, and described second narrow portion and described first narrow portion have identical width and length.
10. fuse-wires structure according to claim 9, is characterized in that, described width is 0.1 ~ 10um, and described length is 1 ~ 20um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410045514.9A CN104835800B (en) | 2014-02-08 | 2014-02-08 | A kind of fuse-wires structure and its manufacturing method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410045514.9A CN104835800B (en) | 2014-02-08 | 2014-02-08 | A kind of fuse-wires structure and its manufacturing method of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104835800A true CN104835800A (en) | 2015-08-12 |
| CN104835800B CN104835800B (en) | 2019-01-22 |
Family
ID=53813584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410045514.9A Active CN104835800B (en) | 2014-02-08 | 2014-02-08 | A kind of fuse-wires structure and its manufacturing method of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104835800B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5914524A (en) * | 1994-05-15 | 1999-06-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20030036254A1 (en) * | 2001-08-16 | 2003-02-20 | Dennison Charles H. | Semiconductor processing methods, and semiconductor assemblies |
| US20040209404A1 (en) * | 1998-10-02 | 2004-10-21 | Zhongze Wang | Semiconductor fuses, methods of using and making the same, and semiconductor devices containing the same |
| CN1716591A (en) * | 2004-06-29 | 2006-01-04 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN101000906A (en) * | 2006-01-12 | 2007-07-18 | 三星电子株式会社 | Fuse region and method of fabricating the same |
| CN101034697A (en) * | 2006-03-09 | 2007-09-12 | 国际商业机器公司 | Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof |
| CN101083251A (en) * | 2003-08-07 | 2007-12-05 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN102428563A (en) * | 2009-05-22 | 2012-04-25 | 国际商业机器公司 | Structure and method of forming electrically blown metal fuses for integrated circuits |
| CN103107150A (en) * | 2011-11-09 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Interposers for semiconductor devices and methods of manufacture thereof |
| US20130277796A1 (en) * | 2006-10-19 | 2013-10-24 | International Business Machines Corporation | Electrical fuse and method of making |
-
2014
- 2014-02-08 CN CN201410045514.9A patent/CN104835800B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5914524A (en) * | 1994-05-15 | 1999-06-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20040209404A1 (en) * | 1998-10-02 | 2004-10-21 | Zhongze Wang | Semiconductor fuses, methods of using and making the same, and semiconductor devices containing the same |
| US20030036254A1 (en) * | 2001-08-16 | 2003-02-20 | Dennison Charles H. | Semiconductor processing methods, and semiconductor assemblies |
| CN101083251A (en) * | 2003-08-07 | 2007-12-05 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN1716591A (en) * | 2004-06-29 | 2006-01-04 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN101000906A (en) * | 2006-01-12 | 2007-07-18 | 三星电子株式会社 | Fuse region and method of fabricating the same |
| CN101034697A (en) * | 2006-03-09 | 2007-09-12 | 国际商业机器公司 | Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof |
| US20130277796A1 (en) * | 2006-10-19 | 2013-10-24 | International Business Machines Corporation | Electrical fuse and method of making |
| CN102428563A (en) * | 2009-05-22 | 2012-04-25 | 国际商业机器公司 | Structure and method of forming electrically blown metal fuses for integrated circuits |
| CN103107150A (en) * | 2011-11-09 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Interposers for semiconductor devices and methods of manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104835800B (en) | 2019-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI282592B (en) | Manufacturing method of semiconductor device | |
| US9054225B2 (en) | Integrated capacitor having a non-uniform thickness | |
| TW200908152A (en) | Semiconductor device and manufacturing method thereof | |
| CN102044426A (en) | Semiconductor device and manufacturing method thereof | |
| CN102324427B (en) | A kind of metal film resistor structure and manufacture method thereof | |
| CN114446876B (en) | Wafer cutting method | |
| CN106847690B (en) | etching method of multilayer metal layer | |
| CN101419924A (en) | Manufacturing method for semiconductor device | |
| CN104867865A (en) | Lead process for wafer three-dimensional integration | |
| CN109585452B (en) | Memory and manufacturing method thereof | |
| KR20140140390A (en) | Methods for fabricating semicondctor devices having through electrodes | |
| US9543247B1 (en) | Surface-mount electronic component | |
| US9570384B2 (en) | Semiconductor device | |
| CN105655341A (en) | Method for forming semiconductor device | |
| CN105513954A (en) | Forming method of semiconductor device | |
| CN102130036A (en) | Method for producing shallow trench isolating structure | |
| CN104835800A (en) | Integrated circuit fuse structure and manufacturing method thereof | |
| CN104701295B (en) | Electric fuse structure and forming method thereof | |
| CN105590923B (en) | Mim capacitor and forming method thereof | |
| CN104752154A (en) | Method for manufacturing capacitor | |
| US20110227230A1 (en) | Through-silicon via fabrication with etch stop film | |
| US11488820B2 (en) | Method of fabricating layered structure | |
| US7833896B2 (en) | Aluminum cap for reducing scratch and wire-bond bridging of bond pads | |
| KR100197535B1 (en) | Forming method for metal wiring in semiconductor device | |
| US20150194382A1 (en) | Interconnect and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220725 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |