CN104821721B - Semiconductor structure for enhanced transient response in low voltage difference (LDO) voltage-stablizer - Google Patents

Semiconductor structure for enhanced transient response in low voltage difference (LDO) voltage-stablizer Download PDF

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CN104821721B
CN104821721B CN201510057249.0A CN201510057249A CN104821721B CN 104821721 B CN104821721 B CN 104821721B CN 201510057249 A CN201510057249 A CN 201510057249A CN 104821721 B CN104821721 B CN 104821721B
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circuit
amplifier
amplifier circuit
output
voltage
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CN104821721A (en
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G·卢夫
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Intersil Americas LLC
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Intersil Americas LLC
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Abstract

The present invention discloses system, semiconductor structure, electronic circuit and the method for the enhanced transient response in low voltage difference (LDO) voltage-stablizer.For example, the present invention discloses the semiconductor structure for the enhanced transient response in LDO voltage stabilizer, and the semiconductor structure includes the first current mirroring circuit, is coupled to the input pad and output connector of the LDO voltage stabilizer；Second current mirroring circuit is coupled to the input pad of the LDO voltage stabilizer.First input coupling of the first amplifier circuit is to second current mirroring circuit, the output connector of the second input coupling of first amplifier circuit to the LDO voltage stabilizer, and the third input coupling of first amplifier circuit is to reference voltage.Output of the input coupling of second amplifier circuit to first amplifier circuit, the output coupling of second amplifier circuit is to first current mirroring circuit, the input coupling of third amplifier circuit is to the output of first amplifier circuit, and the output coupling of the third amplifier circuit is to second current mirroring circuit.In some embodiments, the semiconductor structure is formed at the adaptive-biased LDO voltage stabilizer in the power management integrated circuit on semiconducter IC, chip, chip or bare die (PMIC) or in power supply.

Description

Semiconductor structure for enhanced transient response in low voltage difference (LDO) voltage-stablizer
Cross reference to related applications
It is entitled " for enhanced transient state in low voltage difference (LDO) voltage-stablizer this application involves what is submitted on 2 5th, 2014 Semiconductor structure (the SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN of response LOW DROPOUT (LDO) VOLTAGE REGULATORS) " and the U.S. Provisional Patent Application that is hereby incorporated herein by Sequence number 61/936,111.The application further relates to submit on 2 28th, 2014 entitled " for low voltage difference (LDO) voltage-stablizer In enhanced transient response semiconductor structure (SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOW DROPOUT (LDO) VOLTAGE REGULATORS) " and U.S. for being hereby incorporated herein by Temporary patent application sequence number 61/946,268.The application is there is a requirement that 61/936,111 He of U.S. Provisional Patent Application Serial No. 61/946,268 equity.
Technical field
The present invention relates generally to low voltage difference (LDO) voltage-stablizers, and relate in particular to using semiconductor integrated circuit, The adaptive-biased LDO voltage stabilizer of enhanced transient response in chip, chip or bare die.
Background technique
In the conventional LDO voltage stabilizer of use " super current mirror " design, adjuster is to the response speed of transient state by them Adaptive-biased circuit rise to operating point the time it takes appropriate limitation.It is come from however, these LDO voltage stabilizers use The adaptive-biased feedback of the grid of their conducting transistor, and the therefore width of their adaptive-biased feedback loop It is limited by the big grid capacitance of their conducting device.Therefore, the output voltage that the transient state of these LDO voltage stabilizers induces falls phase When big.
Summary of the invention
One embodiment is for a kind of semiconductor structure for transient response enhanced in LDO voltage stabilizer.It is described Semiconductor structure is the LDO for including the adaptive-biased input stage being formed on semiconductor integrated circuit, chip, chip or bare die Voltage-stablizer.Adaptive-biased signal is the anti-of the input from the output coupling of input stage (for example, first gain stage) to the grade Feedback signal.Therefore, the transient response of the adaptive-biased feedback loop of gained is significantly faster than that the wink of the main feedback loop of LDO voltage stabilizer State response.More precisely, to LDO voltage stabilizer output stage driving current be apparently higher than output electric current rate rate Increase, so as to the gate capacitance charges to conducting transistor unit.Therefore, the load transient of adaptive-biased LDO voltage stabilizer lures The output voltage of hair, which falls, to be significantly less than the output voltage of conventional LDO voltage stabilizer and falls (for example, if using relatively small defeated Capacitor out).
Detailed description of the invention
It should be understood that attached drawing only depicted example embodiment and thus be not intended as having in range it is limited, by making With attached drawing, in addition the exemplary implementation scheme will be described with additional specificity and details.
Fig. 1 is the schematic block diagram of electronic circuit, and the electronic circuit can be used for implementing an exemplary reality of the invention Apply scheme.
Fig. 2 is the schematic block diagram of the second electronic circuit, and second electronic circuit can be used for implementing of the invention second Exemplary implementation scheme.
Fig. 3 is the schematic block diagram of third electronic circuit, and the third electronic circuit can be used for implementing third of the invention Exemplary implementation scheme.
Fig. 4 is the schematic block diagram of the 4th electronic circuit, and the 4th electronic circuit can be used for implementing of the invention the 4th Exemplary implementation scheme.
Fig. 5 is the schematic circuit of exemplary semiconductor structure, and the semiconductor structure can be used for implementing describing in Fig. 2 Electronic circuit or Fig. 4 in the electronic circuit described.
Fig. 6 is the schematic circuit of exemplary semiconductor structure, and the semiconductor structure can be used for implementing describing in Fig. 1 Electronic circuit or Fig. 3 in the electronic circuit described.
Fig. 7 A and Fig. 7 B are the analogue phase allowances for showing the LDO voltage stabilizer of embodiment structuring according to the present invention The correlogram of energy curve and gain margin performance curve.
Fig. 8 is that the simulation transient state for the adaptive-biased LDO voltage stabilizer for showing embodiment structuring according to the present invention is negative Carry the curve graph of response.
Fig. 9 is the performance mode for describing embodiment according to the present invention under the conditions of the simulated operation of LDO voltage stabilizer Curve graph.
Figure 10 is arranged to the schematic block diagram of the exemplary system of power management integrated circuit (PMIC), the power supply pipe Reason integrated circuit can be used for implementing partly the leading for enhanced transient response of one or more embodiments in accordance with the present invention Body structure.
Figure 11 is arranged to the schematic block diagram of the exemplary system of PMIC, and the PMIC can be used for implementing according to the present invention One or more embodiments the semiconductor structure for enhanced transient response.
Figure 12 is the exemplary of the adaptive-biased LDO voltage stabilizer of description one or more embodiments in accordance with the present invention The flow chart of operating method.
The list of reference numbers of primary clustering in attached drawing
100 electronic circuits
102 first amplifiers
104 non-inverting inputs
106 nodes
108 resistor R1
110 resistor R2
112 anti-phase inputs
114 outputs
The control input of 116 bias currents
118 inputs
120 second amplifiers
122 current mirrors
124 outputs
126 first crystal pipe devices
128 second transistor devices
130 input terminals
132 output terminals
134 capacitor C1
136 ground terminals
200 electronic circuits
201 inputs
202 first amplifiers
203 buffer amplifiers
204 non-inverting inputs
205 outputs
206 nodes
208 resistor R1
210 resistor R2
212 anti-phase inputs
214 outputs
The control input of 216 bias currents
218 inputs
220 second amplifiers
222 current mirrors
224 outputs
226 first crystal pipe devices
228 second transistor devices
230 input terminals
232 output terminals
234 capacitor C1
236 ground terminals
300 electronic circuits
302 first amplifiers
304 non-inverting inputs
305 third amplifiers
306 nodes
307 third transistor devices
308 resistor R1
309 the 4th transistor units
310 resistor R2
312 anti-phase inputs
The input of 316 bias currents
318 inputs
319 inputs
320 second amplifiers
322 first current mirrors
324 outputs
325 outputs
326 first crystal pipe devices
328 second transistor devices
330 input terminals
332 output terminals
334 capacitor C1
336 ground terminals
338 second current mirrors
400 electronic circuits
401 inputs
402 first amplifiers
403 buffer amplifiers
404 non-inverting inputs
405 third amplifiers
406 nodes
407 third transistor devices
408 resistor R1
409 the 4th transistor units
410 resistor R2
412 anti-phase inputs
The input of 416 bias currents
418 inputs
419 inputs
420 second amplifiers
422 first current mirrors
424 outputs
425 outputs
426 first crystal pipe devices
428 second transistor devices
430 input terminals
432 output terminals
434 capacitor C1
436 ground terminals
438 second current mirrors
500 semiconductor structures
501 transistor M8
502 first amplifiers
503 buffer amplifiers
504 non-inverting inputs
505 third amplifiers
506 nodes
507 third transistor devices
508 resistor R1
509 the 4th transistor units
510 resistor R2
512 anti-phase inputs
514 outputs
515 outputs
520 second amplifiers
522 first current mirrors
526 first crystal pipe devices
528 second transistor devices
530 input terminals
532 output terminals
534 capacitor C1
536 ground terminals
538 second current mirrors
600 semiconductor structures
601 transistor M8
602 first amplifiers
604 non-inverting inputs
605 third amplifiers
606 nodes
607 third transistor devices
608 resistor R1
609 the 4th transistor units
610 resistor R2
612 anti-phase inputs
614 outputs
620 second amplifiers
622 first current mirrors
626 first crystal pipe devices
628 second transistor devices
630 input terminals
632 output terminals
634 capacitor C1
636 ground terminals
638 second current mirrors
700a curve graph
700b curve graph
800 curve graphs
802 2.176V
900 curve graphs
902a performance curve
902b performance curve
904a performance curve
904b performance curve
906a performance curve
906b performance curve
908a performance curve
908b performance curve
1000 systems
1002 adaptive-biased LDO voltage stabilizers
1004 channels VLOGIC export connector
1006 sequencers
1008 AVDD boost controllers
1010 gate pulse modulators
1012 voltage detectors
1014 numerical control potentiometers
1030 input terminals
1032 output terminals
1100 systems
1102 adaptive-biased LDO voltage stabilizers
1130 voltage inputs
1132 voltage outputs
1136 ground terminals
1200 flow charts
1202 pieces
1204 pieces
1206 pieces
1208 pieces
1210 pieces
Specific embodiment
In the following detailed description, with reference to the attached drawing for forming present invention a part, and wherein by means of certain illustrative reality Scheme is applied to show.It is to be appreciated, however, that using other embodiments, and it can carry out that logic, mechanically and electrically aspect changes Become.In addition, the method presented in attached drawing and specification is understood not to limit the sequence of executable respective actions.Therefore, no It should explain in a limiting sense described in detail below.Throughout the drawings, referred to as far as possible using same or similar reference number For same or similar construction package or part.
The embodiment described herein provides the semiconductor for the enhanced transient response in low voltage difference (LDO) voltage-stablizer Structure.For an exemplary implementation scheme, semiconductor structure includes the LDO pressure stabilizing with adaptive-biased input stage Device.Adaptive-biased signal is the feedback letter of the input from the output coupling of input stage (for example, first gain stage) to the grade Number.Therefore, the transient response of the adaptive-biased feedback loop of gained is significantly faster than that the transient state of the main feedback loop of LDO voltage stabilizer is rung It answers.More precisely, the driving current to the output stage of LDO voltage stabilizer is increased with the rate for being apparently higher than the rate of output electric current Add, so as to the gate capacitance charges to conducting transistor unit.Therefore, the load transient of adaptive-biased LDO voltage stabilizer induces Output voltage fall and be significantly less than the output voltage of conventional LDO voltage stabilizer and fall (for example, if using relatively small output Capacitor).
It can be formed in such as semiconductor integrated circuit (IC), chip, chip or bare die for enhanced transient response The embodiment of semiconductor structure of the present invention.Thus, for example, the semiconductor structure can be used as IC power supply or power management IC (PMIC) LDO voltage stabilizer or in connection in.For example, high level, low ESR (ESR) electricity can needed Such IC power supply or PMIC are used in the product of capacitive load and the power supply rejection ratio of enhancing (PSRR) performance.In this way, for example, with It can be used in the IC power supply or PMIC of smart phone or similar products in the semiconductor structure of the present invention of enhanced transient response, institute Product is stated using relatively large (μ F range), low ESR ceramic capacitor to be used for power decoupling.In addition, certain products may Such semiconducter IC is asked to be embodied as the LDO voltage stabilizer that there is suitable transient response to relatively low output capacitance, because of supply Such ldo regulator of digital circuit usually undergoes the unexpected increase of load current.Therefore, the gained of LDO voltage stabilizer should be made Output voltage falls minimum (for example, 10mV to 30mV), to keep the appropriate circuitry of LDO voltage stabilizer at low voltage Energy.In this way, the semiconductor structure of the present invention for enhanced transient response is due to from the defeated of the first gain stage in LDO voltage stabilizer Adaptive-biased feedback is obtained out and readily satisfies such performance requirement, so that the bandwidth of adaptive-biased feedback loop is not led The big grid capacitance limitation of logical transistor unit, and bandwidth is limited in conventional LDO voltage stabilizer.
Fig. 1 is the schematic block diagram of electronic circuit 100, and it is exemplary that the electronic circuit can be used for implementing of the invention one Embodiment.For example, electronic circuit 100 can be used for implementing for the adaptive of the enhanced transient response in semiconductor structure LDO voltage stabilizer, such as semiconductor integrated circuit (IC), chip, chip or bare die should be biased.
The exemplary implementation scheme with reference to shown in Fig. 1, electronic circuit 100 (for example, LDO voltage stabilizer) include the first amplification Device 102, first amplifier are the input stages for also functioning as the error amplifier in circuit 100.In this exemplary implementation scheme In, the first amplifier 102 is voltage gain amplifier, and current offset level is by its output voltage control (for example, self-bias is put Big device).First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 104 of the first amplifier 102.? In some embodiments, the first input voltage is the fixed reference potential generated in electronic circuit 100.In other embodiments In, the first input voltage is variable reference voltage (for example, being changed by D/A converter).In some embodiments, first Input voltage generates outside electronic circuit 100, and is connected to input 104 for example, by the pin of semiconducter IC or chip.The Two input voltages (for example, feedback voltage or Vfb) are from the node 106 for being connected to first resistor device 108 and second resistor 110 (for example, resistive voltage divider) is connected to the anti-phase input 112 of the first amplifier 102, and the output voltage of the first amplifier 102 Bias current control 116 (that is, automatic biasings) of input of the first amplifier 102 are coupled back into from the output 114 of the first amplifier 102, And it is additionally coupled to the input 118 of the second amplifier 120.In this exemplary implementation scheme, the second amplifier 120 is reverse phase mutual conductance Amplifier, second amplifier form the driving current for being used for current mirror output stage 122.More precisely, the second amplifier The gate terminal and drain terminal of the first crystal pipe device 126 of current mirror output stage 122 are coupled in 120 output 124, and also It is coupled to the gate terminal of the second transistor device 128 of current mirror output stage 122.First crystal pipe device 126 and the second crystalline substance The source terminal of body pipe device 128 is coupled to the input terminal 130 of electronic circuit 100 (for example, VIN).Second transistor device 128 drain terminal is coupled to side (for example, opposite with the side of node 106) and the electronic circuit of first resistor device 108 100 output terminal 132 is (for example, VOUT).Output terminal 132 is coupled in the side of capacitor 134 (for example, output capacitor), And the ground terminal 136 (for example, GND or circuit ground) of electronic circuit 100 is coupled in the opposite side of capacitor 134.Second electricity Second side (for example, opposite with the side of node 106) of resistance device 110 is also coupled to ground terminal 136.
In this exemplary implementation scheme, the output electric current of electronic circuit 100 is produced by second (mirror) transistor unit 128 Raw, described second (mirror) transistor unit is usually the total gate area or width having than first (mirror) transistor unit 126 It is larger about 50 to 500 times of total gate area or the big conducting transistor unit of width.In other words, by first crystal pipe device 126 and second transistor device 128 formed current mirror 122 compared with other conventional current mirror grades, can have relatively high Conduction ratio.The frequency compensation of electronic circuit 100 is provided by output capacitor 134, and the output capacitor is in electronic circuit 100 Generate dominant frequency pole.The pole frequency generated by the grid capacitance of second (mirror) transistor unit 128 is by the first mirror crystal Pipe device 126 increases.Note that also generating frequency pole at the output 114 of first amplifier 102 due to the capacitor at output 114 Point.However, the output impedance (and being therefore voltage gain) of the first amplifier 102 suitably reduces according to design alternative, thus Keep this pole non-dominant.In addition, noticing that the following content is useful at this time: for example, depend on designing or manufacturing preference, it can Implemented using p-channel metal-oxide semiconductor (MOS) (PMOS) or n-channel MOS (NMOS) transistor unit as described herein all Transistor unit.It should be noted that in some embodiments, not using first (mirror) transistor unit 126, therefore without using output Current mirror (122), and output stage is generally made of output transistor 128.
Fig. 2 is the schematic block diagram of the second electronic circuit 200, and second electronic circuit can be used for implementing of the invention Two exemplary implementation schemes.For example, electronic circuit 200 can be used for implementing ringing for the enhanced transient state in semiconductor structure The adaptive-biased LDO voltage stabilizer of second answered, such as semiconducter IC, chip, chip or bare die.
With reference to exemplary implementation scheme shown in Fig. 2, electronic circuit 200 (for example, LDO voltage stabilizer) includes the first amplification Device 202, first amplifier are the input stages for also functioning as the error amplifier in circuit 200.In this exemplary implementation scheme In, the first amplifier 202 is voltage gain amplifier, and current offset level is by its output voltage control (for example, self-bias is put Big device).First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 204 of the first amplifier 202.? In some embodiments, the first input voltage is the fixed reference potential generated in electronic circuit 200.In other embodiments In, the first input voltage is variable reference voltage (for example, being changed by D/A converter).In some embodiments, first Input voltage generates outside electronic circuit 200, and is coupled to input 204 for example, by the pin of semiconducter IC or chip.The Two input voltages (for example, feedback voltage or Vfb) are from the node 206 for being connected to first resistor device 208 and second resistor 210 (for example, resistive voltage divider) is coupled to the anti-phase input 212 of the first amplifier 202, and the output voltage of the first amplifier 202 Bias current control 216 (that is, automatic biasings) of input of the first amplifier 202 are coupled back into from the output 214 of the first amplifier 202, And it is also connected to the input 218 of the second amplifier 220.In this exemplary implementation scheme, the second amplifier 220 is reverse phase mutual conductance Amplifier, second amplifier form the driving current for being used for current mirror output stage 222.More precisely, the second amplifier The drain terminal of the first crystal pipe device 226 of current mirror output stage 222 is coupled in 220 output 224, and is additionally coupled to third The input 201 of (for example, buffering) amplifier 203.First crystal pipe device 226 is coupled in the output 205 of third amplifier 203 Gate terminal, and it is additionally coupled to the gate terminal of the second transistor device 228 of current mirror output stage 222.
In this exemplary implementation scheme, electronic circuit 200 exports electric current by second (mirror) of current mirror output stage 222 Transistor unit 228 generates.Second transistor device 228 is usually with total grid than first (mirror) transistor unit 226 Area or width are larger about 50 to 500 times of total gate area or the big conducting transistor unit of width.Note that showing shown in In example property embodiment, the output 224 and first crystal pipe device 226 and second transistor for being coupled in the second amplifier 220 are filled The combination for setting the third amplifier 203 between 228 gate terminal is formed through buffer current mirror output stage 222.In other words, example Such as, third amplifier 203 serves as buffer amplifier or voltage follower, with the second transistor of driven current mirror output stage 222 The relatively large grid capacitance of device 228.Therefore, third amplifier 203 can be used for increasing total band of current mirror output stage 222 Width, to be more than the total bandwidth of the current mirror output stage 122 of electronic circuit 100.However, because using additional circuit unit, So this enhancing can be slightly above electronic circuit 100 current drain in electronic circuit 200 is slightly offset.
The source terminal of first crystal pipe device 226 and second transistor device 228 is coupled to the input of electronic circuit 200 Terminal 230 is (for example, VIN).The drain terminal of second transistor device 228 be coupled to first resistor device 208 side (for example, with The side of node 206 is opposite) and electronic circuit 200 output terminal 232 (for example, VOUT).Capacitor 234 is (for example, output Capacitor) side be coupled to output terminal 232, and the ground terminal of electronic circuit 200 is coupled in the opposite side of capacitor 234 236 (for example, GND or circuit grounds).Second side (for example, opposite with the side of node 206) of second resistor 210 also couples To ground terminal 236.
Fig. 3 is the schematic block diagram of third electronic circuit 300, and the third electronic circuit can be used for implementing of the invention Three exemplary implementation schemes.For example, electronic circuit 300 can be used for implementing ringing for the enhanced transient state in semiconductor structure The adaptive-biased LDO voltage stabilizer of the third answered, such as semiconducter IC, chip, chip or bare die.
The exemplary implementation scheme with reference to shown in Fig. 3, electronic circuit 300 (for example, LDO voltage stabilizer) include the first amplification Device 302, first amplifier are the input stages for also functioning as the error amplifier in circuit 300.In this exemplary implementation scheme In, the first amplifier 302 is voltage gain amplifier, and current offset level is by its output voltage control (for example, self-bias is put Big device).First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 304 of the first amplifier 302.? In some embodiments, the first input voltage is the fixed reference potential generated in electronic circuit 300.In other embodiments In, the first input voltage is variable reference voltage (for example, being changed by D/A converter).In some embodiments, first Input voltage generates outside electronic circuit 300, and is coupled to input 304 for example, by the pin of semiconducter IC or chip.The Two input voltages (for example, feedback voltage or Vfb) are from the node 306 for being connected to first resistor device 308 and second resistor 310 (for example, resistive voltage divider) is coupled to the anti-phase input 312 of the first amplifier 302, and the output voltage of the first amplifier 302 It is coupled to the input 318 of the second amplifier 320 from the output 314 of the first amplifier 302, and is additionally coupled to third amplifier 305 Input 319.In this exemplary implementation scheme, the second amplifier 320 is inverting transconductance amplifier, the second amplifier shape At the driving current for the first current mirror output stage 322.More precisely, the output 324 of the second amplifier 320 is coupled to The gate terminal and drain terminal of the first crystal pipe device 326 of one current mirror output stage 322, and it is additionally coupled to the first current mirror The gate terminal of the second transistor device 328 of output stage 322.First crystal pipe device 326 and second transistor device 328 Source terminal is coupled to the input terminal 330 of electronic circuit 300 (for example, VIN).The drain terminal coupling of second transistor device 328 Close side (for example, opposite with the side of node 306) and the output terminal 332 of electronic circuit 300 of first resistor device 308 (for example, VOUT).It is coupled to output terminal 332, and the phase of capacitor 334 in the side of capacitor 334 (for example, output capacitor) It is coupled to the ground terminal 336 (for example, GND or circuit ground) of electronic circuit 300 in opposite side.Second side of second resistor 310 (for example, opposite with the side of node 306) is also coupled to ground terminal 336.
In this exemplary implementation scheme, the output electric current of electronic circuit 300 is generated by second transistor device 328, institute Stating second transistor device is usually that have total gate area or width than first crystal pipe device 326 be larger about 50 to 500 The big conducting transistor unit of total gate area again or width.In other words, by first crystal pipe device 326 and the second crystal The first current mirror 322 that pipe device 328 is formed has relatively high conduction ratio compared with other conventional current mirror grades.
In this exemplary implementation scheme, third amplifier 305 is also reverse phase transconductance stage, the reverse phase transconductance stage and second The reverse phase transconductance stage of amplifier 320 works similarly.The second current mirror stage 338 is coupled in the output 325 of third amplifier 305 Third transistor device 307 gate terminal, and be additionally coupled to the 4th transistor unit 309 of the second current mirror stage 338 Gate terminal and drain terminal.The bias current that the drain terminal of third transistor device 307 is coupled to the first amplifier 302 is defeated Enter 316.Therefore, third amplifier 305 passes through the third transistor device 307 of the second current mirror stage 338 and the 4th transistor dress It sets the bias current that 309 provide bias current to the first amplifier 302 and inputs 316, and the bias current is put with by second Big device 320 is supplied to the first crystal pipe device 326 of the first current mirror output stage 322 and the electric current of second transistor device 328 It is proportional.Ratio value is can be by adjusting the transconductance value of the second amplifier 320 and the third mirror crystal of the second current mirror stage 338 Mirror between pipe device 307 and the 4th transistor unit 309 is than come the design parameter that is arranged.It should be noted that 320 He of trsanscondutance amplifier 305 transconductance value can be different, and the size of the transistor of the second current mirror stage 338 is than the first current mirror stage 322 The much smaller size of transistor.
Fig. 4 is the schematic block diagram of the 4th electronic circuit 400, and the 4th electronic circuit can be used for implementing of the invention Four exemplary implementation schemes.For example, electronic circuit 400 can be used for implementing ringing for the enhanced transient state in semiconductor structure The 4th adaptive-biased LDO voltage stabilizer answered, such as semiconducter IC, chip, chip or bare die.
The exemplary implementation scheme with reference to shown in Fig. 4, electronic circuit 400 (for example, LDO voltage stabilizer) include the first amplification Device 402, first amplifier are the input stages for also functioning as the error amplifier in circuit 400.In this exemplary implementation scheme In, the first amplifier 402 is voltage gain amplifier, and current offset level is by its output voltage control (for example, self-bias is put Big device).First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 404 of the first amplifier 402.? In some embodiments, the first input voltage is the fixed reference potential generated in electronic circuit 400.In other embodiments In, the first input voltage is variable reference voltage (for example, being changed by D/A converter).In some embodiments, first Input voltage generates outside electronic circuit 400, is coupled to input 404 for example, by the pin of semiconducter IC or chip.Second Input voltage (for example, feedback voltage or Vfb) is from the 406 (example of node for being connected to first resistor device 408 and second resistor 410 Such as, resistive voltage divider) be coupled to the anti-phase input 412 of the first amplifier 402, and the output voltage of the first amplifier 402 from The input 418 of the second amplifier 420 is coupled in the output 414 of first amplifier 402, and is additionally coupled to third amplifier 405 Input 419.In this exemplary implementation scheme, the second amplifier 420 is inverting transconductance amplifier, and second amplifier is formed Driving current for the first current mirror output stage 422.More precisely, the output 424 of the second amplifier 420 is coupled to first The drain terminal of transistor unit 426, and it is additionally coupled to the input 401 of buffer amplifier 403.The output of buffer amplifier 403 405 are coupled to the gate terminal of first crystal pipe device 426, and are also connected to the second crystal of the first current mirror output stage 422 The gate terminal of pipe device 428.The source terminal of first crystal pipe device 426 and second transistor device 428 is coupled to electronics The input terminal 430 of circuit 400 is (for example, VIN).The drain terminal of second transistor device 428 is coupled to first resistor device 408 Side (for example, opposite with the side of node 406) and electronic circuit 400 output terminal 432 (for example, VOUT).Capacitor Output terminal 432 is coupled in the side of 434 (for example, output capacitors), and electronic circuit is coupled in the opposite side of capacitor 434 400 ground terminal 436 (for example, GND or circuit ground).Second side of second resistor 410 is (for example, one with node 406 Side is opposite) it is also coupled to ground terminal 436.
In this exemplary implementation scheme, the output electric current of electronic circuit 400 is by the second of the first current mirror output stage 422 Transistor unit 428 generates.Second transistor device 428 is usually with total gate area than first crystal pipe device 426 Or width is larger about 50 to 500 times of total gate area or the big conducting transistor unit of width.In other words, by first crystal The first current mirror 422 that pipe device 426 and second transistor device 428 are formed can have compared with other conventional current mirror grades Relatively high conduction ratio.
In this exemplary implementation scheme, third amplifier 405 is also reverse phase transconductance stage, the reverse phase transconductance stage and the The reverse phase transconductance stage of two amplifiers 420 works similarly.The second current mirror stage is coupled in the output 425 of third amplifier 405 The gate terminal of 438 third transistor device 407, and it is additionally coupled to the 4th transistor unit 409 of the second current mirror stage 438 Gate terminal and source terminal.The drain terminal of third transistor device 407 is coupled to the bias current of the first amplifier 402 Input 416.Therefore, third amplifier 405 passes through the third transistor device 407 and the 4th transistor of the second current mirror stage 438 Device 409 by bias current provide to the first amplifier 402 bias current input 416, and the bias current with by second Amplifier 420 is supplied to the first crystal pipe device 426 of the first current mirror output stage 422 and the electricity of second transistor device 428 It flows proportional.Ratio value is can be by adjusting the transconductance value of the second amplifier 420 and the third crystal of the second current mirror stage 438 Mirror between pipe device 407 and the 4th transistor unit 409 is than come the design parameter that is arranged.
Note that in the illustrated exemplary embodiment, being coupled in output 424 and the first crystal of the second amplifier 420 The combination of buffer amplifier 403 between pipe device 426 and the gate terminal of second transistor device 428 is used to form through buffering Current mirror output stage 422.In other words, for example, buffer amplifier 403 serves as buffer amplifier or voltage follower to drive The relatively large grid capacitance of the second transistor device 428 of one current mirror stage 422.Therefore, buffer amplifier 403 is for increasing Add the total bandwidth of current mirror output stage 422, to be more than the total bandwidth of the current mirror output stage 322 of electronic circuit 300.It should infuse Meaning, the transconductance value of trsanscondutance amplifier 420 and 405 can be different, and the size of the transistor of the second current mirror stage 438 is comparable The much smaller size of the transistor of first current mirror stage 422.
Fig. 5 is the schematic circuit of exemplary semiconductor structure 500, and the semiconductor structure includes that can be used for implementing electricity The electronic circuit of sub-circuit 200 or electronic circuit 400 is (for example, be used for the adaptive-biased LDO pressure stabilizing of enhanced transient response Device).For example, semiconductor structure 500 can be semiconducter IC, chip, chip or bare die.In this embodiment, buffering is put Big device is included in circuit 500, for example to generate through buffer current mirror output stage, as shown in figs. 2 and 4 through buffer circuit Mirror output stage 222,422.
The exemplary implementation scheme with reference to shown in Fig. 5 (and for example, by Fig. 5 structure and Fig. 2 and Fig. 4 shown in Structure be compared), semiconductor structure 500 include the first amplifier 502 (for example, by the dotted line including transistor M1 to M4 Instruction), first amplifier is the input stage for also functioning as error amplifier.In this exemplary implementation scheme, the first amplification Device 502 is voltage gain amplifier, and current offset level is by its output voltage control (for example, self biased amplifier).Crystal Pipe 501 is coupled to the first amplifier 502, and response be coupled to the gate terminal of transistor 501 input voltage (for example, BIAS), transistor 501 generates fixed bias current, and therefore for the first amplifier 502, to provide benchmark inclined at for example light load Set electric current.In some embodiments, input voltage (BIAS) is the fixed voltage generated in semiconductor structure 500.Other In embodiment, input voltage (BIAS) is variable reference voltage (for example, being changed by D/A converter).In some implementations In scheme, input voltage (BIAS) generates outside semiconductor structure 500, and for example, by semiconducter IC or the pin coupling of chip Close the gate terminal of transistor 501.
First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 504 of the first amplifier 502 (grid of transistor M1).In some embodiments, the first input voltage is the fixed reference generated in semiconductor structure 500 Voltage.In other embodiments, the first input voltage generates outside semiconductor structure 500, and for example, by semiconducter IC Or the pin of chip is coupled to input 504.Second input voltage (for example, feedback voltage or Vfb) is from being connected to first resistor device 508 and the node 506 (for example, resistive voltage divider) of second resistor 510 be coupled to the anti-phase input of the first amplifier 502 512 (for example, grids of transistor M2).The output voltage of first amplifier 502 is coupled to from the output 514 of the first amplifier The gate terminal (input) of two amplifiers 520 (transistor M9), and it is additionally coupled to the grid of third amplifier 505 (transistor M5) Terminal (input).
In this exemplary implementation scheme, the second amplifier 520 is inverting transconductance amplifier, and second amplifier is formed Driving current for the first current mirror output stage 522.More precisely, output (drain terminal) coupling of the second amplifier 520 The input of buffer amplifier 503 (for example, being indicated by the dotted line including transistor M10 to M13) is closed, and is additionally coupled to the first crystalline substance The drain terminal of body pipe device 526 (via transistor M10, the M12 for being connected with diode).The output 515 of buffer amplifier 503 It is coupled to the gate terminal of first crystal pipe device 526, and is also connected to the second transistor dress of the first current mirror output stage 522 Set 528 gate terminal.The source terminal of first crystal pipe device 526 and second transistor device 528 is coupled to semiconductor junction The input terminal 530 of structure 500 is (for example, VIN).The drain terminal of second transistor device 528 is coupled to first resistor device 508 The output terminal 532 of side (for example, opposite with the side of node 506) and semiconductor structure 500 is (for example, VOUT).Capacitor Output terminal 532 is coupled in the side of 534 (for example, output capacitors), and semiconductor junction is coupled in the opposite side of capacitor 534 The ground terminal 536 (for example, GND or circuit ground) of structure 500.Second side of second resistor 510 is (for example, with node 506 Side is opposite) it is also coupled to ground terminal 536.
In this exemplary implementation scheme, the output electric current of semiconductor structure 500 is by the of the first current mirror output stage 522 Two-transistor device 528 generates.Second transistor device 528 usually has may be than total grid of first crystal pipe device 526 Pole-face product or width are larger about 50 to 500 times of total gate area or the big conducting transistor unit of width.In other words, by The first current mirror 522 that one transistor unit 526 and second transistor device 528 are formed compared with other conventional current mirror grades, There can be relatively high conduction ratio.
In this exemplary implementation scheme, third amplifier 505 is also reverse phase transconductance stage, the reverse phase transconductance stage and second The reverse phase transconductance stage of amplifier 520 works similarly.The second electric current is coupled in the output (drain terminal) of third amplifier 505 The gate terminal of the third transistor device 507 of mirror grade 538 (for example, being indicated by the dotted line including transistor M5 to M7), and also It is coupled to the gate terminal and drain terminal of the 4th transistor unit 509 of the second current mirror stage 538.Third transistor device 507 drain terminal is coupled to the bias current input (source electrode of M1, M2) of the first amplifier 502.Therefore, third amplifier 505 are provided bias current by the third transistor device 507 and the 4th transistor unit 509 of the second current mirror stage 538 The bias current of first amplifier 502 inputs (source electrode of M1, M2), and the bias current is supplied with by the second amplifier 520 It is proportional to the first crystal pipe device 526 of the first current mirror output stage 522 and the electric current of second transistor device 528.Ratio Value be can by adjusting the second amplifier 520 transconductance value (for example, the ruler by adjusting transistor M5 relative to transistor M9 It is very little) and the third transistor device 507 and the 4th transistor unit 509 of the second current mirror stage 538 between mirror ratio be arranged Design parameter.It should be noted that the transconductance value of trsanscondutance amplifier 520 and 505 can be different, and the second current mirror stage 538 Much smaller size of the size of transistor than the transistor of the first current mirror stage 522.
Note that in the illustrated exemplary embodiment, it is coupled in the output (drain terminal) of the second amplifier 520 and the The combination of buffer amplifier 503 between one transistor 526 and the gate terminal of second transistor 528 is used to form through buffering electricity Flow mirror output stage 522.In other words, for example, buffer amplifier 503 serves as buffer amplifier or voltage follower, to drive The relatively large grid capacitance of the second transistor device 528 of one current mirror output stage 522.Therefore, buffer amplifier 503 is used In increase current mirror output stage 522 total bandwidth, thus be more than it is other without buffer current mirror output stage (for example, shown in Fig. 3 Current mirror output stage 322) total bandwidth.
In operation, with reference to Fig. 5, when semiconductor structure 500 is for example embodied as LDO voltage stabilizer, consider following two Output condition or state: 1) pass through 532 (V of output terminalOUT) load current be stable (DC)；And 2) pass through output end 532 (V of sonOUT) load current increase suddenly.For example, in steady state operation, semiconductor structure 500 substantially utilizes three A current mirror stage operation: the 1) current mirror pair formed by transistor 526 and 528；2) electric current formed by transistor 520 and 505 Mirror pair；And 3) current mirror formed by transistor 509 and 507 is to (that is, M5 and M9).These three current mirror stages generate tail current And tail current is coupled to difference transistor to the source terminal of M1 and M2 (for example, the first amplifier by (passing through transistor 507) 502 bias current input).The value of this tail current is generally designed to the transistor 528 by the first current mirror output stage 522 The sub-fraction of output electric current (therefore the size of the transistor of the second current mirror stage 538 is usually the first current mirror stage 522 The sub-fraction of the size of transistor).In steady state operation, the overall feedback circuit of semiconductor structure 500 is in equilibrium state, And the feedback voltage Vfb at node 506 is approximately equal to reference voltage Vref.In this way, when the value for exporting electric current is relatively small (for example, stable state), transistor 501 generate first and put in response to being applied to the value of the voltage (BIAS) of the grid of transistor 501 The quiescent bias current of big device 502, and by the possible very little of bias current that transistor 507 generates, it is even insignificant.
In the second mode of operation, pass through 532 (V of output terminalOUT) load current increase suddenly.In semiconductor structure Before 500 overall feedback circuit can react to the change of this state, additional load current puts output capacitor 534 Electricity, and output voltage V is reduced in turnOUTValue.This reduction of output voltage reduces the feedback voltage Vfb at node 506 Value, the feedback voltage are applied to the voltage of the gate terminal of the transistor M2 of the first amplifier 502.The grid of transistor M2 The gained of voltage, which reduces, keeps the input voltage of differential pair transistors M1 and M2 uneven, to increase the electricity for passing through transistor M2 Stream, and increase the voltage for being applied to the grid of transistor 505 and 520 in turn.The resulting increased electric leakage circulation of transistor 505 The bias current that overcurrent mirror transistor feeds back to the first amplifier 502 to 509 and 507 inputs, to increase positive generation again Tail current value.This increase of tail current, which increases, to be increased by the electric current of transistor M2, and in turn with positive (increased) rate Add the voltage at the gate terminal of transistor 505 and 520.Meanwhile by the increased electric current of transistor 520 to output transistor 528 big gate capacitance charges (for example, passing through buffer amplifier 503), supply enough until the drain current of transistor 528 and bear Until carrying electric current.At this moment, output voltage VOUTMagnitude back to institute increased electric current to output capacitor 534 charging when it is steady State.In this way, the adaptive-biased arrangement (input stage) of the first amplifier 502 makes the levels of current of the first order increase to overall feedback On the equilibrium level in circuit, quickly to give the gate capacitance charges of output transistor 528.Therefore, reach new stable state Condition, adaptive bias reach new equilibrium valve, the equilibrium valve by transistor to 528 and 526,520 and 505 and 509 and 507 gate area (or width) ratio explicitly defines.
In short, the relatively large grid capacitance of transistor 528 is connected in adaptive-biased circuit according to the teaching of the application It is external.Adaptive-biased circuit by increase adaptive bias value to respond increased load current, so as to faster Gate capacitance charges of the ground to conducting transistor 528.Because the grid capacitance of transistor 528 is connected in adaptive-biased circuit Outside, so the response time in adaptive-biased circuit is significantly faster than that the response in the normal bias circuit in conventional LDO voltage stabilizer Time, and the resulting output voltage for the LDO voltage stabilizer implemented using semiconductor structure 500 falls that be significantly less than conventional LDO steady The output voltage of depressor falls.
Note that using positive feedback in the exemplary implementation scheme of semiconductor structure 500.Therefore, obtained in bias current Increase changes in the operating point of the first amplifier 502, to increase generated adaptive bias again.By In the exemplary implementation scheme that semiconductor structure 500 is described, positive loop feedback gain is designed to less than 1, adaptive to ensure The stability of bias loop.For example, selection transistor size design is so that adaptively feedback transistor 505 is to be crystal Twice of current density operation of the current density of pipe M3 and M4.Therefore, because mutual conductance/drain current ratio (GM/Id) is with electricity Current density and reduce, the loop gain less than 1 is ensured.
Fig. 6 is the schematic circuit of exemplary semiconductor structure 600, and the semiconductor structure includes that can be used for implementing scheming The electronic circuit of electronic circuit 100 or electronic circuit 300 shown in 1 and Fig. 3 is (for example, as enhanced transient response is used for Adaptive-biased LDO voltage stabilizer).For example, semiconductor structure 600 can be semiconducter IC, chip, chip or bare die. Note that semiconductor structure 600 is structurally and operationally substantially similar to the structure of semiconductor structure 500 and behaviour shown in Fig. 5 Make, but buffer amplifier grade (for example, 503 in Fig. 5) is not included in semiconductor structure 600.
The exemplary implementation scheme with reference to shown in Fig. 6 (and for example, by Fig. 6 structure and Fig. 1 and Fig. 3 shown in Structure is compared), semiconductor structure 600 includes the first amplifier 602 (for example, being referred to by the dotted line including transistor M1 to M4 Show), first amplifier is the input stage for also functioning as error amplifier.In this exemplary implementation scheme, the first amplifier 602 be voltage gain amplifier, and current offset level is by its output voltage control (for example, self biased amplifier).Transistor 601 are coupled to the first amplifier 602, and the input voltage (for example, BIAS) of the gate terminal of transistor 601 is coupled in response, Transistor 601 generates fixed bias current, and therefore provides reference offset electricity at for example light load for the first amplifier 602 Stream.In some embodiments, input voltage (BIAS) is the fixed voltage generated in semiconductor structure 600.In other implementations In scheme, input voltage (BIAS) is variable reference voltage (for example, being changed by D/A converter).In some embodiments In, input voltage (BIAS) generates outside semiconductor structure 600, and is coupled to for example, by the pin of semiconducter IC or chip The gate terminal of transistor 601.
First input voltage (for example, reference voltage or Vref) is coupled to the non-inverting input 604 of the first amplifier 602 (grid of transistor M1).In some embodiments, the first input voltage is the fixed reference generated in semiconductor structure 600 Voltage.In other embodiments, the first input voltage generates outside semiconductor structure 600, and for example, by semiconducter IC Or the pin of chip is coupled to input 604.Second input voltage (for example, feedback voltage or Vfb) is from being connected to first resistor device 608 and the node 606 (for example, resistive voltage divider) of second resistor 610 be coupled to the anti-phase input of the first amplifier 602 612 (grids of transistor M2).The output voltage of first amplifier 602 is coupled to second from the output 614 of the first amplifier 602 The gate terminal (input) of amplifier 620 (transistor M9), and it is additionally coupled to the gate terminal of third amplifier 605 (transistor M5) Sub (input).
In this exemplary implementation scheme, the second amplifier 620 is inverting transconductance amplifier, and second amplifier is formed Driving current for the first current mirror output stage 622.More precisely, output (drain terminal) coupling of the second amplifier 620 The drain terminal of first crystal pipe device 626 is closed, and is additionally coupled to the first crystal pipe device of the first current mirror output stage 622 626 and second transistor device 628 gate terminal.The source terminal of first crystal pipe device 626 and second transistor device 628 Son is coupled to the input terminal 630 of semiconductor structure 600 (for example, VIN).The drain terminal of second transistor device 628 is coupled to The side (for example, opposite with the side of node 606) of first resistor device 508 and the output terminal 632 of semiconductor structure 600 (for example, VOUT).It is coupled to output terminal 632, and the phase of capacitor 634 in the side of capacitor 634 (for example, output capacitor) It is coupled to the ground terminal 636 (for example, GND or circuit ground) of semiconductor structure 600 in opposite side.The second of second resistor 610 Side (for example, opposite with the side of node 606) is also coupled to ground terminal 636.
In this exemplary implementation scheme, the output electric current of semiconductor structure 600 is by the of the first current mirror output stage 622 Two-transistor device 628 generates.Second transistor device 628 usually has may be than total grid of first crystal pipe device 626 Pole-face product or width are larger about 50 to 500 times of total gate area or the big conducting transistor unit of width.In other words, by The first current mirror output stage 622 and other conventional current mirror grades that one transistor unit 626 and second transistor device 628 are formed It compares, can have relatively high conduction ratio.
In this exemplary implementation scheme, third amplifier 605 is also reverse phase transconductance stage, the reverse phase transconductance stage and second The reverse phase transconductance stage of amplifier 620 works similarly.The second electric current is coupled in the output (drain terminal) of third amplifier 605 The gate terminal of the third transistor device 607 of mirror grade 638 (for example, being indicated by the dotted line including transistor M5 to M7), and also It is coupled to the gate terminal and drain terminal of the 4th transistor unit 609 of the second current mirror stage 638.Third transistor device 607 drain terminal is coupled to the bias current input (source electrode of M1, M2) of the first amplifier 602.Therefore, third amplifier 605 are provided bias current by the third transistor device 607 and the 4th transistor unit 609 of the second current mirror stage 638 The bias current of first amplifier 602 inputs (source electrode of M1, M2), and the bias current is supplied with by the second amplifier 620 It is proportional to the first crystal pipe device 626 of the first current mirror output stage 622 and the electric current of second transistor device 628.Ratio Value is can be by adjusting the transconductance value of the second amplifier 620 and the third transistor device 607 of the second current mirror stage 638 and Mirror between four transistor units 609 is than come the design parameter that is arranged.
In operation, with reference to Fig. 6, when semiconductor structure 600 is embodied as such as LDO voltage stabilizer, consider following two Output condition or state: 1) pass through 632 (V of output terminalOUT) load current be stable (DC)；And 2) pass through output end 632 (V of sonOUT) load current increase suddenly.For example, in steady state operation, semiconductor structure 600 substantially utilizes three A current mirror stage operation: the 1) current mirror pair formed by transistor 626 and 628；2) electric current formed by transistor 620 and 605 Mirror pair；And 3) current mirror formed by transistor 609 and 607 is to (M5 and M9).These three current mirror stages generate tail current, and Tail current is coupled to difference transistor to M1 and M2 (for example, the bias current of the first amplifier 602 by (passing through transistor 607) Input).The value of this tail current is designed to the one small of the output electric current by the transistor 628 of the first current mirror output stage 622 Part.In steady state operation, the overall feedback circuit of semiconductor structure 600 is in equilibrium state, and the feedback electricity at node 606 Pressure Vfb is approximately equal to reference voltage Vref.In this way, when the value for exporting electric current is relatively small (for example, stable state), transistor 601 in response to be applied to the value of the voltage (BIAS) of the grid of transistor 601 and generate the first amplifier 602 quiescent biasing electricity Stream, and by the possible very little of bias current that transistor 607 generates, it is even insignificant.
In the second mode of operation, pass through 632 (V of output terminalOUT) load current increase suddenly.In semiconductor structure Before 600 overall feedback circuit can react to the change of this state, additional load current puts output capacitor 634 Electricity, and output voltage V is reduced in turnOUTValue.This reduction of output voltage reduces the feedback voltage level Vfb's at node 606 Value, the feedback voltage are applied to the voltage of the gate terminal of the transistor M2 of the first amplifier 602.The grid of transistor M2 The gained of voltage, which reduces, keeps the input voltage of differential pair transistors M1 and M2 uneven, to increase the electricity for passing through transistor M2 Stream, and increase the voltage for being applied to the grid of transistor 605 and 620 in turn.The resulting increased electric leakage circulation of transistor 605 The bias current that overcurrent mirror transistor feeds back to the first amplifier 602 to 609 and 607 inputs, to increase positive generation again Tail current value.This increase of tail current, which increases, to be increased by the electric current of transistor M2, and in turn with positive (increased) rate Add the voltage at the gate terminal of transistor 605 and 620.Meanwhile output is quickly given by the increased electric current of transistor 620 The big gate capacitance charges of transistor 628, until the drain current of transistor 628 supplies load current enough.At this moment, defeated Voltage V outOUTMagnitude back to institute increased electric current to output capacitor 634 charging when stable state.In this way, the first amplifier 602 adaptive-biased arrangement (input stage) make the levels of current of the first order increase to overall feedback circuit equilibrium level it On, to give the gate capacitance charges of output transistor 628.Therefore, reach new limit, adaptive bias reaches New equilibrium valve, the equilibrium valve are clear to 628 and 626,620 and 605 and 609 and 607 gate area ratio by transistor Definition.
In short, the relatively large grid capacitance of transistor 628 is connected at adaptive-biased time according to the teaching of the application Outside road.Adaptive-biased circuit responds increased load current by increasing the value of adaptive bias, so as to faster Gate capacitance charges of the ground to conducting transistor 628.Because the grid capacitance of transistor 628 is connected in adaptive-biased circuit Outside, so the response time in adaptive-biased circuit is significantly faster than that the response in the normal bias circuit in conventional LDO voltage stabilizer Time, and the resulting output voltage for the LDO voltage stabilizer implemented using semiconductor structure 600 falls that be significantly less than conventional LDO steady The output voltage of depressor falls.
Note that using positive feedback in the exemplary implementation scheme of semiconductor structure 600.Therefore, obtained in bias current Increase changes in the operating point of the first amplifier 602, to increase generated adaptive bias again.By It is adaptive to ensure by positive feedback loop gain design at less than 1 in the exemplary implementation scheme that semiconductor structure 600 is described The stability of bias loop.For example, selection transistor size design is so that adaptively feedback transistor 605 is to be crystal Twice of current density operation of the current density of pipe M3 and M4.Therefore, because mutual conductance/drain current ratio (GM/Id) is with electricity The reduction of current density, the loop gain less than 1 are ensured.
Fig. 7 A and Fig. 7 B be describe one or more of the embodiment above according to the present invention and structuring it is adaptive The analogue phase allowance performance curve of LDO voltage stabilizer and the correlogram of gain margin performance curve should be biased.These curves Figure describes the simulated performance curve for being applied the adaptive-biased LDO voltage stabilizer of different electrical power voltage, temperature and process corner.Water Flat (X) axis indicates applied load current, and vertical (Y) axis instruction is for the different behaviour of related LDO voltage stabilizer simulation Make the phase margin value or gain margin value of condition and different output current level.
Note that being given to the offer of the acceptable level of circuit stability quite big as curve graph 700a and 700b are indicated Design concern, the acceptable level is on all possible potential operating conditions met with and output levels of current.However, This level of stability is usually directed to the significant tradeoff to quiescent current.However, LDO as shown in figures 7 a and 7b is adjusted Indicated by device performance characteristics, these analog results confirm that the embodiment above of the invention can be used for implementing LDO voltage stabilizer, institute State the acceptable level for the circuit stability that LDO voltage stabilizer is realized for both small signal and big signal.In other words, such as curve Shown in Figure 70 0a and 700b, for all different operation conditions (for example, supply voltage, temperature, process corner) and applied Output levels of current for, the overall performance of related LDO voltage stabilizer is generally similar.
Fig. 8 is to describe above-mentioned teaching according to the application and the simulation transient state of the adaptive-biased LDO voltage stabilizer of structuring The curve graph of load response.For the simulation shown in, 300mA load current step-length is applied to adaptively at 500 μ s Bias LDO voltage stabilizer.Note that Fig. 8 shows the transient voltage drop performance more than conventional LDO voltage stabilizer transient voltage drop performance Improve mainly by being more than that the increased response speed of response speed of conventional LDO voltage stabilizer generates.For example, institute in Fig. 8 Show, simulates the output voltage of LDO voltage stabilizer at about 500.45 μ s " falling " to about 2.176V (802).In significant comparison, The output voltage of conventional LDO voltage stabilizer will drop at least 2.142V at 500.5 μ s or in the time later.In this way, with routine LDO voltage stabilizer is compared, and the enhanced transient response of adaptive-biased LDO voltage stabilizer is mainly implemented as follows.It is somewhat similarly to routine LDO voltage stabilizer, the output voltage of adaptive-biased LDO voltage stabilizer drop when the increased load of institute to output capacitor for discharging It is low.However, adaptive-biased LDO voltage stabilizer increases its bias current, so as to quickly to the grid of conducting transistor unit Electrode capacitance charging.The transient response time of adaptive-biased feedback loop is rung than the transient state in the overall feedback circuit of LDO voltage stabilizer Much shorter between seasonable, and therefore, adaptive-biased LDO voltage stabilizer is more steady than the conventional LDO for not having adaptive-biased feedback loop Depressor responds more quickly load transient, and (wherein described more adaptive than the conventional LDO voltage stabilizer with adaptive-biased feedback The input capacitance that feedback loop includes usual biggish output device should be biased) respond more quickly load transient.In addition, adaptive LDO voltage stabilizer transient state experienced should be biased fall and be significantly less than conventional LDO voltage stabilizer transient state experienced and fall.
Fig. 9 is to describe adaptive-biased LDO voltage stabilizer in High Operating Temperature (125C), 2.5V input voltage (for example, VIN) With 2.2V rated output voltage (for example, VOUT) simulated operation under the conditions of simulated performance mode curve graph.As shown in figure 9, Although simulation carries out under the conditions of a variety of different process, temperature and input voltage, the performance mould of adaptive-biased LDO voltage stabilizer Formula is generally maintained.In other words, curve graph depicted in figure 9 shows that manufacture variation (m) is steady to adaptive-biased LDO The performance of depressor have how small influence.In this way, performance change depicted in figure 9 is mainly produced from the change of operation temperature It is raw.For example, the maximum voltage that upper curve 902a to 908a shown in Fig. 9 describes adaptive-biased LDO voltage stabilizer misses Difference or transient overshoot, and lower curve 902b to 908b describe related adaptive-biased LDO voltage stabilizer minimum voltage or Transient state is fallen.Process corner of horizontal (X) the axis instruction for this simulation for following five kinds of manufacturing situations: the instruction of situation 0 is used In the process corner of typical n-channel metal-oxide semiconductor (MOS) (NMOS) and p-channel (PMOS) transistor；The instruction of situation 1 is used for The process corner of slow NMOS and PMOS transistor；The instruction of situation 2 is used for the process corner of fast NMOS and PMOS transistor；Situation 3 Indicate the process corner for being used for slow NMOS transistor and fast PMOS transistor；And the instruction of situation 4 for fast NMOS transistor and The process corner of slow PMOS transistor.In this exemplary simulated, performance curve 902a and 902b instruction are for 2.5V input electricity The circuit performance of pressure and 125C operation temperature；Curve 904a and 904b instruction are for 5.5V input voltage and 125C operation temperature Circuit performance；Curve 906a and 906b instruction are directed to the circuit performance of 5.5V input voltage and -20C operation temperature；And curve 908a and 908b instruction is directed to the circuit performance of 2.5V input voltage and -20C operation temperature.2.2V output voltage (specified) is used for All simulations.Note that simulation shown in Fig. 9 indicates the enhanced transient overshoot of above-mentioned adaptive-biased LDO voltage stabilizer and falls Fall transient overshoot and drop performance that performance is better than conventional LDO voltage stabilizer.
Figure 10 describes the schematic block diagram for being configured to the exemplary system 1000 of PMIC, and the PMIC can be used for implementing basis The semiconductor structure for enhanced transient response of one or more embodiments of the invention.In some embodiments, System 1000 can be implemented on semiconducter IC, chip, chip or bare die.In the illustrated exemplary embodiment, system 1000 It can be implemented as integrated PMIC, to be, for example, notebook computer, tablet personal computer (PC), the film in monitor Transistor liquid crystal display (TFT-LCD) (TFT-LCD) provides electric power, and is also the TFT- of small-size display (such as smart phone display) LCD provides electric power.With reference to Figure 10, for an exemplary implementation scheme, system 1000 includes being retouched according in Fig. 1 to 6 One or more of the embodiment above drawn and configure adaptive-biased LDO voltage stabilizer 1002.Adaptive-biased LDO is steady Depressor 1002 is coupled to voltage input connector 1030 to receive input voltage (VIN), and it is coupled to voltage output connector 1032 With will through adjust voltage (VOUT) it is output to the channel VLOGIC output connector 1004.From adaptive-biased LDO voltage stabilizer 1002 Through adjust output voltage be for drive be coupled to the channel VLOGIC export 1004 external digital circuit relatively low electricity Pressure.Ldo regulator 1002 is also used to be adjusted voltage and provides sequencer 1006, simulation Vdd or supply voltage (AVDD) increasing It pressure controller 1008, gate pulse modulator (GPM) 1010, voltage detector 1012 and is used as calibrator with adjusting LCD VCOMThe numerical control potentiometer (DCP) 1014 of voltage.In this exemplary system, LDO voltage stabilizer 1002 is that outside can It adjusts component (for example, via semiconducter IC or contact pin of chip), and exposes as " independence " function.In other examples system In system, LDO voltage stabilizer 1002 is not external adjustable.In this way, above-mentioned teaching according to the present invention, adaptive-biased LDO are steady Depressor 1002 provides enhanced (for example, generally faster) in system 1000 better than the transient response of conventional LDO voltage stabilizer Transient response.
Figure 11 describes the schematic block diagram for being configured to the second exemplary system 1100 of PMIC, and the PMIC can be used for implementing The semiconductor structure for enhanced transient response of one or more embodiments in accordance with the present invention.In some embodiments In, system 1100 can be implemented on semiconducter IC, chip, chip or bare die.In the illustrated exemplary embodiment, by system 1100 are embodied as the high-efficiency power for small size, hand-held display device (such as smart phone TFT-LCD).With reference to Figure 11, For an exemplary implementation scheme, system 1100 includes one according to the embodiment above discribed in Fig. 1 to 6 Or adaptive-biased LDO voltage stabilizer 1102 that is multiple and configuring.Adaptive-biased LDO voltage stabilizer 1102 is coupled in system 1100 Between current earthing 1136 and numerous other circuit units, to provide suitable decoupling for the power circuit in system 1100. In this way, in some example embodiments, adaptive-biased LDO voltage stabilizer 1102 and the adjustment of " on chip " voltage are integrated, with Just the subsequent manufacture voltage adjustment of adaptive-biased LDO voltage stabilizer 1102 is realized.Substantially, in operation, adaptive-biased LDO 1130 (the V of input of voltage-stablizer 1102IN) at voltage be from booster converter 1101 provide, the booster converter be suitable for tracking 1132 (the V of output of adaptive-biased LDO voltage stabilizer 1102OUT) at voltage, in order to provide just enough voltage drops to be provided from Adapt to biasing LDO voltage stabilizer 1102 such as required operation.In this way, teaching according to the present invention, adaptive-biased LDO voltage stabilizer 1102 Better than enhanced (for example, faster) transient response of the transient response of conventional LDO voltage stabilizer in offer system 1100.
Figure 12 is the exemplary of the adaptive-biased LDO voltage stabilizer of description one or more embodiments in accordance with the present invention The flow chart of operating method 1200.For example, method 1200 can be used for describing Fig. 1 to exemplary implementation depicted in figure 6 The operation of one or more of scheme.With reference to Figure 12, for an exemplary implementation scheme, the first amplifier (for example, Error amplifier) the suitable voltage (1202) of output, the voltage conversion (for example, passing through trsanscondutance amplifier) is at for controlling certainly Adapt to the load current of the output device (for example, conducting transistor) of biasing LDO voltage stabilizer.First amplifier also receives representative certainly Adapt to the feedback voltage (1204) of the output voltage of biasing LDO voltage stabilizer.If sent out by the received feedback voltage of the first amplifier It is raw to fall (for example, output voltage associated with the transient state of load current reduces) (1206), then falling in response to output voltage It falls, the first amplifier increases the bias current (1208) of its own using positive feedback loop.Note that positive feedback loop does not include Capacitor (for example, grid capacitance of conducting or output transistor) associated with the control terminal of output device.In response to biasing The increase of electric current, the first amplifier increase its output voltage and (for example, via trsanscondutance amplifier), and then increase and go to output dress The load current (1210) set.However, process is exported back to monitoring if (1206) feedback voltage is there is no falling Voltage (1204).
In the discussion and claims of this paper, relative to two kinds of materials'uses term " above ", one Mean that at least some are contacted between these materials in another "upper", and " on the top " means that these materials are It is close, but may have one or more additional insert layers, therefore it is possible rather than necessary for contacting.As made herein " ... upper (on) " or " ... top (over) " any direction is not implied that.Listed by term " about " instruction Value can be changed out, if it is described change not the process to illustrated embodiment or structure cause it is inconsistent.
The term of relative position used herein is based on flat with the conventional plane or working surface of chip or substrate Capable plane defines, orientation without considering chip or substrate.Term "horizontal", " transverse direction " are fixed as used in this application Justice is the plane parallel with the conventional plane or working surface of chip or substrate, the orientation without considering chip or substrate.Term " vertical " refers to the direction with horizontal vertical.Such as " ... on ", " side " (side such as in " side wall "), " higher ", " compared with It is low ", " ... on ", " top " and " ... under " be normal on chip or top surface relative to being located at The orientation that plane or working surface are advised to define, without considering chip or substrate.
Although this article has illustrated and described specific embodiment, however, it will be appreciated by those skilled in the art that plan comes in fact Any arrangement of existing identical purpose can replace shown specific embodiment.It is, therefore, apparent that wishing only to be wanted by appended right Book and its equipollent is asked to limit the present invention.

Claims (17)

1. a kind of semiconductor structure comprising:
First current mirroring circuit, first current mirroring circuit is coupled to the input pad of the semiconductor structure and output connects Fitting；
Second current mirroring circuit, second current mirroring circuit are coupled to the input pad of the semiconductor structure；
First amplifier circuit, the first input coupling of first amplifier circuit are described to second current mirroring circuit The output connector of second input coupling of the first amplifier circuit to the semiconductor structure, and first amplifier The third input coupling of circuit is to reference voltage；
Second amplifier circuit, the output of the input coupling of second amplifier circuit to first amplifier circuit, and The output coupling of second amplifier circuit is to first current mirroring circuit；And
Third amplifier circuit, the input coupling of the third amplifier circuit to the described defeated of first amplifier circuit Out, and the output coupling of the third amplifier circuit is to second current mirroring circuit.
2. semiconductor structure as described in claim 1, further include:
4th amplifier circuit, the 4th amplifier circuit be connected to the output of second amplifier circuit with it is described Between first current mirroring circuit.
3. semiconductor structure as described in claim 1, wherein the reference voltage is fixed voltage.
4. semiconductor structure as described in claim 1, wherein second input of first amplifier circuit is suitable for connecing Receive the feedback voltage proportional to the output voltage of the semiconductor structure.
5. semiconductor structure as described in claim 1, wherein first input of first amplifier circuit includes inclined Set electric current input.
6. semiconductor structure as described in claim 1, wherein first amplifier circuit includes error amplifier, described Two amplifier circuits include trsanscondutance amplifier；And the third amplifier circuit includes trsanscondutance amplifier.
7. semiconductor structure as claimed in claim 2, wherein the 4th amplifier circuit includes buffer amplifier.
8. semiconductor structure as described in claim 1, wherein the semiconductor structure includes semiconductor integrated circuit (IC), crystalline substance Adaptive-biased low voltage difference (LDO) voltage-stablizer on piece, chip or bare die.
9. semiconductor structure as described in claim 1, wherein first input of first amplifier circuit is connected to The drain terminal of the first crystal pipe device of second current mirroring circuit, and first amplifier circuit includes in turn self-bias Set amplifier circuit.
10. a kind of electronic circuit comprising:
First crystal pipe device, the first crystal pipe device are coupled to input pad and the output connection of the electronic circuit Part；
Second transistor device, the second transistor device be coupled to the first crystal pipe device of the electronic circuit with And the input pad, wherein the first transistor device and the second transistor device include the first current mirror stage, And the first crystal pipe device includes the output transistor of the electronic circuit；
Third transistor device, the third transistor device are coupled to the input pad of the electronic circuit；
4th transistor unit, the 4th transistor unit are coupled to the input pad and the institute of the electronic circuit Third transistor device is stated, wherein the third transistor device and the 4th transistor unit include the second current mirror stage；
Error amplifier, the error amplifier are coupled to the first crystal pipe device and described via the first trsanscondutance amplifier Second transistor device, and it is coupled to the third transistor device and the 4th transistor dress via the second trsanscondutance amplifier It sets, and the bias current input coupling of the error amplifier is to the drain terminal of the 4th transistor unit, wherein described Error amplifier is suitable for for reference voltage and the feedback voltage proportional to the output voltage of the electronic circuit being compared, and Current signal is coupled to first current mirror stage and second current mirror stage to drive first current mirror stage and institute State the second current mirror stage.
11. electronic circuit as claimed in claim 10 further includes voltage follower, the voltage follower is connected to described Between first trsanscondutance amplifier and first current mirror stage.
12. electronic circuit as claimed in claim 10, wherein the electronic circuit includes adaptive-biased LDO voltage stabilizer.
13. electronic circuit as claimed in claim 10, wherein the electronic circuit includes IC power supply or power management IC (PMIC) all or part of.
14. a kind of power-supply management system comprising:
Sequencer unit；
Analog power voltage (AVDD) boost controller；
Gate pulse modulator (GPM)；
Voltage detector；
Numerical control potentiometer (DCP)；And
Adaptive-biased LDO voltage stabilizer is coupled to the sequencer unit, AVDD boost controller, GPM, voltage detector With the one or more of DCP, wherein the adaptive-biased LDO voltage stabilizer includes:
First current mirroring circuit, first current mirroring circuit are coupled to the input connection of the adaptive-biased LDO voltage stabilizer Part and output connector；
Second current mirroring circuit, second current mirroring circuit are coupled to the input of the adaptive-biased LDO voltage stabilizer Connector；
First amplifier circuit, the first input coupling of first amplifier circuit are described to second current mirroring circuit Second input coupling of the first amplifier circuit to the adaptive-biased LDO voltage stabilizer the output connector, and it is described The third input coupling of first amplifier circuit is to reference voltage；
Second amplifier circuit, the output of the input coupling of second amplifier circuit to first amplifier circuit, and The output coupling of second amplifier circuit is to first current mirroring circuit；And
Third amplifier circuit, the input coupling of the third amplifier circuit to the described defeated of first amplifier circuit Out, and the output coupling of the third amplifier circuit is to second current mirroring circuit.
15. system as claimed in claim 14, wherein the system comprises be formed in semiconductor wafer, chip, IC or bare die On power supply.
16. a kind of power-supply management system comprising:
Power supply, the power supply are used for Thin Film Transistor-LCD (TFT-LCD)；And
Adaptive-biased LDO voltage stabilizer, the adaptive-biased LDO voltage stabilizer is for decoupling or switching to by the one of the power supply The circuit ground one or more frequency signal that a or multiple components generate, the adaptive-biased LDO voltage stabilizer include:
First current mirroring circuit, first current mirroring circuit are coupled to the input connection of the adaptive-biased LDO voltage stabilizer Part and output connector；
Second current mirroring circuit, second current mirroring circuit are coupled to the input of the adaptive-biased LDO voltage stabilizer Connector；
First amplifier circuit, the first input coupling of first amplifier circuit are described to second current mirroring circuit Second input coupling of the first amplifier circuit to the adaptive-biased LDO voltage stabilizer the output connector, and it is described The third input coupling of first amplifier circuit is to reference voltage；
Second amplifier circuit, the output of the input coupling of second amplifier circuit to first amplifier circuit, and The output coupling of second amplifier circuit is to first current mirroring circuit；And
Third amplifier circuit, the input coupling of the third amplifier circuit to the described defeated of first amplifier circuit Out, and the output coupling of the third amplifier circuit is to second current mirroring circuit.
17. system as claimed in claim 16, wherein the system comprises be formed in semiconductor wafer, chip, IC or bare die On PMIC or power supply.
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