KR20170040731A - Low Drop-Out regulator and display device including the same - Google Patents

Abstract

According to an embodiment of the present invention, a low drop-out regulator comprises: a pass transistor configured to regulate an input power voltage according to a control signal to output the input power voltage as an output voltage; a feedback unit configured to generate the feedback voltage in response to the output voltage; an error amplifier configured to receive a reference voltage and the feedback voltage to output a comparison signal; and a correction circuit configured to generate negative capacitance to a first node to which the gate electrode of the pass transistor is connected.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low dropout regulator and a display device including the low dropout regulator,

The present invention relates to a low dropout (LDO) regulator, and more particularly, to a LDO regulator having a high power supply rejection ratio (PSRR) characteristic and a display device having the same.

A voltage regulator is used to stably supply power to an electronic device such as a display device or the like. Voltage regulators are classified as linear regulators and switching regulators.

DC-DC converter (DC-DC converter) is a kind of switching regulator. DC-DC converters have high conversion efficiency. However, the output voltage of the DC-DC converter includes more noise than the output voltage of the linear regulator.

 Low-dropout (LDO) regulators are a type of linear regulator. LDO regulators have low conversion efficiency, but have a fast response time. In other words, an LDO regulator can provide a stable voltage, even though the output voltage is lower than the input voltage and there is power loss.

In addition, the output voltage of the LDO regulator includes a small amount of noise compared to the output voltage of the DC-DC converter. Therefore, an LDO regulator can be used to compensate for the shortcomings of the DC-DC converter. In particular, an LDO regulator may be used to power a noise sensitive device or a device that must be driven at high performance.

Power Supply Rejection Ratio (PSRR) is the ratio of input voltage noise to output voltage noise supplied to the power supply. The PSRR is used as an indicator of the degree to which the input voltage noise is effectively blocked by a voltage regulator in a certain frequency band and is stably supplied with voltage.

When the input voltage of the voltage regulator includes noise, the output voltage of the voltage regulator does not maintain a constant value due to noise. Particularly, in a high frequency band of several hundred kHz or a few MHz or more, which is larger than the gain crossover frequency of the closed loop of the linear regulator, the input voltage noise of the linear regulator is not effectively blocked. Therefore, it is difficult to form a stable output voltage in the high frequency band.

Embodiments of the present invention provide a low-dropout regulator and a display device having the low-dropout regulator.

According to an aspect of the present invention, there is provided a low-voltage dropout regulator including: a pass transistor for regulating an input voltage according to a control signal; And a compensation circuit for providing a negative capacitance to a gate node of the pass transistor, wherein the control signal is formed based on a feedback signal, a reference input signal, and the negative capacitance associated with the output voltage of the pass transistor.

According to another aspect of the present invention, there is provided a low-voltage dropout regulator including: a pass transistor that regulates an input supply voltage according to a control signal and outputs the regulated output voltage; A feedback unit for generating a feedback voltage in response to the output voltage; An error amplifier receiving the reference voltage and the feedback voltage and outputting a comparison signal; And a compensation circuit for generating a negative capacitance at a first node to which the gate electrode of the pass transistor is connected.

The pass transistor includes: a first electrode connected to the input power supply voltage; A second electrode connected to a second node through which the output voltage is output; And a gate electrode to which the control signal is inputted.

The reference voltage is input to the inverting input terminal (-) of the error amplifier, and the feedback voltage is input to the non-inverting input terminal (+) of the error amplifier.

The size of the negative capacitance is substantially equal to the sum of the parasitic capacitance at the first node and the capacitance between the gate and drain electrodes of the pass transistor.

The pass transistor is connected to a second node to which the output voltage is output, and a load capacitance is formed at an output terminal corresponding to the second node. The load capacitance may be implemented with parasitic capacitance.

The compensation circuit includes an OP amplifier and a compensation capacitor connected to the non-inverting amplifier and a non-inverting amplifier composed of a first resistor and a second resistor connected between the output terminal of the OP amplifier and ground.

The operational amplifier has a wider operating bandwidth than the error amplifier, and at least one of the first resistor and the second resistor is a variable resistor.

A signal corresponding to the control signal is input to the non-inverting input terminal (+) of the operational amplifier, and an inverting input terminal (-) is connected to the output voltage of the operational amplifier .

The compensation circuit further includes a source follower connected to the input of the non-inverting amplifier.

The source follower includes a transistor having a first electrode coupled to the input power supply voltage, a second electrode coupled to the current sink, and a control signal applied to the gate electrode.

And the transistor included in the source follower portion is a transistor of a type different from that of the pass transistor.

A display device according to an embodiment of the present invention includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; A gate driver for outputting a gate signal to the gate lines; And a voltage generator for receiving an input voltage, converting the analog voltage into an analog voltage, and outputting the analog voltage to the gate driver and / or the source driver, wherein the voltage generator includes a DC- And an LDO regulator, wherein the LDO regulator includes a compensation circuit that generates a negative capacitance.

According to the embodiment of the present invention as described above, by providing the compensation circuit capable of eliminating the influence of the parasitic capacitance generated at the gate node of the pass transistor, the gate-source voltage difference of the pass transistor is removed, (PSRR) characteristics can be improved.

In addition, the LDO regulator according to the embodiment of the present invention can output a stable output voltage even in a high frequency band while eliminating a large capacity load capacitor having a large area through the compensation circuit. Accordingly, It can operate as an optimal regulator that provides a stable voltage with a small area to the analog circuits of the necessary Display Driver IC (DDI).

1 is a circuit diagram of a low-dropout regulator;
2 is a small signal modeling circuit for the low-dropout regulator shown in FIG.
3 is a circuit diagram of a low-voltage drop regulator according to an embodiment of the present invention.
4 is a small-signal modeling circuit for the low-dropout regulator shown in FIG.
Figure 5 is a circuit diagram of a low-dropout regulator including one embodiment of the compensation circuit shown in Figure 4;
6 is a graph showing PSRR characteristics of a low-voltage dropout regulator according to an embodiment of the present invention.
7 is a block diagram of a display device according to an embodiment of the present invention;
8 is a block diagram showing the configuration of the voltage generator shown in Fig.

It is to be understood that the description in the technical field of the background of the present invention is only for the understanding of the background art on the technical idea of the present invention and therefore it can be understood that it corresponds to the prior art known to a person skilled in the art none.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that the various embodiments may be practiced without these specific details, or with one or more equivalents. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the various embodiments unnecessarily.

In the drawings, the sizes or relative sizes of layers, films, panels, regions, etc. may be exaggerated for clarity. Also, like reference numerals designate like elements.

Throughout the specification, if an element or layer is described as being "connected" to another element or layer, it is not only directly connected but also indirectly connected with another element or layer in between . However, if a part is described as "directly connected" to another part, it will mean that there is no other element between that part and the other part. At least one selected from the group consisting of "X, Y and Z and at least one selected from the group consisting of X, Y and Z" is X, Y, Z, (E.g., XYZ, XYY, YZ, ZZ). Herein, "and / or" includes all combinations of one or more of the corresponding configurations.

The terms first, second, etc. may be used herein to describe various elements, elements, regions, layers, and / or sections, Or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and / or section from another element, element, region, layer, and / or section. Thus, a first element, element, region, layer, and / or section in one embodiment may be referred to as a second element, element, region, layer, and / or section in another embodiment.

Spatially relative terms such as "below "," above ", and the like can be used for illustrative purposes, thereby describing the relationship between one element or feature and another element (s) or feature (s) do. This is used to denote the relationship of one component to another in the drawings, but not to an absolute position. For example, if the device shown in the figures is inverted, the elements depicted as being "below" other elements or features are positioned in the "up" direction of other elements or features. Thus, in one embodiment, the term "below" may include both upward and downward directions. In addition, the device may be in another direction (e.g., rotated 90 degrees or in another direction), and such spatially relative terms used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Throughout the specification, when a component is referred to as "comprising ", it means that it can include other components as well, without departing from the other components unless specifically stated otherwise. Unless defined otherwise, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a low-voltage drop regulator, and FIG. 2 is a small-signal modeling circuit for the low-voltage drop regulator shown in FIG.

1, a low drop-out (LDO) regulator 10 regulates the input power supply voltage Vdd and outputs the regulated output to the load. The LDO regulator 10 includes a pass transistor Mp, an error amplifier 12, Part 14 and an output load capacitor C _L.

The first electrode of the pass transistor Mp is connected to the input power supply voltage Vdd so as to output the regulated input power supply voltage Vdd through the output node N2 and the second electrode of the pass transistor Mp is connected to the output node N2 . Also, the control signal CTRL is supplied to the gate electrode, and the control signal CTRL is a signal for controlling the output voltage Vout to be output based on the input power supply voltage Vdd. That is, the magnitude of the output voltage Vout is determined corresponding to the magnitude of the control signal CTRL.

At this time, the pass transistor Mp may be implemented as a P-type transistor (for example, a PMOSFET).

The feedback unit 14 generates a feedback voltage V _FD in response to the output voltage Vout and includes a plurality of resistors connected in series between the output node N2 and the ground GND R1, R2). That is, the feedback voltage V _FB is a voltage obtained by dividing the output voltage Vout by the resistors. The feedback section 14 provides the feedback voltage V _FD to the error amplifier 12.

The error amplifier 12 receives the reference voltage V _REF at the inverting input terminal (-) and receives the feedback voltage V _FD at the non-inverting input terminal (+). The error amplifier 12 receives the input reference voltage V _REF and feedback And compares the voltage (V _FB ). The error amplifier 12 outputs a comparison signal to the first node N1 connected to the gate electrode of the pass transistor Mp in response to the comparison result, (CTRL).

The comparison signal includes information on a change in the output voltage (V _OUT ) of the low voltage drop regulator (10). That is, when the output voltage V _OUT changes, the feedback voltage V _FB varies in response to this, and the error amplifier 12 generates the comparison signal in response to the changed feedback voltage V _FB . For example, if the feedback voltage V _FB is less than the reference voltage V _REF , the comparison signal of the error amplifier 12 can control the pass transistor M p to increase the value of the output voltage V _OUT have. If the feedback voltage V _FB is greater than the reference voltage V _REF , the comparison signal may control the pass transistor Mp to decrease the value of the output voltage V _OUT .

Thus, the pass transistor Mp stabilizes the output voltage V _OUT by fluctuating the output voltage V _OUT in response to the comparison signal acting as the control signal CTRL. That is, the low-voltage drop regulator 10 can maintain a stable output using feedback.

However, when noise is included in the input power supply voltage Vdd, in accordance with the signal flow in the loop formed by the pass transistor Mp, the feedback section 14 and the error amplifier 12, The signal CTRL may contain noise. In this case, the control signal CTRL may not properly control the pass transistor Mp.

2, a parasitic capacitor Cp ₁ is connected to a first node N 1 to which a gate electrode of the pass transistor Mp is connected, and a second node N 1 to which a gate electrode of the pass transistor Mp is connected is a small-signal modeling circuit for the low- Can be formed. For example, the parasitic capacitor Cp ₁ may be generated when the error amplifier 12 adjacent to the first node N 1 is laid out.

A gate-source capacitor Cgs is formed between the gate and source electrodes of the pass transistor Mp and a gate-drain capacitor Cgd is formed between the gate and drain electrodes. The small signal modeling shown in FIG. 2 includes first and second voltage-controlled current sources VCCS ₁ and VCCS ₂ , a total load resistance R _LT formed at the output stage, and a total load capacitor C _LT are shown. The entire load capacitor C _LT may include a load capacitor C _L and a second parasitic capacitor C _P2 formed at the output node N2. The second parasitic capacitor C _P2 may include a second parasitic capacitor C _P2 , For example, when laying out a load device adjacent to the output node N2. 2, the gate-drain capacitor Cgd is connected between the first node N1 and the ground GND and the voltage-controlled current sources VCCS ₁ and VCCS ₂ Is formed.

The first node voltage V _N1 generated in the first node N1 is generated by the input power supply voltage Vdd irrespective of the comparison signal output from the error amplifier 12. [ That is, when noise is included in the input power supply voltage Vdd, the input power supply voltage Vdd includes a frequency component due to the noise. In the case of the small signal model circuit of FIG. 2, The voltage V _N1 can be derived by the following equation (1).

(s: Laplace variable, R _g: equivalent resistance of the first node)

According to Equation (1), the first node voltage V _N1 varies with a magnitude different from the input power supply voltage Vdd. That is, when noise is included in the input power supply voltage Vdd, the first node voltage V _N1 is influenced by the parasitic capacitor Cp ₁ and the gate-drain capacitor Cgd to be higher than the input power supply voltage Vdd It has a small size and fluctuates.

The gate-source voltage Vgs which is a voltage value for operating the pass transistor Mp is a voltage applied to the source electrode (input power supply voltage Vdd) and a voltage applied to the gate electrode, that is, Since the difference between the first node voltage (V _N1)), when said input supply voltage (Vdd) and the first node voltage (V _N1) is changed to a different size from each other and the gate-source voltage (Vgs) it is varied.

The control signal CTRL of the pass transistor Mp is set such that the first node voltage V _N1 is equal to the input power supply voltage Vdd The control signal CTRL does not control the pass transistor Mp properly. That is, the power supply noise rejection rate (PSRR) characteristic is lowered.

The PSRR characteristic of the LDO regulator 10 is more vulnerable to the high frequency component of the input power supply voltage Vdd and therefore when the noise included in the input power supply voltage Vdd is a high frequency component, the LDO regulator 10 is unstable And can output the output voltage (V _OUT ).

Accordingly, the LDO regulator 10 shown in Fig. 1 forms a large-capacity load capacitor C _{L at the} output node N2 in order to more stably output the output voltage V _OUT . However, in order to implement the load capacitor C _L in a large capacity, a physically large area is required, which is disadvantageous in design.

The LDO regulator overcomes the above disadvantages. The LDO regulator includes a compensation circuit that can remove the influence of the parasitic capacitance generated at the gate node of the pass transistor, so that even if noise is introduced into the input voltage, It is possible to provide a low-dropout regulator that eliminates the gate-source voltage difference to improve the power supply noise rejection ratio (PSRR) characteristic.

In addition, by providing the compensation circuit, it is possible to output a stable output voltage even in a high frequency band while eliminating a large capacity load capacitor having a large area, and accordingly, it is possible to output an analog output circuit Lt; RTI ID = 0.0 > regulator < / RTI >

FIG. 3 is a circuit diagram showing a low-voltage drop regulator according to an embodiment of the present invention, and FIG. 4 is a small-signal modeling circuit for the low-voltage drop regulator shown in FIG.

Referring to FIG. 3, the LDO regulator 20 according to the embodiment of the present invention includes a first node N1 to which the gate electrode of the pass transistor Mp is connected, as compared with the LDO regulator 10 shown in FIG. 1, And the load capacitor C _L formed in the output node N2 is removed, and the other structures are substantially the same. Therefore, the same reference numerals are used for the same elements as in the embodiment of FIG. 1, and a detailed description thereof will be omitted. In the case of FIG. 4, the same reference numerals are used for the same constituent elements shown in FIG. 2, and a detailed description thereof will be omitted.

The compensation circuit 200 is a circuit for generating a negative capacitance, which means that the equivalent capacitance Ceg for the compensation circuit 200 at the first node N1 has a negative value.

That is, equivalent to the capacitor (Ceq) of the compensation circuit 200, as shown in Figure 4 is to have the capacitance of the sound, which is parasitic in the first node (N1), the capacitance (Cp ₁₎ and a pass transistor (Mp the sum of the capacitance (Cgd) between the drain electrode, - the gate of) can be implemented in a (Cp ₁ + Cgd).

Therefore, when also compared to the circuit shown in Figure 2 above, the equivalent capacitor (Ceq) having a capacitance of the negative is the first node (N1) Parasitic capacitors (Cp ₁₎ and a pass transistor (Mp) at the gate-drain electrodes Is connected in parallel with the capacitor Cgd.

Here, the first node voltage V _N1 'of the first node _N1 is generated by the input voltage Vdd irrespective of the comparison signal output from the error amplifier 12.

That is, when noise is included in the input power supply voltage Vdd, the input power supply voltage Vdd includes a frequency component due to the noise. In the case of the small signal model circuit of FIG. 4, The voltage V _N1 'can be derived by the following equation (2).

According to the above equation, the first node voltage V _N1 'varies with the same magnitude as the input voltage Vdd. That is, even if the input power supply voltage Vdd fluctuates due to noise, the first node voltage V _N1 'is supplied to the parasitic capacitor Cp ₁ and the gate-drain capacitor Cp by an equivalent capacitor Ceq having a negative capacitance value. The influence of the input power supply voltage (Vgd) is removed, thereby changing the input power supply voltage (Vdd).

The gate-source voltage Vgs which is a voltage value for operating the pass transistor Mp is a difference between the voltage Vdd input to the source electrode and the first node voltage V _N1 'applied to the gate electrode, The gate-source voltage Vgs is constant if the voltage Vdd and the first node voltage V _N1 'are equally varied.

In this case, the control signal CTRL of the pass transistor Mp controls the first node voltage V _N1 'to be equal to the input power supply voltage Vdd when the comparison signal output from the error amplifier 12 is output with a constant voltage value. The control signal CTRL can appropriately control the pass transistor Mp. That is, the power supply noise rejection ratio (PSRR) characteristic is improved.

That is, according to the LDO regulator 20 according to the embodiment of the present invention, even when the noise included in the input power supply voltage Vdd is a high frequency component, it is possible to output a stable output voltage V _OUT .

Accordingly, unlike the LDO regulator 10 shown in FIG. 1, the LDO regulator 20 shown in FIG. 3 does not need to further form a large-capacity load capacitor C _{L at the} output node N2.

However, the output node (N2) may be the second may be formed of a parasitic capacitor (Cp _2), it plays a role of this second parasitic capacitor (Cp ₂₎ is the total load capacitor (C _LT). For example, the second parasitic capacitor Cp ₂ may be generated when laying out a load device (e.g., an analog circuit in the DDI) adjacent to the output node N2.

5 is a circuit diagram of a low-dropout regulator including one embodiment of the compensation circuit shown in FIG.

Referring to FIG. 5, the compensation circuit 200 includes a non-inverting amplifier 210, a source follower 220, and a compensation capacitor 230, C _M.

The non-inverting amplifier 210 includes an operational amplifier 212, a first resistor Rf1 and a second resistor Rf2 connected in series between the output terminal of the operational amplifier 212 and the ground. The control signal CTRL or the signal corresponding to the comparison signal of the error amplifier 12 is input to the noninverting input terminal of the OP amplifier 212 and the inverting input terminal of the operational amplifier 212 is connected to the non- Is fed back. That is, a signal applied to the inverting input terminal is a voltage divided by the first resistor Rf1 and the second resistor Rf2, the output voltage of the OP amplifier 212. [ Gain (Gain, _CL A) of the non-inverting amplifier 210 having the above structure is calculated as 1 + Rf1 / Rf2.

Although the comparison signal of the error amplifier 12 may be directly input to the non-inverting input terminal (+) of the OP amplifier 212, the voltage level of the comparison signal may be slightly higher than the input signal of the operational amplifier 212 Level.

The compensation circuit 200 may include a source follower unit 220 for converting a comparison signal of the error amplifier 12 into a low level voltage.

The source follower 220 has a first electrode connected to the input power supply voltage Vdd, a second electrode connected to the current sink 222, and a comparison signal output from the error amplifier 12 as a gate electrode And an N-type transistor Ms (for example, an NMOSFET, for example) applied thereto.

The voltage applied to the non-inverting input terminal (+) of the operational amplifier 212 in the source follower 220 is a voltage having a value obtained by subtracting the threshold voltage of the transistor Ms from the comparison signal of the error amplifier 12 . Further, a current path is formed from the input power supply voltage Vdd to the ground (GND) through the current sink portion 222 so that the transistor Ms operates as a source follower.

The compensation capacitors 230, C _M are connected in parallel to the non-inverting amplifier 210. That is, the first electrode of the compensation capacitor 230, C _M may be coupled to the output of the non-inverting amplifier 210 and the second electrode may be coupled to the non-inverting input of the non-inverting amplifier 210.

However, when the source follower unit 220 is included, the second electrode of the compensation capacitor 230, C _M may be connected to the gate electrode of the transistor Ms.

In addition, when the compensation capacitors 230 and C _M are connected in parallel to the non-inverting amplifier 210 as shown in the figure, the equivalent capacitances on the side of the compensation circuit 220 viewed by the Miller effect (Ceg), that is, the equivalent capacitance Ceg for the compensation circuit 200 at the first node N1 is derived by the following equation (3).

(Provided that Rf1 = Rf2)

Although the equivalent capacitance Ceq of the compensation circuit 200 includes the compensation capacitor C _M having a small area, the first resistor Rf1 and the second resistor Rf2 included in the non- At least one is implemented as a variable resistor, and the value of these resistors is changed to adjust the ratio (Rf1: Rf2) of the first and second resistances, thereby generating a negative capacitance having a desired magnitude.

That is, the capacity of the capacitor Cgd between the gate-drain electrode of the parasitic capacitor Cp ₁ and the pass transistor Mp in the first node N1, which is a capacitor to be compensated, (Cp ₁ + Cgd), which can compensate (remove) the capacitance by adjusting the ratio (Rf 1: Rf 2) of the first and second resistors so as to have a size corresponding to the negative capacitance Can be generated.

Accordingly, even if noise is introduced into the input voltage, the voltage difference between the gate and the source of the pass transistor can be removed to improve the PSRR characteristic of the power supply, and the large- The load capacitor can be removed and a stable output voltage can be formed even in a high frequency band.

However, in the case of the embodiment of the present invention, the operation of the compensation circuit 200 must maintain a higher operating speed than the error amplifier 12 of the LDO regulator 20. Therefore, the operational amplifier 212 of the non-inverting amplifier 210 has a wider operating bandwidth than the error amplifier 12. [

6 is a graph showing the PSRR characteristics of the low-voltage dropout regulator according to the embodiment of the present invention.

6, line A shows the PSRR characteristic of the LDO regulator 10 shown in Fig. 1, and line B shows the PSRR characteristic of the LDO regulator 20 having the compensation circuit 200 shown in Fig. 3 .

The horizontal axis (freq (Hz)) of the graph shown in FIG. 6 represents the frequency component value of the input power supply voltage Vdd applied to the LDO regulator and the vertical axis V (dB) represents the supply power noise removal rate PSRR). The closer the PSRR value is to 0, the less the PSRR characteristic of the LDO regulator is.

6, since the PSRR characteristic of the LDO regulator for the frequency band of 100 KHz or less of the input power supply voltage (Vdd) is determined based on the loop gain characteristic of the LDO regulator, the LDO regulators 10, A and LDO regulators 20 and B are all good.

On the other hand, the PSRR characteristic of the LDO regulator for the high frequency band of 1 MHz or more of the input power supply voltage (Vdd) can be influenced by the parasitic capacitance of the pass transistor or the like. In addition, the PSRR characteristic of the LDO regulator is more vulnerable to the high frequency component of the input voltage. In this case, the input power supply voltage Vdd may include noise having a high frequency component.

That is, as shown in FIG. 6, the PSRR characteristic of the voltage regulator for the high frequency band of 1 MHz or more of the input voltage in the case of the LDO regulator 10, A is worse than that for the frequency band of 100 KHz or less of the input voltage.

However, in the case of the LDO regulator 10, A provided with the compensation circuit 200, it can be seen that the PSRR characteristic is improved even in a high frequency band of 1 MHz or more as shown in FIG.

6, the LDO regulator 10, B provided with the compensation circuit 200 has a gain of about 30 dB in a range of 1 MHz to 10 MHz, which is a high frequency band, in comparison with the LDO regulators 10, PSRR improvement effect can be confirmed.

FIG. 7 is a block diagram of a display apparatus according to an embodiment of the present invention, and FIG. 8 is a block diagram showing the configuration of the voltage generator shown in FIG.

Although all of the embodiments of the present invention have been described with respect to a liquid crystal display (LCD) in the illustrated embodiment, all of the embodiments of the present invention can be applied to all of flat panel displays such as a plasma display device (PDP), an organic light emitting display And is applicable to a display device.

7 and 8, a display device 100 according to an embodiment of the present invention includes a display panel 110, a controller 120, a voltage generator 130, a gate driver 140, and a source driver 150).

The voltage generating unit 130 includes a DC-DC converter 30 and an LDO regulator 20. The LDO regulator 20 has the same configuration as the LDO regulator 20 shown in FIG. Therefore, detailed description of the configuration and operation of the LDO regulator 20 will be omitted.

The display panel 110 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. Specifically, the plurality of gate lines GL1 to GLn extend in a first direction D1 and are arranged in a second direction D2 orthogonal to the first direction D1. The plurality of data lines DL1 to DLm extend in the second direction D2 and are arranged in the first direction D1. The plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn are provided on different layers and are electrically insulated from each other.

A plurality of pixel regions are defined by the gate lines GL1 to GLn and the data lines DL1 to DLm. A plurality of pixels PX are arranged in the pixel regions.

The controller 120 receives input image data I_DAT and an image control signal I_CS from an external video board (not shown). The input image data I_DAT may be defined as an image data signal input from the outside of the display device 100 to the display device 100.

The controller 120 converts the input image data I_DAT according to the specifications of the source driver 150. The converted image data I_DAT 'generated by the controller 120 through the conversion operation is provided to the source driver 150.

The controller 120 generates a gate control signal GCS and a data control signal DCS in response to the image control signal I_CS. The gate control signal GCS is a signal for driving the gate driver 140 and the data control signal DCS is a signal for driving the source driver 150.

The gate driver 140 generates a gate signal in response to the gate control signal GCS and sequentially outputs the gate signal to the gate lines GL1 to GLn.

The source driver 150 receives the converted image data I_DAT 'and the data control signal DCS from the controller 120 and outputs the converted image data I_DAT' in response to the data control signal DCS. Into a data voltage and outputs the data voltage to the display panel 110.

The gate driver 140, the source driver 150 and / or the controller 120 may be directly mounted on a lower substrate of the display panel 110 in the form of a single integrated circuit chip (e.g., a display driver IC, DDI) have.

The voltage generating unit 130 receives the input voltage Vin and converts the input voltage Vin into an analog voltage to be supplied to the gate driver 140 and / or the source driver 150, which are analog circuits included in the DDI Output. Also, the voltage generating unit 130 may be mounted together with the analog circuit in the DDI.

7, the signal output from the voltage generator 130 is an analog driving voltage AVDD that is supplied to the source driver 150 and can be used as a reference voltage for generating a gray scale voltage. However, In one embodiment, the signal output from the voltage generator 130 is not limited thereto.

8, the voltage generating unit 130 includes a DC-DC converter 30 and an LDO regulator 20. The LDO regulator 20 is the same as the LDO regulator 20 shown in FIG. (200 in Fig. 3) for generating a negative capacitance with the configuration.

The DC-DC converter 30 may be provided with an input voltage Vin and a switching signal SW. The switching signal SW is a signal for controlling the adjustment voltage Vreg to be output based on the input voltage Vin. The DC-DC converter 30 may output the adjustment voltage Vreg according to the switching signal SW. The DC-DC converter 30 can convert the input voltage Vin whose value greatly fluctuates to the adjustment voltage Vreg having a relatively stable value. However, since the DC-DC converter 30 operates in accordance with the switching signal SW, the regulated voltage Vreg may include noise due to switching.

The LDO regulator 20 may serve as a sub-regulator for the DC-DC converter 30. [ The LDO regulator 20 according to the embodiment of the present invention receives the adjustment voltage Vreg as the input power supply voltage Vdd and controls the adjustment voltage Vdd through the negative capacitance generated by the compensation circuit 200, Vreg) can be removed and a stable output voltage (V _OUT ) can be output.

In particular, since the noise due to the switching may be a noise of a high frequency component, the adjustment voltage Vreg applied to the input power supply voltage Vdd of the LDO regulator 20 may include noise of a high frequency component.

3 and 5, the LDO regulator 20 according to the embodiment of the present invention includes the parasitic capacitance Cp generated in the gate node N1 of the pass transistor Mp and the gate- (PSRR) characteristic by removing the gate-source voltage difference of the pass transistor by providing the compensation circuit 200 capable of removing the influence of the drain capacitance Cgd, Circuit 200, it is possible to output a stable output voltage even in a high-frequency band while eliminating a large-capacity load capacitor having a large area.

Therefore, the display apparatus 100 according to the embodiment of the present invention removes a large capacity load capacitor to the analog circuits of the DDI (Display Driver IC) necessary for the display driving through the LDO regulator 20, To provide a stable voltage.

As described above, the present invention has been described with reference to particular embodiments, such as specific constituent elements, and limited embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

10, 20: LDO regulator 12: error amplifier
14: Feedback section 30: DC-DC converter
130: voltage generator 200: compensation circuit
212: non-inverting amplifier 220: source follower
230: compensation capacitor

Claims (10)

A pass transistor for regulating an input voltage according to a control signal; And
And a compensation circuit for providing a negative capacitance to the gate node of the pass transistor,
Wherein the control signal is formed based on a feedback signal, a reference input signal, and the negative capacitance associated with the output voltage of the pass transistor. A pass transistor that regulates an input power supply voltage according to a control signal and outputs the regulated output voltage;
A feedback unit for generating a feedback voltage in response to the output voltage;
An error amplifier receiving the reference voltage and the feedback voltage and outputting a comparison signal; And
And a compensation circuit for generating a negative capacitance at a first node to which a gate electrode of the pass transistor is connected. 3. The method of claim 2,
Wherein a magnitude of the negative capacitance is substantially equal to a magnitude of a parasitic capacitance at the first node and a sum of capacitances between gate and drain electrodes of the pass transistor. 3. The method of claim 2,
Wherein the compensation circuit comprises:
A non-inverting amplifier composed of an operational amplifier, a first resistor and a second resistor connected between the output terminal of the operational amplifier and ground,
And a compensation capacitor coupled to the non-inverting amplifier. 5. The method of claim 4,
Wherein the operational amplifier has a wider operational bandwidth than the error amplifier. 6. The method of claim 5,
A signal corresponding to the control signal is input to the non-inverting input terminal (+) of the operational amplifier, and an inverting input terminal (-) is connected to the output voltage of the operational amplifier Is input to the LDO regulator. 5. The method of claim 4,
Wherein the compensation circuit further comprises a source follower connected to an input of the non-inverting amplifier. 8. The method of claim 7,
Wherein the source follower includes a transistor having a first electrode coupled to the input power supply voltage, a second electrode coupled to the current sink, and a control signal applied to the gate electrode. 9. The method of claim 8,
And the transistor included in the source follower unit is a transistor of a type different from that of the pass transistor. A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels;
A gate driver for outputting a gate signal to the gate lines;
A source driver for outputting a data voltage to the data lines,
And a voltage generator for receiving an input voltage, converting the analog voltage into an analog voltage, and outputting the analog voltage to the gate driver and / or the source driver,
Wherein the voltage generator comprises a DC-DC converter and an LDO regulator,
And the LDO regulator includes a compensation circuit that generates a negative capacitance.

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