CN104821121B - Remote circuit design hardware experiment and method based on LAN and FPGA - Google Patents
Remote circuit design hardware experiment and method based on LAN and FPGA Download PDFInfo
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- CN104821121B CN104821121B CN201510187659.7A CN201510187659A CN104821121B CN 104821121 B CN104821121 B CN 104821121B CN 201510187659 A CN201510187659 A CN 201510187659A CN 104821121 B CN104821121 B CN 104821121B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
- G09B23/00—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
- G09B23/06—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics
- G09B23/18—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism
- G09B23/183—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits
- G09B23/186—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits for digital electronics; for computers, e.g. microprocessors
Abstract
The invention discloses a kind of remote circuit design hardware experiment and method based on LAN and FPGA, experimental system includes server end, client PC and hardware experiment platform, it is connected between three parts by LAN and is communicated, being also connected between server and hardware experiment platform by USB JTAG downloading wires is communicated；Experimental method is that system components are connected, user is tested and the end that uploads onto the server by client PC, server end downloads to related data in hardware experiment platform, and hardware experiment platform constantly collects related data and is sent to client rs PC machine and carries out showing for reference.Of the invention and existing software emulation experiment is compared with hardware experiments, and the running situation of true reflection hardware circuit supports the tele-experimentation under network；In the ARM cores that hardware platform monitoring programme and network monitoring and data acquisition program are operated in same chip, the burden of server is alleviated；User can do the contrived experiment of various digital circuits on this system.
Description
Technical field
The present invention relates to computer-experiment instrument, especially a kind of remote circuit design hardware based on LAN and FPGA
Experimental system and method.
Background technology
The teaching and experiment method and system of existing computer hardware are roughly divided into two major classes：One class is imitative based on computer
The pure software simulated experimental environments of true technology；Another kind of is the experimental ring for being completed on local laboratory real hardware platform experiment
Border.
The former is not related to real hardware experiments equipment, and all experiment contents are all focused on server, pass through network
Issue, user can carry out related experiment and acquisition by a computer that can connect internet to supporting simulation software
Experimental result；The latter carries out related experiment local, it usually needs user and real hardware device are attached and interacted,
User can really experience the effect of practical operation, but need to put into substantial amounts of experimental facilities and carry out the dimension of correlation
Shield.
The void of both the above method one one is real, but the former has lacked the confidence level and verifiability of actual hardware operation, and not
It is that all situations can real simulation；The latter needs to put into substantial amounts of human and material resources and financial resources carry out renewal and the dimension of equipment
Shield, in the case where a large amount of personnel concentrate and tested, experimental facilities is difficult to be guaranteed, while experimenter can only be defined
Time and defined place are tested, the need for less meeting current open experiment.With large-scale open network course
MOOC is in the popularization in the whole world, the problem of being badly in need of solving to carry out hardware experiments under network opening environment.
The content of the invention
Goal of the invention：The problem of present invention is solves to carry out hardware experiments under network opening environment, proposes that one kind is based on
LAN and FPGA remote circuit design hardware experiment and method.
Technical scheme：A kind of remote circuit design hardware system based on LAN and FPGA of the present invention, including
Between server end, client PC and hardware experiment platform, three parts by LAN be connected communicated, server and
Also it is connected between hardware experiment platform by USB-JTAG downloading wires and is communicated.
Hardware experiment platform, which is used, collects ZedBoard plates of the double-core ARM Cortex-A9 and FPGA in a master chip
Card, the master chip uses Xilinx Zynq-7000 All Programmable SoC, possesses double-core ARM inside it
The PS that CortexA9 processors are constituted（Processing System, processing system）Part and the PL of fpga logic
（Programmable Logic, FPGA）Part.
Server end includes automatic download module and Bitstream（Bit element flow）Update module；Bitstream update modules
Server end, the Bitstream files that automatic identification user submits are operated in, and is preserved and is updated；Automatic download module
Server end is operated in, Bitstream files are automatically downloaded in hardware experiment platform.
Client PC includes FTP uploading modules and client emulation module；Client emulation module operates in client
On PC, carry out local virtual hardware debugging, complete the experiment of user hardware design Straight simulation simulation and with long-range hardware
Experiment porch carries out communication interaction；FTP uploading modules are operated in client rs PC, by LAN, access the FTP of server end
Service, and the Bitstream files that user designs are uploaded onto the server.
Hardware experiment platform includes FPGA portion and ARM parts, and FPGA portion includes FPGA circuitry and monitors IP kernel, ARM portions
Dividing includes feedback interactive module and network monitoring and data acquisition module；FPGA circuitry monitoring IP kernel operates in ZedBoard boards
PL parts in there is provided the IP kernel interface unified to user, complete the hardware circuit of user's design to being run in fpga chip
Monitoring, and and operate in hardware platform monitoring programme in ARM parts and carry out data exchange；Network monitoring and data acquisition module
Block is operated in the PS parts of ZedBoard boards, is responsible for the real-time and validity of network data transmission；Feed back interactive module
In the PS parts for operating in ZedBoard boards, the data control bag of user is received, and parses and is transferred to FPGA, while can be by
The live signal encapsulation of FPGA circuitry monitoring collection, by network-feedback to user.
The method tested using said system, is comprised the following steps：
（1）Server end, hardware experiment platform are connected with client PC by LAN, by server end and hardware
Experiment porch is also connected by USB-JTAG downloading wires；
（2）Server end designs design FPGA in automatic download module and Bitstream update modules, hardware experiment platform
In circuit supervision core, feedback interactive module and network monitoring and data acquisition module, client PC design FTP uploading modules and
Client emulation module, and the experiment software with custom feature is installed；
（3）User carries out digital circuit experiment on client PC using FPGA design software, designs the circuit of generation
Uploaded onto the server end by FTP uploading modules with Bitstream document forms, server end Bitstream update modules are detectd
After hearing that new data flow arrives, receive data and start the Bitstream texts that automatic download module downloads user's design automatically
Part is into the FPGA portion of hardware experiment platform；
（4）FPGA circuitry monitoring IP kernel and network monitoring in hardware experiment platform are engaged with data acquisition module, no
It is disconnected to collect the executory relevant data of subscriber's line circuit, and these data are adopted by feeding back interactive module and network monitoring with data
The client emulation module progress visualization that collection module is sent to client PC shows that user passes through the software on client PC
The change of experimental result is obtained in real time.
Wherein：Described hardware experiment platform, which is used, collects double-core ARM Cortex-A9 and FPGA in a master chip
ZedBoard boards, the master chip uses Xilinx Zynq-7000 All Programmable SoC, possesses double inside it
PS parts and the PL parts of fpga logic that core ARM CortexA9 processors are constituted.
In step（3）In, described automatic download module operates in server end, and Bitstream files are downloaded automatically
Into hardware experiment platform, the listening port process of server end in running background, the process be responsible for intercepting FTP service to
The Bitstream files that family is uploaded update this event, and are responsible for starting Xilinx microprocessor debugging XMD instruments, XMD works
Tool identification download interface, and start programming of the download service completion to hardware experiment platform.
Beneficial effect：Compared with prior art, its significant effect is the present invention：（1）Possesses real hardware bottom layer branch
Hold, the running situation of true reflection hardware circuit supports the tele-experimentation under network, expanded region and the opening of experiment
Property；（2）The advantage of hardware experiment platform is made full use of to operate in the hardware circuit that FPGA circuitry monitors IP kernel and user's design
In the FPGA of same chip, hardware platform monitoring programme and network monitoring and data acquisition program are operated in into same chip
ARM cores in, significantly reduce the burden of server；（3）User can do the contrived experiment of various digital circuits on this system,
Including logical combination, sequential logic and more complicated CPU design etc..
Brief description of the drawings
Fig. 1 is the overall system structure schematic diagram of the present invention；
Fig. 2 is the functional block diagram of the present invention.
Embodiment
As shown in figure 1, a kind of remote circuit design hardware system based on LAN and FPGA of the present invention, including
Between server end, client PC and hardware experiment platform, three parts by LAN be connected communicated, server and
Also communicated between hardware experiment platform by being connected between USB-JTAG downloading wires；Hardware experiment platform is using collection double-core
ZedBoard boards of the ARM Cortex-A9 and FPGA in a master chip, the master chip uses Xilinx Zynq-
7000 All Programmable SoC, possess PS parts and the FPGA of double-core ARM CortexA9 processors composition inside it
The PL parts of logic.
As shown in Fig. 2 server end includes automatic download module and Bitstream update modules；Bitstream updates mould
Block operates in server end, the Bitstream files that automatic identification user submits, and is preserved and updated；It is automatic to download mould
Block operates in server end, and Bitstream files are automatically downloaded in hardware experiment platform, server end in running background
Listening port process, the process is responsible for intercepting FTP service updates this event to the Bitstream files that user uploads, and
It is responsible for starting Xilinx microprocessor debugging XMD instruments, XMD instruments identification download interface, and starts download service completion pair
The programming of hardware experiment platform.
Client PC includes FTP uploading modules and client emulation module；Client emulation module operates in client
On PC, carry out local virtual hardware debugging, complete the experiment of user hardware design Straight simulation simulation and with long-range hardware
Experiment porch carries out communication interaction；FTP uploading modules are operated in client rs PC, by LAN, access the FTP of server end
Service, and the Bitstream files that user designs are uploaded onto the server.
Hardware experiment platform includes FPGA portion and ARM parts, and FPGA portion includes FPGA circuitry and monitors IP kernel, ARM portions
Dividing includes feedback interactive module and network monitoring and data acquisition module；FPGA circuitry monitoring IP kernel operates in ZedBoard boards
PL parts in there is provided the IP kernel interface unified to user, complete the hardware circuit of user's design to being run in fpga chip
Monitoring, and and operate in hardware platform monitoring programme in ARM parts and carry out data exchange；Network monitoring and data acquisition module
Block is operated in the PS parts of ZedBoard boards, is responsible for the real-time and validity of network data transmission；Feed back interactive module
In the PS parts for operating in ZedBoard boards, the data control bag of user is received, and parses and is transferred to FPGA, while can be by
The live signal encapsulation of FPGA circuitry monitoring collection, by network-feedback to user.
The method tested using said system, is comprised the following steps：
（1）Server end, hardware experiment platform are connected with client PC by LAN, by server end and hardware
Experiment porch is also connected by USB-JTAG downloading wires；
（2）Server end designs design FPGA in automatic download module and Bitstream update modules, hardware experiment platform
In circuit supervision core, feedback interactive module and network monitoring and data acquisition module, client PC design FTP uploading modules and
Client emulation module, and the experiment software with custom feature is installed；
（3）User carries out digital circuit experiment on client PC using FPGA design software, designs the circuit of generation
Uploaded onto the server end by FTP uploading modules with Bitstream document forms, server end Bitstream update modules are detectd
After hearing that new data flow arrives, receive data and start the Bitstream texts that automatic download module downloads user's design automatically
Part is into the FPGA portion of hardware experiment platform；
（4）FPGA circuitry monitoring IP kernel in hardware experiment platform is engaged with network monitoring with data acquisition module, no
It is disconnected to collect the executory relevant data of subscriber's line circuit, and these data are adopted by feeding back interactive module and network monitoring with data
The client emulation module progress visualization that collection module is sent to client PC shows that user can be by client PC
Software obtains the change of experimental result in real time.
User on client PC using FPGA design software carry out digital circuit experiment, design generation circuit with
Bitstream document forms are uploaded onto the server end, and server end, which is listened to, automatic after new data flow arrives to be downloaded user and set
The Bitstream files of meter are into hardware experiment platform, and on the one hand hardware experiment platform monitors the operation of the circuit of user's design,
On the other hand interacted by the Ethernet network interface access to LAN of its own and the software on client PC, user can be with
Obtain the change of experimental result in real time by the software on client PC.
User carries out digital circuit experiment, design generation Bitstream on client PC using FPGA design software
File, this document is uploaded onto the server by FTP uploading modules, and server end Bitstream update modules listen to new number
According to after flowing to and, receiving data, and start Bitstream file downloads that automatic download module designs user to hardware experiments
The FPGA portion of platform；FPGA circuitry monitoring IP kernel in hardware experiment platform matches with network monitoring with data acquisition module
Close, constantly collect the executory relevant data of subscriber's line circuit, and by these data by feed back interactive module and network monitoring with
The client emulation module progress visualization that data acquisition module is sent to client PC is shown.
The control command that user is inputted by interface is packaged into after data by client emulation module, uploads to hardware experiments
The network monitoring of platform and data acquisition module part, further, monitor IP kernel by feeding back interactive module and FPGA circuitry, make
The execution of subscriber's line circuit is directly controlled for control signal.
Although the present invention is illustrated and described with regard to preferred embodiment, it is understood by those skilled in the art that
Without departing from scope defined by the claims of the present invention, variations and modifications can be carried out to the present invention.
Claims (5)
1. it is a kind of based on LAN and FPGA remote circuit design hardware system, including server end, client PC and
It is connected between hardware experiment platform, three parts by LAN and is communicated, is also passed through between server and hardware experiment platform
USB-JTAG downloading wires, which are connected, to be communicated；Described hardware experiment platform using collect double-core ARM Cortex-A9 and FPGA in
ZedBoard boards in one master chip, described master chip uses Xilinx Zynq-7000All Programmable
SoC, possesses the PS parts and the PL parts of fpga logic of double-core ARM CortexA9 processors composition inside it；Described service
Device end includes automatic download module and Bitstream update modules；Described Bitstream update modules operate in server
End, the Bitstream files that automatic identification user submits, and preserved and updated；Described automatic download module is operated in
Server end, Bitstream files are automatically downloaded in hardware experiment platform；Described client PC is uploaded including FTP
Module and client emulation module；Client emulation module is operated on client PC, carries out local virtual hardware debugging, complete
Simulated into the Straight simulation that user's hardware design is tested and carry out communication interaction with long-range hardware experiment platform；FTP uploads mould
Block is operated in client rs PC, by LAN, accesses the FTP service of server end, and the Bitstream texts that user is designed
Part uploads onto the server.
2. the remote circuit based on LAN and FPGA designs hardware system as claimed in claim 1, it is characterised in that described
Hardware experiment platform include FPGA portion and ARM parts, FPGA portion includes FPGA circuitry and monitors IP kernel, and ARM parts include
Feed back interactive module and network monitoring and data acquisition module；FPGA circuitry monitoring IP kernel operates in the PL portions of ZedBoard boards
There is provided the IP kernel interface unified to user in point, the monitoring of the hardware circuit of user's design to being run in fpga chip is completed,
And carry out data exchange with the hardware platform monitoring programme operated in AR M parts；Network monitoring is run with data acquisition module
In the PS parts of ZedBoard boards, it is responsible for the real-time and validity of network data transmission；Feedback interactive module is operated in
In the PS parts of ZedBoard boards, the data control bag of user is received, and parsing is transferred to FPGA, while can be by FPGA electricity
The live signal encapsulation of road monitoring collection, by network-feedback to user.
3. a kind of remote circuit design hardware experiments method based on LAN and FPGA, comprises the following steps：
(1) server end, hardware experiment platform are connected with client PC by LAN, by server end and hardware experiments
Platform is also connected by USB-JTAG downloading wires；
(2) server end designs design FPGA circuitry in automatic download module and Bitstream update modules, hardware experiment platform
Monitor design FTP uploading modules and client in core, feedback interactive module and network monitoring and data acquisition module, client PC
Emulation module is held, and the experiment software with custom feature is installed；
(3) user on client PC using FPGA design software carry out digital circuit experiment, design generation circuit with
Bitstream document forms are uploaded onto the server end by FTP uploading modules, and server end Bitstream update modules are intercepted
After being arrived to new data flow, receive data and start the Bitstream files that automatic download module downloads user's design automatically
Into the FPGA portion of hardware experiment platform；
(4) FPGA circuitry monitoring IP kernel and network monitoring in hardware experiment platform is engaged with data acquisition module, is constantly received
Collect the executory relevant data of subscriber's line circuit, and by these data by feeding back interactive module and network monitoring and data acquisition module
The client emulation module progress visualization that block is sent to client PC shows that user is real-time by the software on client PC
Obtain the change of experimental result.
4. method as claimed in claim 3, it is characterised in that described hardware experiment platform is using collection double-core ARM
ZedBoard boards of the Cortex-A9 and FPGA in a master chip, described master chip uses Xilinx Zynq-
7000All Programmable SoC, the PS parts and FPGA that double-core ARM CortexA9 processors composition is possessed inside it is patrolled
The PL parts collected.
5. method as claimed in claim 3, it is characterised in that automatic download module operates in server end in step (3), will
Bitstream files are automatically downloaded in hardware experiment platform, the listening port process of server end in running background, this enters
Journey is responsible for intercepting FTP service and this event is updated to the Bitstream files that user uploads, and is responsible for starting Xilinx micro- place
Device debugging XMD instruments, XMD instruments identification download interface are managed, and starts programming of the download service completion to hardware experiment platform.
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Families Citing this family (7)
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| CN105070127A (en) * | 2015-08-11 | 2015-11-18 | 武汉美 | Interactive practical teaching system and method |
| CN105550119B (en) * | 2016-01-29 | 2018-06-19 | 中国人民解放军国防科学技术大学 | A kind of simulator based on JTAG protocol |
| CN106412013B (en) * | 2016-08-30 | 2023-06-23 | 上海新华控制技术集团科技有限公司 | Linux-based photovoltaic grid-connected Web monitoring system |
| CN106448321A (en) * | 2016-10-31 | 2017-02-22 | 河南理工大学 | Method for realizing remote experiment and single-chip remote experiment system thereof |
| CN112055045A (en) * | 2020-07-22 | 2020-12-08 | 北京杰创永恒科技有限公司 | Network virtual laboratory system based on remote control |
| CN112380800B (en) * | 2020-12-03 | 2024-03-29 | 中国科学技术大学 | Online FPGA (field programmable gate array) experimental platform for automatic evaluation and related method |
| CN113744606A (en) * | 2021-08-11 | 2021-12-03 | 南通大学 | Embedded artificial intelligence experiment platform |
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