CN104821121A - LAN-and-FPGA-based remote circuit design hardware experimental system and method - Google Patents
LAN-and-FPGA-based remote circuit design hardware experimental system and method Download PDFInfo
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Abstract
The invention discloses a LAN-and-FPGA-based remote circuit design hardware experimental system and method. The experimental system includes a server side, a client side PC and a hardware experimental platform, the three parts are connected through a LAN for communication, the server and the hardware experimental platform are also connected through a USB-JTAG download line for communication; and the experimental method is that all parts of a system are connected, a user conducts an experiment through the client side PC and uploads to the server side, the server side downloads related data to the hardware experimental platform, and the hardware experimental platform constantly collects the related data and sends to the client side PC to be displayed for reference by the user. Compared with an existing software simulation experiment and hardware experiment, the LAN-and-FPGA-based remote circuit design hardware experimental system and method truly reflect the operation condition of a hardware circuit, and support a remote experiment under a network; a hardware platform monitoring program and a network monitoring and data acquisition programs run in an ARM core of the same chip, thereby reducing the load of the server; and the user can conduct designing experiments of various digital circuits on the system.
Description
Technical field
The present invention relates to computer-experiment instrument, especially a kind of remote circuit based on LAN (Local Area Network) and FPGA designs hardware experiment and method.
Background technology
The teaching and experiment method of existing computer hardware and system are roughly divided into two large classes: a class is the pure software simulated experimental environments based on computer simulation technique; Another kind of is the experimental situation completing experiment on the real hardware platform of local laboratory.
The former does not relate to real hardware experiments equipment, and all experiment contents all focus on server, and by Web Publishing, user can the computer of connecting Internet and the supporting simulation software experiment that can carry out being correlated with obtain experimental result by one; The latter carries out the experiment of being correlated with in this locality, usually need user and real hardware device to carry out being connected and mutual, and user can experience the effect of practical operation really, but needing to drop into a large amount of experimental facilitiess goes forward side by side the maintenance of line correlation.
Above two kinds of methods one empty one are real, but the former has lacked confidence level and the verifiability of actual hardware operation, and not all situation can real simulation; The latter needs a large amount of human and material resources of input and financial resources to carry out renewal and the maintenance of equipment, when a large amount of personnel concentrate test, experimental facilities is difficult to be guaranteed, experimenter can only test in the place of official hour and regulation simultaneously, not too meets the needs of current open experiment.Along with the popularization of large-scale open network course MOOC in the whole world, be badly in need of solving the problem of carrying out hardware experiments under network opening environment.
Summary of the invention
Goal of the invention: the present invention solves the problem of carrying out hardware experiments under network opening environment, proposes a kind of remote circuit based on LAN (Local Area Network) and FPGA and designs hardware experiment and method.
Technical scheme: a kind of remote circuit based on LAN (Local Area Network) and FPGA of the present invention designs hardware system, comprise server end, client PC and hardware experiment platform, be connected by LAN (Local Area Network) between three parts and communicate, being also connected by USB-JTAG downloading wire between server and hardware experiment platform is communicated.
Hardware experiment platform adopts and collects the ZedBoard board of double-core ARM Cortex-A9 and FPGA in a master chip, described master chip adopts Xilinx Zynq-7000 All Programmable SoC, its inside has the PS(Processing System that double-core ARM CortexA9 processor is formed, disposal system) part and the PL(Programmable Logic of fpga logic, FPGA (Field Programmable Gate Array)) part.
Server end comprises automatic download module and Bitstream
(bit element flow) update module; Bitstream update module operates in server end, automatically identifies the Bitstream file that user submits to, and carries out preserving and upgrading; Automatic download module operates in server end, is automatically downloaded in hardware experiment platform by Bitstream file.
Client PC comprises transmission module and client emulation module on FTP; Client emulation module operates on client PC, carries out local virtual hardware debug, and the Straight simulation of completing user hardware design experiment is simulated and carries out communication interaction with long-range hardware experiment platform; The upper transmission module of FTP operates in client rs PC, by LAN (Local Area Network), and the FTP service of access services device end, and Bitstream files passe user designed is to server.
Hardware experiment platform comprises FPGA part and ARM part, and FPGA part comprises FPGA circuit supervision IP kernel, and ARM part comprises feedback interactive module and network monitoring and data acquisition module; FPGA circuit supervision IP kernel operates in the PL part of ZedBoard board, be supplied to the IP kernel interface that user is unified, complete the monitoring of the hardware circuit to the user's design run in fpga chip, and carry out exchanges data with the hardware platform watchdog routine operated in ARM part; Network monitoring and data acquisition module operate in the PS part of ZedBoard board, are responsible for real-time and the validity of network data transmission; Feedback interactive module operates in the PS part of ZedBoard board, receive the Data Control bag of user, and analytical propagation is to FPGA, and the live signal encapsulation that simultaneously FPGA circuit supervision can be gathered, by network-feedback to user.
Use said system to carry out the method for testing, comprise the steps:
(1) server end, hardware experiment platform are connected by LAN (Local Area Network) with client PC, server end is also connected by USB-JTAG downloading wire with hardware experiment platform;
(2) server end designs automatic download module and Bitstream update module, design FPGA circuit supervision core, feedback interactive module and network monitoring and data acquisition module in hardware experiment platform, design transmission module and client emulation module on FTP in client PC, and the experiment software with custom feature is installed;
(3) user utilizes FPGA design software to carry out digital circuit experiment on client PC, the circuit that design generates to be uploaded onto the server end by transmission module on FTP with Bitstream document form, server end Bitstream update module listens to after new data stream arrives, receive data and the Bitstream file starting the automatic download user design of automatic download module in the FPGA part of hardware experiment platform;
(4) the FPGA circuit supervision IP kernel in hardware experiment platform and network monitoring match with data acquisition module, the executory relevant data of continuous collection subscriber's line circuit, and the client emulation module these data being mail to client PC by feeding back interactive module and network monitoring and data acquisition module carries out visual display, user is by the change of the software Real-time Obtaining experimental result on client PC.
Wherein: described hardware experiment platform adopts and collects the ZedBoard board of double-core ARM Cortex-A9 and FPGA in a master chip, described master chip adopts Xilinx Zynq-7000 All Programmable SoC, and its inside has the PS part of double-core ARM CortexA9 processor formation and the PL part of fpga logic.
In step (3), described automatic download module operates in server end, Bitstream file is downloaded in hardware experiment platform automatically, the listening port process of server end at running background, this process is responsible for intercepting this event of Bitstream file update that FTP service for user is uploaded, and be responsible for the microprocessor debugging XMD instrument starting Xilinx, XMD tool identification download interface, and start download service and complete programming to hardware experiment platform.
Beneficial effect: compared with prior art, its significant effect is in the present invention: (1) possesses real hardware bottom layer support, the ruuning situation of true reflection hardware circuit, the tele-experimentation under network enabled, has expanded region and the opening of experiment; (2) hardware circuit of FPGA circuit supervision IP kernel and user's design operates in the FPGA of same chip by the advantage making full use of hardware experiment platform, hardware platform watchdog routine and network monitoring and data acquisition program are operated in the ARM core of same chip, significantly reduces the burden of server; (3) user can do the contrived experiment of various digital circuit on this system, comprises logical combination, sequential logic and more complicated CPU design etc.
Accompanying drawing explanation
Fig. 1 is overall system structure schematic diagram of the present invention;
Fig. 2 is functional block diagram of the present invention.
Embodiment
As shown in Figure 1, a kind of remote circuit based on LAN (Local Area Network) and FPGA of the present invention designs hardware system, comprise server end, client PC and hardware experiment platform, being connected by LAN (Local Area Network) between three parts and communicating, also communicating by being connected between USB-JTAG downloading wire between server and hardware experiment platform; Hardware experiment platform adopts and collects the ZedBoard board of double-core ARM Cortex-A9 and FPGA in a master chip, described master chip adopts Xilinx Zynq-7000 All Programmable SoC, and its inside has the PS part of double-core ARM CortexA9 processor formation and the PL part of fpga logic.
As shown in Figure 2, server end comprises automatic download module and Bitstream update module; Bitstream update module operates in server end, automatically identifies the Bitstream file that user submits to, and carries out preserving and upgrading; Automatic download module operates in server end, Bitstream file is downloaded in hardware experiment platform automatically, the listening port process of server end at running background, this process is responsible for intercepting this event of Bitstream file update that FTP service for user is uploaded, and be responsible for the microprocessor debugging XMD instrument starting Xilinx, XMD tool identification download interface, and start download service and complete programming to hardware experiment platform.
Client PC comprises transmission module and client emulation module on FTP; Client emulation module operates on client PC, carries out local virtual hardware debug, and the Straight simulation of completing user hardware design experiment is simulated and carries out communication interaction with long-range hardware experiment platform; The upper transmission module of FTP operates in client rs PC, by LAN (Local Area Network), and the FTP service of access services device end, and Bitstream files passe user designed is to server.
Hardware experiment platform comprises FPGA part and ARM part, and FPGA part comprises FPGA circuit supervision IP kernel, and ARM part comprises feedback interactive module and network monitoring and data acquisition module; FPGA circuit supervision IP kernel operates in the PL part of ZedBoard board, be supplied to the IP kernel interface that user is unified, complete the monitoring of the hardware circuit to the user's design run in fpga chip, and carry out exchanges data with the hardware platform watchdog routine operated in ARM part; Network monitoring and data acquisition module operate in the PS part of ZedBoard board, are responsible for real-time and the validity of network data transmission; Feedback interactive module operates in the PS part of ZedBoard board, receive the Data Control bag of user, and analytical propagation is to FPGA, and the live signal encapsulation that simultaneously FPGA circuit supervision can be gathered, by network-feedback to user.
Use said system to carry out the method tested, comprise the steps:
(1) server end, hardware experiment platform are connected by LAN (Local Area Network) with client PC, server end is also connected by USB-JTAG downloading wire with hardware experiment platform;
(2) server end designs automatic download module and Bitstream update module, design FPGA circuit supervision core, feedback interactive module and network monitoring and data acquisition module in hardware experiment platform, design transmission module and client emulation module on FTP in client PC, and the experiment software with custom feature is installed;
(3) user utilizes FPGA design software to carry out digital circuit experiment on client PC, the circuit that design generates to be uploaded onto the server end by transmission module on FTP with Bitstream document form, server end Bitstream update module listens to after new data stream arrives, receive data and the Bitstream file starting the automatic download user design of automatic download module in the FPGA part of hardware experiment platform;
(4) the FPGA circuit supervision IP kernel in hardware experiment platform matches with data acquisition module with network monitoring, the executory relevant data of continuous collection subscriber's line circuit, and the client emulation module these data being mail to client PC by feeding back interactive module and network monitoring and data acquisition module carries out visual display, user can by the change of the software Real-time Obtaining experimental result on client PC.
User utilizes FPGA design software to carry out digital circuit experiment on client PC, the circuit that design generates to upload onto the server end with Bitstream document form, the Bitstream file of the new data stream that listens to server end download user design automatically after arriving is in hardware experiment platform, hardware experiment platform monitors the operation of the circuit of user's design on the one hand, on the other hand carry out alternately by the Ethernet network interface access to LAN of himself with the software on client PC, user can pass through the change of the software Real-time Obtaining experimental result on client PC.
User utilizes FPGA design software to carry out digital circuit experiment on client PC, design generates Bitstream file, this file is uploaded onto the server by transmission module on FTP, after server end Bitstream update module listens to new data stream arrival, receive data, and start Bitstream file download that user designs by the automatic download module FPGA part to hardware experiment platform; FPGA circuit supervision IP kernel in hardware experiment platform matches with data acquisition module with network monitoring, the executory relevant data of continuous collection subscriber's line circuit, and the client emulation module these data being mail to client PC by feeding back interactive module and network monitoring and data acquisition module carries out visual display.
After user is packaged into data by the control command that interface inputs by client emulation module, upload to network monitoring and the data acquisition module part of hardware experiment platform, further, by feedback interactive module and FPGA circuit supervision IP kernel, directly control the execution of subscriber's line circuit as control signal.
Although the present invention illustrates with regard to preferred implementation and describes, only it will be understood by those of skill in the art that otherwise exceed claim limited range of the present invention, variations and modifications can be carried out to the present invention.
Claims (8)
1. one kind is designed hardware system based on the remote circuit of LAN (Local Area Network) and FPGA, comprise server end, client PC and hardware experiment platform, be connected by LAN (Local Area Network) between three parts and communicate, being also connected by USB-JTAG downloading wire between server and hardware experiment platform is communicated.
2. design hardware system based on the remote circuit of LAN (Local Area Network) and FPGA as claimed in claim 1, it is characterized in that: described hardware experiment platform adopts and collects the ZedBoard board of double-core ARM Cortex-A9 and FPGA in a master chip, described master chip adopts Xilinx Zynq-7000 All Programmable SoC, and its inside has the PS part of double-core ARM CortexA9 processor formation and the PL part of fpga logic.
3. design hardware system based on the remote circuit of LAN (Local Area Network) and FPGA as claimed in claim 1, it is characterized in that: described server end comprises automatic download module and Bitstream update module; Described Bitstream update module operates in server end, automatically identifies the Bitstream file that user submits to, and carries out preserving and upgrading; Described automatic download module operates in server end, is automatically downloaded in hardware experiment platform by Bitstream file.
4. design hardware system based on the remote circuit of LAN (Local Area Network) and FPGA as claimed in claim 1, it is characterized in that, described client PC comprises transmission module and client emulation module on FTP; Client emulation module operates on client PC, carries out local virtual hardware debug, and the Straight simulation of completing user hardware design experiment is simulated and carries out communication interaction with long-range hardware experiment platform; The upper transmission module of FTP operates in client rs PC, by LAN (Local Area Network), and the FTP service of access services device end, and Bitstream files passe user designed is to server.
5. design hardware system based on the remote circuit of LAN (Local Area Network) and FPGA as claimed in claim 2, it is characterized in that, described hardware experiment platform comprises FPGA part and ARM part, FPGA part comprises FPGA circuit supervision IP kernel, and ARM part comprises feedback interactive module and network monitoring and data acquisition module; FPGA circuit supervision IP kernel operates in the PL part of ZedBoard board, be supplied to the IP kernel interface that user is unified, complete the monitoring of the hardware circuit to the user's design run in fpga chip, and carry out exchanges data with the hardware platform watchdog routine operated in AR M part; Network monitoring and data acquisition module operate in the PS part of ZedBoard board, are responsible for real-time and the validity of network data transmission; Feedback interactive module operates in the PS part of ZedBoard board, receive the Data Control bag of user, and analytical propagation is to FPGA, and the live signal encapsulation that simultaneously FPGA circuit supervision can be gathered, by network-feedback to user.
6. the remote circuit based on LAN (Local Area Network) and FPGA designs a hardware experiments method, comprises the steps:
(1) server end, hardware experiment platform are connected by LAN (Local Area Network) with client PC, server end is also connected by USB-JTAG downloading wire with hardware experiment platform;
(2) server end designs automatic download module and Bitstream update module, design FPGA circuit supervision core, feedback interactive module and network monitoring and data acquisition module in hardware experiment platform, design transmission module and client emulation module on FTP in client PC, and the experiment software with custom feature is installed;
(3) user utilizes FPGA design software to carry out digital circuit experiment on client PC, the circuit that design generates to be uploaded onto the server end by transmission module on FTP with Bitstream document form, server end Bitstream update module listens to after new data stream arrives, receive data and the Bitstream file starting the automatic download user design of automatic download module in the FPGA part of hardware experiment platform;
(4) the FPGA circuit supervision IP kernel in hardware experiment platform and network monitoring match with data acquisition module, the executory relevant data of continuous collection subscriber's line circuit, and the client emulation module these data being mail to client PC by feeding back interactive module and network monitoring and data acquisition module carries out visual display, user is by the change of the software Real-time Obtaining experimental result on client PC.
7. method as claimed in claim 6, it is characterized in that, described hardware experiment platform adopts and collects the ZedBoard board of double-core ARM Cortex-A9 and FPGA in a master chip, described master chip adopts Xilinx Zynq-7000 All Programmable SoC, and its inside has the PS part of double-core ARM CortexA9 processor formation and the PL part of fpga logic.
8. method as claimed in claim 6, it is characterized in that, in step (3), automatic download module operates in server end, Bitstream file is downloaded in hardware experiment platform automatically, the listening port process of server end at running background, this process is responsible for intercepting this event of Bitstream file update that FTP service for user is uploaded, and be responsible for the microprocessor debugging XMD instrument starting Xilinx, XMD tool identification download interface, and start download service and complete programming to hardware experiment platform.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070127A (en) * | 2015-08-11 | 2015-11-18 | 武汉美 | Interactive practical teaching system and method |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN106412013A (en) * | 2016-08-30 | 2017-02-15 | 上海新华控制技术集团科技有限公司 | Photovoltaic grid-connected Web monitoring system based on Linux |
| CN106448321A (en) * | 2016-10-31 | 2017-02-22 | 河南理工大学 | Method for realizing remote experiment and single-chip remote experiment system thereof |
| CN112055045A (en) * | 2020-07-22 | 2020-12-08 | 北京杰创永恒科技有限公司 | Network virtual laboratory system based on remote control |
| CN112380800A (en) * | 2020-12-03 | 2021-02-19 | 中国科学技术大学 | Automatic evaluation online FPGA (field programmable Gate array) experiment platform and related method |
| CN113744606A (en) * | 2021-08-11 | 2021-12-03 | 南通大学 | Embedded artificial intelligence experiment platform |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1804948A (en) * | 2005-12-14 | 2006-07-19 | 北京交通大学 | Network-based remote electronic circuit experimental method and system |
| CN202306881U (en) * | 2011-09-14 | 2012-07-04 | 北华大学 | Digital signal processing (DSP) technology comprehensive experiment platform based on network |
| CN102882932A (en) * | 2012-09-04 | 2013-01-16 | 健雄职业技术学院 | Information safety virtual experimental system based on cloudy server |
| CN103258449A (en) * | 2012-02-15 | 2013-08-21 | 中国人民解放军海军航空工程学院 | Test system networked teaching platform |
-
2015
- 2015-04-21 CN CN201510187659.7A patent/CN104821121B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1804948A (en) * | 2005-12-14 | 2006-07-19 | 北京交通大学 | Network-based remote electronic circuit experimental method and system |
| CN202306881U (en) * | 2011-09-14 | 2012-07-04 | 北华大学 | Digital signal processing (DSP) technology comprehensive experiment platform based on network |
| CN103258449A (en) * | 2012-02-15 | 2013-08-21 | 中国人民解放军海军航空工程学院 | Test system networked teaching platform |
| CN102882932A (en) * | 2012-09-04 | 2013-01-16 | 健雄职业技术学院 | Information safety virtual experimental system based on cloudy server |
Non-Patent Citations (1)
| Title |
|---|
| 孟宪元: "FPGA实现智能化嵌入式系统", 《计算机工程与应用》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070127A (en) * | 2015-08-11 | 2015-11-18 | 武汉美 | Interactive practical teaching system and method |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN105550119B (en) * | 2016-01-29 | 2018-06-19 | 中国人民解放军国防科学技术大学 | A kind of simulator based on JTAG protocol |
| CN106412013A (en) * | 2016-08-30 | 2017-02-15 | 上海新华控制技术集团科技有限公司 | Photovoltaic grid-connected Web monitoring system based on Linux |
| CN106448321A (en) * | 2016-10-31 | 2017-02-22 | 河南理工大学 | Method for realizing remote experiment and single-chip remote experiment system thereof |
| CN112055045A (en) * | 2020-07-22 | 2020-12-08 | 北京杰创永恒科技有限公司 | Network virtual laboratory system based on remote control |
| CN112380800A (en) * | 2020-12-03 | 2021-02-19 | 中国科学技术大学 | Automatic evaluation online FPGA (field programmable Gate array) experiment platform and related method |
| CN112380800B (en) * | 2020-12-03 | 2024-03-29 | 中国科学技术大学 | Online FPGA (field programmable gate array) experimental platform for automatic evaluation and related method |
| CN113744606A (en) * | 2021-08-11 | 2021-12-03 | 南通大学 | Embedded artificial intelligence experiment platform |
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