CN104810331B - Power device and its method of production - Google Patents
Power device and its method of production Download PDFInfo
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- CN104810331B CN104810331B CN201510104154.XA CN201510104154A CN104810331B CN 104810331 B CN104810331 B CN 104810331B CN 201510104154 A CN201510104154 A CN 201510104154A CN 104810331 B CN104810331 B CN 104810331B
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- Prior art keywords
- chip
- polyimide layer
- power device
- connector
- insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Organic Insulating Materials (AREA)
Abstract
The present invention proposes a kind of power device and produces its method.The power device includes the connector for being used to be electrically connected of chip and setting between the chips, and connector is connected with chip bonding, wherein, the first polyimide layer is set around the bonding point that connector is connected with chip.Thus, the bond strength of chip and connector is improved, realizes the reinforcing of bonding point, and then improves power device operating time phase reliability.
Description
Technical field
The present invention relates to power semiconductor field, more particularly to a kind of power device and produces its method.
Background technology
With the development of electronic technology, increasing electronic equipment develops towards miniaturization, integrated direction.Power device
Main devices of the part as electronic equipment, it is also dedicated to minimize and integrated.Wherein, the direction of power device miniaturization
One of be to use encapsulating structure, its structure type is that device is integrated in a packaging body.Also, with the work(of encapsulating structure
Rate density more and more higher, requirement to reliability of the power device in long-term work also more and more higher.
In power device, connector is provided with by bonding pattern between chip, to realize electrical connection.And module
In the course of the work, chip is main pyrotoxin, and heating causes thermal expansion, due to chip surface material and connector material
Thermal coefficient of expansion is variant, necessarily leads to thermal stress.Chip is in continuous switching process, and bonding point is just constantly by cycling hot
The effect of stress.Thus, bonding point intensity will be influenceed, reduces the long-term reliability of power device.
The content of the invention
The technical problems to be solved by the invention are to overcome power device of the prior art due to bonding point intensity
Caused by the deficiency that can not work reliably and with long-term.
For the above-mentioned technical problem in the presence of prior art, the present invention proposes a kind of power device and produces its
Method.The power device can reinforce bonding point, improve bonding point intensity, increase the long-term reliability of power device.
According to the first aspect of the invention, it is proposed that a kind of power device, including chip and use between the chips is set
In the connector of electrical connection, connector is connected with chip bonding, wherein, set around the bonding point that connector is connected with chip
Put the first polyimide layer.
Thus, by setting the first polyimide layer at bonding point, polyimide layer has well resistance at high temperature
High temperature creep property, the thermal stress that chip surface is born can be reduced.And polyimide layer improves chip and the bonding of connector is strong
Degree, realizes the reinforcing of bonding point.So as to reliable by setting the first polyimide layer to improve the power device operating time phase
Property.
In one embodiment, the first polyimide layer is by extending to the upper surface of whole chip around bonding point.Pass through
This set, reduce stress raisers caused by chip, improve the stress distribution of chip surface, so as to contribute into one
Step improves the long-term reliability of the power device.Meanwhile this setup simplifies the processing technology of power device, improves
Operating efficiency.
In one embodiment, in addition to substrate and be arranged on substrate upper surface liner plate, liner plate have insulator and
Attached layers of copper on insulator is set, and chip is arranged on the upper surface of attached layers of copper, in insulator positioned at the periphery of attached layers of copper
Upper surface on the second polyimide layer is set.Because the second polyimide layer has high insulation resistance, increased by above-mentioned setting
The insulating properties between chip and the insulator of liner plate are added, so as to extend the service life of whole power device.
According to the second aspect of the invention, it is proposed that a kind of method for producing above-mentioned power device, power device include core
Piece, connector, substrate, liner plate, the first polyimide layer with insulator and attached layers of copper, and the second polyimide layer, should
Method includes：
Step 1, chip is welded in the attached layers of copper of liner plate,
Step 2, connector bonding is connected on chip,
Step 3, the first polyimide layer is set on the upper surface of chip,
Step 4, liner plate is welded on the upper surface of substrate.
The power device produced by the above method, the first polyimide layer is provided with bonding point peripheral location to reinforce key
Chalaza, improve the intensity and anti-fatigue performance of bonding point.And above method process optimization, helps to ensure that power device
Long-term reliability.
In one embodiment, in step 3, is set on the upper surface of the periphery of attached layers of copper in insulator
Two polyimide layers.By this method, using the good insulating properties of the second polyimide layer, the insulation of insulator is added
Effect, so as to extend the service life of power device.Furthermore it is possible to set the first polyimide layer and the second polyamides sub- simultaneously
Amine layer, so as to optimize process, save manufacturing cost.
In step 3, the first polyimide layer is set to be included in polyamide coating acid, Yi Jigu on the upper surface of chip
Change polyamic acid to form the first polyimide layer, set second polyimide layer to be included on insulator upper surface and coat
Polyamic acid, and solidify polyamic acid to form the second polyimide layer, wherein, the solidification temperature for solidifying polyamic acid is less than
The fusing point of chip solder.The secondary thawing of the chip solder in polyamic acid solidification process is avoided by this method, from
And it ensure that the quality of power device.Thus, the above method is favorably improved the long-term reliability of power device.
In a preferred embodiment, before polyamide coating acid, diluent is added into polyamic acid.Pass through this
Kind method can adjust the viscosity of polyamic acid, so as to increase the coating uniformity of polyamic acid, reduce the life in polyimide layer
Aerogenesis steeps, thereby it is ensured that the excellent mechanical performance of polyimide layer.
Compared with prior art, it is an advantage of the current invention that improving the bond strength of chip and connector, key is realized
The reinforcing of chalaza, and then improve power device operating time phase reliability.In addition, the method for production power device can guarantee that
The excellent mechanical performance of polyimide layer.
Brief description of the drawings
The preferred embodiments of the present invention are described in detail below in conjunction with accompanying drawing.In figure：
Fig. 1 shows the structure chart of the power device according to the present invention.
Fig. 2 shows the top view of the liner plate from Fig. 1.
Fig. 3 shows the left view of the liner plate from Fig. 1.
In the accompanying drawings, identical part uses identical reference.Accompanying drawing is not drawn according to the ratio of reality.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Fig. 1 schematically shows the structure chart of the power device 100 according to the present invention.As shown in figure 1, power device
100 include chip 1 and are bonded in connector 2 thereon.This connector 2 is bonded at bonding point 11 on the upper surface of chip 1,
It is electrically connected for realizing.In the course of the work, chip 1 is main pyrotoxin to power device 100, and heating causes the He of chip 1
The thermal expansion of connector 2, and the material due to chip 1 is different from the thermal coefficient of expansion of the material of connector 2, necessarily leading to heat should
Power.In continuous switching process, bonding point 11 is just constantly acted on chip 1 by cyclic thermal stres.This stress reduction key
The intensity of chalaza 11, it is harmful to the long-time stability of power device 100.Thus, in order to increase between chip 1 and connector 2
Bond strength, the first polyimide layer 3 is set around bonding point 11.Because polyimide layer has good high temperature resistant compacted
Become performance, the first polyimide layer 3 can reduce the thermal stress that the surface of chip 1 is born, so as to solidify bonding point 11.Thus, improve
The long-term reliability of power device 100.
To reduce production cost, while simplify process, connector 2 is it is so structured that aluminum steel.It should be noted that even
Fitting 2 is not limited to aluminum steel, can also be manufactured by other materials.For example, copper or silver etc..
As shown in Fig. 2 in a preferred embodiment, the first polyimide layer 3 extends to the whole surface of chip 1
On.First polyimide layer 3 is evenly distributed on the surface of whole chip 1, reduces stress raisers caused by chip 1,
The stress distribution situation on the surface of chip 1 is improved, further improves the long-term reliability of power device 100.It is in addition, this
The first polyimide layer 3 that mode is set, help to realize the uniformity of film of the first polyimide layer 3, ensure that it is good
Mechanical performance.
As shown in figure 1, power device 100 also includes substrate 4 and liner plate 5.Liner plate 5 sets substrate 4 by way of welding
Upper surface on.Liner plate 5 includes insulator 51 and the attached layers of copper 52 being arranged on insulator 51.Chip 1 is arranged on attached layers of copper 52
Upper surface on.It is, on direction from top to bottom, power device 100 is disposed with substrate 4, liner plate 5, the and of chip 1
Connecting line 2.
As shown in Fig. 2 second polyimide layer is set on the upper surface of the periphery of attached layers of copper 52 in insulator 51
6.Second polyimide layer 6 make use of the insulating properties of polyimide layer, add between chip 1 and the insulator 51 of liner plate 5
Insulating properties.So as to ensure that the reliability of the work of power device 100 by the second polyimide layer 6, and extend power device
The service life of part 100.
The method for describing production power device 100 in detail below according to Fig. 1 to 3.
When producing power device 100, first, chip 1 is arranged on by way of welding in the attached layers of copper 52 of liner plate 5.
Then, wire bonding is carried out.It is, aluminum steel 2 is bonded on the upper surface of chip 1.Again, the upper surface of chip 1 (
Exactly be bonded with the surface of aluminum steel 2) on the first polyimide layer 3 is set.Finally, liner plate 5 is welded on to the upper surface of substrate 4
On.It should be noted that the first polyimide layer 3 can be provided only on around bonding point 11.But in order to further improve
Bond strength at bonding point 11, protects chip 1, and the first polyimide layer 3 is arranged on the whole upper surface of chip 1.
The first polyimide layer 3 is set to include procedure below：The first polyamide coating acid on the upper surface of chip 1, then it is solid
Change polyamic acid to form the first polyimide layer 3.While the first polyimide layer 3 are generated, in the upper table of insulator 51
Polyamide coating acid on the periphery (surface for being provided with chip 1) of the attached layers of copper 52 in face, solidification polyamic acid are poly- to form second
Imide layer 6.It is the good insulating properties that make use of polyimide layer to set the second polyimide layer 6, to increase insulator 51
Insulation effect, so as to extend the service life of power device 100.
In polyamic acid solidification process, to avoid the secondary thawing of solder of the chip 1 of power device 100, polyamic acid
Solidification temperature be less than chip 1 solder fusing point.Thus, the solidification temperature of polyamic acid has no effect on the jail of the welding of chip 1
Soundness, so as to ensure that the soldering reliability of chip 1, improve its working life.Being more conducive to the long-term of increment rate device can
By property.
, can be to before polyamide coating acid to ensure the uniformity of the first polyimide layer 3 and the second polyimide layer 6
Diluent is added in polyamic acid.In coating procedure, the polyamic acid being diluted helps to control the generation of bubble.It is and dilute
Release agent to volatilize in polyamic acid solidification process, to the first polyimide layer 3 and the mechanics of the second polyimide layer 6 formed
Performance does not influence.So as to ensure that the excellent mechanical performance of polyimide layer.
High according to the intensity of the bonding point 11 of the power device 100 of the present invention, the stress distribution on the surface of chip 1 is more equal
Even, long-term use of reliability is high.Meanwhile the good insulating between chip 1 and the insulator 51 of liner plate 5.In addition, this power device
100 is simple in construction, and production technology is easy, is advantageous to promote.
It should be noted that in 1 to 3 in figure, the first polyimide layer 3 and the second polyimide layer 6 are linear with section
Formula represents.
It should be noted that orientation term " on " " under " using the structure chart shown in Fig. 1 as reference.
The preferred embodiment of the present invention is the foregoing is only, but the scope of the present invention is not limited thereto, Ren Heben
The technical staff in field easily can be changed or change in technical scope disclosed by the invention, and this change or change
Change should be all included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (6)
1. a kind of power device, including chip and the connector for being used to be electrically connected that is arranged between the chip, the company
Fitting is connected with the chip bonding, it is characterised in that is set around the bonding point that the connector is connected with the chip
First polyimide layer；
First polyimide layer is by extending to the upper surface of the whole chip around bonding point.
2. power device according to claim 1, it is characterised in that also including substrate and the upper table for being arranged on the substrate
Liner plate on face, the liner plate have insulator and the attached layers of copper being arranged on the insulator, and the chip is arranged on described
In attached layers of copper, the second polyimide layer is set on the upper surface of the periphery of the attached layers of copper in the insulator.
3. a kind of method for producing the power device according to claim 1 or claim 2, the power device includes core
Piece, connector, substrate, liner plate, the first polyimide layer with insulator and attached layers of copper, and the second polyimide layer, its
It is characterised by, including：
Step 1, the chip is welded in the attached layers of copper of the liner plate,
Step 2, connector bonding is connected on the chip,
Step 3, the first polyimide layer is set on the upper surface of the chip,
Step 4, the liner plate is welded on the upper surface of the substrate.
4. according to the method for claim 3, it is characterised in that in step 3, in the insulator positioned at described attached
Second polyimide layer is set on the upper surface of the periphery of layers of copper.
5. according to the method for claim 4, it is characterised in that in step 3, the first polyimide layer bag is set
The polyamide coating acid on the upper surface of the chip, and solidification polyamic acid are included to form the first polyimide layer,
Second polyimide layer is set to be included in polyamide coating acid on the insulator upper surface, and solidification polyamide
Acid to form the second polyimide layer, wherein, solidify polyamic acid solidification temperature be less than the chip solder fusing point.
6. according to the method for claim 5, it is characterised in that before polyamide coating acid, added into polyamic acid
Diluent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510104154.XA CN104810331B (en) | 2015-03-10 | 2015-03-10 | Power device and its method of production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510104154.XA CN104810331B (en) | 2015-03-10 | 2015-03-10 | Power device and its method of production |
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| Publication Number | Publication Date |
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| CN104810331A CN104810331A (en) | 2015-07-29 |
| CN104810331B true CN104810331B (en) | 2017-11-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510104154.XA Active CN104810331B (en) | 2015-03-10 | 2015-03-10 | Power device and its method of production |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| TW200301945A (en) * | 2002-01-03 | 2003-07-16 | Taiwan Semiconductor Mfg | Method of wafer level package using elastomeric electroplating mask |
| CN102945837A (en) * | 2012-10-24 | 2013-02-27 | 西安永电电气有限责任公司 | Semiconductor module structure and connecting and fixing method for bonding wires therein |
| CN103779342A (en) * | 2014-01-24 | 2014-05-07 | 嘉兴斯达微电子有限公司 | Power semiconductor module |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338947A (en) * | 2000-05-26 | 2001-12-07 | Nec Corp | Flip chip type semiconductor device and its manufacturing method |
| US20100301467A1 (en) * | 2009-05-26 | 2010-12-02 | Albert Wu | Wirebond structures |
-
2015
- 2015-03-10 CN CN201510104154.XA patent/CN104810331B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| TW200301945A (en) * | 2002-01-03 | 2003-07-16 | Taiwan Semiconductor Mfg | Method of wafer level package using elastomeric electroplating mask |
| CN102945837A (en) * | 2012-10-24 | 2013-02-27 | 西安永电电气有限责任公司 | Semiconductor module structure and connecting and fixing method for bonding wires therein |
| CN103779342A (en) * | 2014-01-24 | 2014-05-07 | 嘉兴斯达微电子有限公司 | Power semiconductor module |
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| Publication number | Publication date |
|---|---|
| CN104810331A (en) | 2015-07-29 |
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Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CSR TIMES ELECTRIC Co.,Ltd. |
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Effective date of registration: 20201015 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |