CN104810302A - Monitoring wafer and preparation method thereof - Google Patents
Monitoring wafer and preparation method thereof Download PDFInfo
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- CN104810302A CN104810302A CN201410032441.XA CN201410032441A CN104810302A CN 104810302 A CN104810302 A CN 104810302A CN 201410032441 A CN201410032441 A CN 201410032441A CN 104810302 A CN104810302 A CN 104810302A
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- outer box
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract
The invention discloses a monitoring wafer and a preparation method thereof. The monitoring wafer is provided with an outer box structure, wherein an inner edge and an outer edge of the outer box structure are concentric patterns. According to the invention, a wafer, which is acquired by single-layer etching and provided with the outer box structure, is adopted to act as the monitoring wafer. A monitoring wafer in the prior art comprises an outer box structure and an inner box structure and can be acquired by two-layer etching. The monitoring wafer disclosed by the invention only has the outer box structure, that is, the monitoring wafer can be acquired by only single-layer etching. A registration error between two layers of patterns does not exist in single-layer etching, thereby being capable of realizing that central values in the X-direction and in the Y-direction are zero. A specific target value is provided, and conformation and adjustment can be carried out timely when abnormal conditions such that the target value of a machine drifts and the like. When an existing monitoring wafer is damaged, a wafer with the same outer box structure can be used to replace the damaged monitoring wafer immediately, thereby having the substitutability.
Description
Technical field
The present invention relates to semiconductor processing technology field, particularly relate to a kind of monitoring wafer and preparation method thereof.
Background technology
In semiconducter process, overlay is one of topmost monitoring project in photoetching process, and it directly reflects the alignment situation between figure.Quaestor Q7(5 as the measurement board of overlay) equipment, its stable measurement technique is data inevitable prerequisites really, is also the reliable guarantee of product quality.
In semiconductor manufacturing industry, Quaestor Q7(5) overlay of serial board measures technology stability monitoring, and generally include two aspects: one, whether the measurement result of single board in long-term production process be consistent; Its two, whether the measurement result of multiple board within the same period consistent.No matter being that single board is measured or multiple bench monitoring, is all realized by the box-in-box structure in periodic measurement particular wafer (wafer).The above-mentioned specifically monitored wafer of general making has two kinds of methods: first method, and form box-in-box structure with two-layer etching technics, can bring larger technique registration error, the accuracy of the box-in-box structure of actual monitored wafer is difficult to control 0/0; Second method, directly forming box-in-box structure with individual layer etching technics then needs additionally to make mask plate, and cost is higher, but above-mentioned two kinds of methods have respective drawback.
If for above-mentioned first method, adopt the wafer in scrap products, by measuring the box-in-box structure that two-layer etching (Etch) technique is formed, as shown in Figure 1, this measurement result comprises registration error when two layer patterns are formed to schematic diagram.Owing to there is the registration error of two-layer graphics art, can not determine central value according to above-mentioned measurement result, namely can not determine which numerical value is desired value, therefore target is uncertain.In addition, if using mean value as desired value, and this registration error is fixing, then, when this monitoring wafer lost efficacy or damage, can not find the alternative wafer with identical registration error (i.e. same target value).Therefore, the monitoring wafer adopting the method for two-layer etching to obtain does not have substitutability.
Summary of the invention
(1) technical problem that will solve
For above-mentioned defect, the technical problem to be solved in the present invention how to make the monitoring wafer used to have substitutability.
(2) technical scheme
For solving the problem, the invention provides a kind of monitoring wafer, described monitoring wafer has outer box structure, and the inward flange of described outer box structure is concentric figure with outward flange.
Further, the graphics shape of described monitoring wafer is circular or square.
Further, when described monitoring wafer is square, described monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.
Further, the length of side of the inward flange of described monitoring wafer is 20um, and the length of side that outward flange is is 30um.
Further, the distance on different monitoring wafers between inward flange and outward flange is not unique, selects the monitoring wafer of inward flange and outward flange different distance according to the use scenes of described monitoring wafer.
Further, the central value of described monitoring wafer is zero, has clear and definite desired value, when board desired value is drifted about, adjusts in time.
Further, when the monitoring wafer that board is using damages, substitute with the monitoring wafer with identical outer box structure.
For solving the problems of the technologies described above, present invention also offers a kind of monitoring wafer preparation method, comprising: etching forms the monitoring wafer with outer box structure on wafer, and the inward flange of described outer box structure is concentric figure with outward flange.
Further, the monitoring wafer that described etching formation has outer box structure specifically comprises:
First etch the outward flange of described outer box figure, then etch the inward flange of described outer box figure;
Or first etch the inward flange of described outer box figure, then etch the outward flange of described outer box figure;
Or etch outward flange and the inward flange of out box figure simultaneously.
Further, the graphics shape of described monitoring wafer is circular or square.
Further, when described monitoring wafer is square, described monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.
Further, the length of side of the inward flange of described monitoring wafer is 20um, and the outer peripheral length of side is 30um.
(3) beneficial effect
The invention provides a kind of monitoring wafer and preparation method thereof, wherein this monitoring wafer has outer box structure, and the inward flange of described outer box structure is concentric figure with outward flange.The present invention is by etch the wafer with outer box structure that obtains as monitoring wafer using individual layer, outer box structure is comprised and inner case structure needs just can obtain through two-layer etching due to prior art, and this monitoring wafer only has outer box structure, namely carry out individual layer etching can obtain, individual layer etching would not have the registration error between two layer patterns, can realize being zero in the central value of X-direction and Y-direction, there is clear and definite desired value, when the abnormal conditions such as drift appear in the desired value of board, can confirm in time and adjust.When existing monitoring wafer occurs damaged, can replace with the wafer with identical outer box structure immediately, there is substitutability.
Accompanying drawing explanation
Fig. 1 is the box-in-box structural representation monitoring wafer in prior art;
A kind of outer box structural design schematic diagram of monitoring wafer of Fig. 2 for providing in the embodiment of the present invention;
Fig. 3 for the figure that the embodiment of the present invention provides be concentrically ringed outer box structural design drawing.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Monitor wafer (wafer) in Fig. 1 of prior art and comprise outer box structure 01 and inner case structure 02, outer box structure 01 i.e. outer box, inner case structure 02 i.e. inner box, for Quaestor Q7(5) the monitoring wafer of serial board is square, wherein inner box is the length of side is the square of 10um, the inward flange of outer box is the length of side is the square of 20um, and the outward flange of outer box is the length of side is the square of 30um.
The measurement result adopting the monitoring wafer of prior art to obtain is X-direction: (x2-x1)/2; Y-direction: (y2-y1)/2, wherein x1 is the distance between the right side inward flange of outer box structure 01 and the right side outward flange of inner case structure 02, x2 is the distance between the left side inward flange of outer box structure 01 and the left side outward flange of inner case structure 02, y1 is the distance between the upside inward flange of outer box structure 01 and the upside outward flange of inner case structure 02, and y2 is the distance between the downside inward flange of outer box structure 01 and the downside outward flange of inner case structure 02.
Above-mentioned outer box structure 01 and inner case structure 02 are the figures obtained by two-layer etching, registration error is there is in this two layer pattern when being formed, due to this monitoring wafer complete after registration error just fix, be not easy when losing efficacy or damage to find and replace wafer and replace.
The utility model embodiments provides a kind of monitoring wafer, and this monitoring wafer has outer box structure 01, and inward flange S2 and the outward flange S1 of outer box structure are concentric figure.
Preferably, the graphics shape of above-mentioned monitoring wafer is circular or square, certainly, the monitoring wafer of other shapes can also be selected according to the situation of board, but need the outward flange ensureing monitoring wafer to be concentric figure with inward flange, can be concentric circles, can also be the concentric figure of other shape.Such as, as shown in Figure 3, outward flange and inward flange are concentrically ringed monitoring wafer graphic structure.Board in the present embodiment is Quaestor Q7(5) series board, therefore select monitoring wafer graphic structure be square, schematic diagram is as shown in Figure 2.The outward flange of its China and foreign countries' box structure represents with S1, inward flange S2 represents, distance between the right side outward flange S1 that x1 ' is outer box structure 01 and inward flange S2, distance between the left side outward flange S1 that x2 ' is outer box structure 01 and inward flange S2, distance between the upside outward flange S1 that y1 ' is outer box structure 01 and inward flange S2, the distance between the downside outward flange S1 that y2 ' is outer box structure 01 and inward flange S2.
According to Fig. 2, when monitoring wafer is square, monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.Can adjust as required for the distance size between the monitoring inward flange of wafer and outward flange, as long as ensure that monitoring board can identify the outward flange after adjustment and inward flange, and can be used for calculating.
In addition, the distance on different monitoring wafers between inward flange and outward flange is not unique, selects the monitoring wafer of inward flange and outward flange different distance according to the use scenes of monitoring wafer.Preferably, the length of side of the inward flange of the monitoring wafer in the present embodiment is 20um, and the outer peripheral length of side is 30um.
The central value of the monitoring wafer in the present embodiment is zero, has clear and definite desired value, when board desired value is drifted about, can adjust in time.For the monitoring wafer in the present embodiment, the testing result obtained is:
X-direction: (x2 '-x1 ')/2;
Y-direction: (y2 '-y1 ')/2.
Monitoring wafer in employing the present embodiment is owing to only having one deck etched features, therefore the measurement result obtained does not comprise the registration error between two layer patterns, be zero in the central value (i.e. design load) of X-direction and Y-direction, monitoring wafer simultaneously in the present embodiment also has an advantage: when the monitoring wafer that board is using damages, and substitutes with the monitoring wafer with identical outer box structure.
Below the monitoring result that the same graphic structure of monitoring wafer on three different platforms respectively in five same wafer of point in time measurement only having outer box structure to the individual layer had in prior art in the monitoring wafer of two layer patterns and the present embodiment respectively obtains is as follows:
Table 1
Table 2
Above-mentioned table 1 is the monitored results of prior art, and table 2 is the monitored results of the present embodiment, the Data Comparison according in table 1 and table 2:
1) because there is the registration error of two-layer graphics art, the monitored results of prior art can not confirm central value, namely can not illustrate which number is desired value.And the central value of the present embodiment (i.e. Theoretical Design value) is zero, there is clear and definite desired value, when board desired value is drifted about, can to go forward side by side Row sum-equal matrix by Timeliness coverage.
2) if using mean value as desired value in prior art, when this wafer is damaged, by being difficult to the alternative wafer finding same target value, neither there is substitutability.And the monitoring wafer of individual layer etched features easily finds replacement wafer to replace in the present embodiment, there is substitutability.
3) the result value fluctuation that obtains of prior art is very large, and for the x value that on board 1, five times are measured, minimum value is 0.033um, and maximum is 0.042um, between differ about 0.01um, namely fluctuation is very large.And the x value measured for five times on the result board 1 that the present embodiment obtains is example, minimum value is 0.001um, and maximum is 0.003um, between differ about 0.002um, and also having three numerical value to be all identical 0.002um, result is substantially in the lower fluctuation above freezing of theoretical design load, relatively stable.Because eliminate registration error, the result of the present embodiment more truly can reflect the stability of board.
In sum, the monitoring wafer provided in the present embodiment has following characteristics:
1) error is little, because outer box structure is that single layer process is formed, does not comprise registration error;
2) centrales scale value is clear and definite, when board occurs abnormal, and convenient confirmation and adjustment;
3) by force substituting, when existing monitoring wafer damages, can replace with the wafer with identical outer box structure.
Based on above-mentioned, the present embodiment also provides a kind of monitoring wafer preparation method, comprising: on wafer, etching forms the monitoring wafer with outer box structure, and inward flange and the outward flange of outer box structure are concentric figure.
Preferably, etching forms the monitoring wafer with outer box structure and specifically comprises:
First etch the outward flange of outer box figure, then etch the inward flange of outer box figure;
Or first etch the inward flange of outer box figure, then etch the outward flange of outer box figure;
Or etch outward flange and the inward flange of out box figure simultaneously.
Preferably, the graphics shape monitoring wafer is circular or square.
Further, when monitoring wafer is square, monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.Concrete, the length of side etching the inward flange of the monitoring wafer obtained in the present embodiment is 20um, and the outer peripheral length of side is 30um.
Based on above-mentioned preparation method, individual layer is etched the wafer with outer box structure that obtains as monitoring wafer, this monitoring wafer only has outer box structure, namely carry out individual layer etching can obtain, individual layer etching would not have the registration error between two layer patterns, can realize being zero in the central value of X-direction and Y-direction, have clear and definite desired value, when the abnormal conditions such as drift appear in the desired value of board, can confirm in time and adjust.When existing monitoring wafer occurs damaged, can replace with the wafer with identical outer box structure immediately, there is substitutability.
Above execution mode is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (12)
1. monitor a wafer, it is characterized in that, described monitoring wafer has outer box structure, and the inward flange of described outer box structure is concentric figure with outward flange.
2. monitor wafer as claimed in claim 1, it is characterized in that, the graphics shape of described monitoring wafer is circular or square.
3. monitor wafer as claimed in claim 2, it is characterized in that, when described monitoring wafer is square, described monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.
4. monitor wafer as claimed in claim 3, it is characterized in that, the length of side of the inward flange of described monitoring wafer is 20um, and the length of side that outward flange is is 30um.
5. monitor wafer as claimed in claim 1, it is characterized in that, the distance on different monitoring wafers between inward flange and outward flange is not unique, selects the monitoring wafer of inward flange and outward flange different distance according to the use scenes of described monitoring wafer.
6. monitor wafer as claimed in claim 1, it is characterized in that, the central value of described monitoring wafer is zero, has clear and definite desired value, when board desired value is drifted about, adjusts in time.
7. monitor wafer as claimed in claim 1, it is characterized in that, when the monitoring wafer that board is using damages, substitute with the monitoring wafer with identical outer box structure.
8. monitor a wafer preparation method, it is characterized in that, comprising: etching forms the monitoring wafer with outer box structure on wafer, and the inward flange of described outer box structure is concentric figure with outward flange.
9. monitoring wafer preparation method as claimed in claim 8, is characterized in that, described etching forms the monitoring wafer with outer box structure and specifically comprises:
First etch the outward flange of described outer box figure, then etch the inward flange of described outer box figure;
Or first etch the inward flange of described outer box figure, then etch the outward flange of described outer box figure;
Or etch outward flange and the inward flange of out box figure simultaneously.
10. monitoring wafer preparation method as claimed in claim 8, is characterized in that, the graphics shape of described monitoring wafer is circular or square.
11. monitor wafer preparation method as claimed in claim 10, and it is characterized in that, when described monitoring wafer is square, described monitoring wafer is all identical with the distance between outward flange at the inward flange of four edge directions.
12. monitor wafer preparation method as claimed in claim 11, and it is characterized in that, the length of side of the inward flange of described monitoring wafer is 20um, and the outer peripheral length of side is 30um.
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| CN201410032441.XA CN104810302B (en) | 2014-01-23 | 2014-01-23 | A kind of application method monitoring wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110364449A (en) * | 2019-07-24 | 2019-10-22 | 上海华力集成电路制造有限公司 | The monitoring method of grid oxygen nitrating annealing temperature |
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| US6357131B1 (en) * | 1999-12-20 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Overlay reliability monitor |
| US20020102482A1 (en) * | 2000-12-08 | 2002-08-01 | Adlai Smith | Reference wafer and process for manufacturing same |
| CN101286013A (en) * | 2007-03-27 | 2008-10-15 | Asml荷兰有限公司 | Method of forming a substrate for use in calibrating a metrology tool, calibration substrate and metrology tool calibration method |
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| CN110364449A (en) * | 2019-07-24 | 2019-10-22 | 上海华力集成电路制造有限公司 | The monitoring method of grid oxygen nitrating annealing temperature |
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