CN104810253B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN104810253B CN104810253B CN201410042208.XA CN201410042208A CN104810253B CN 104810253 B CN104810253 B CN 104810253B CN 201410042208 A CN201410042208 A CN 201410042208A CN 104810253 B CN104810253 B CN 104810253B
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Abstract
A kind of forming method of semiconductor devices, including：Substrate is provided, substrate includes first area, second area and the 3rd region；The substrate surface for being covered in second area and first mask layer on isolation structure surface are formed, the side wall of the first mask layer is located at second area isolation structure surface, and first mask layer has antireflection effect；The first photoresist layer is formed, exposes the part first mask layer surface adjacent with the 3rd region；Using the first photoresist layer and the first mask layer exposed as mask, the first doping is carried out to the substrate in the 3rd region, forms the first doped region.The present invention improves the position precision of the mask of doping process, avoids being adulterated in undesirable region, improves the reliability and electric property of semiconductor devices.
Description
Technical field
The present invention relates to the forming method of field of semiconductor manufacture technology, more particularly to semiconductor devices.
Background technology
In technical field of semiconductors, with developing rapidly for nanofabrication technique, the characteristic size of transistor has been enter into
Nanoscale.With the continuous reduction of device size, the photoetching process of ion implanting (refers to by being lithographically formed ion implantation mask layer
Technique) receive increasing challenge.
In semiconductor technology processing procedure, the photoetching process of ion implanting is typically using the photoresist layer directly contacted with substrate
As mask, the photoresist layer is influenceed by from integrated substrate on critical size.For example, substrate includes active area
(AA areas, material are generally Si) isolates (STI, material are generally silica), the reflectivity caused by material difference with shallow trench
Difference, typically influence one of most important factor of critical size.Because foregoing AA and sti region have different reflections
Rate, therefore, the photoresist layer on both interfaces can be correspondingly received different light exposures, and which results in most end form
Into the CD values of patterned photoresist layer be difficult to be controlled well.
To meet the requirement of photoetching process, ARC (Anti-Reflective Coating：ARC) technology is answered
For improving the precision of photoetching in photoetching.The effect of ARC is mainly：Prevent light by being covered after photoresist under
Bed boundary is reflected；And the light reflected can interfere with incident light, photoresist is caused to be unable to uniform exposure.Anti-reflective coating
Layer includes reflection coating provided (Top Anti-Reflective Coating：) and bottom antireflective coating (Bottom TARC
Anti-Reflective Coating：BARC).
However, the use of bottom ARC necessarily increases the cost of photoetching process, lightly doped district (LDD) is particularly defined
With the photoetching process of the ion implanting of threshold voltage adjustments area (Vt-Well), while also increase etch process complexity and
Process costs.
In the technical process that prior art forms semiconductor devices, define lightly doped district and threshold voltage adjustments area from
The photoetching process of son injection because being related to the different doping in multiple regions, the position of the multiple photoresist layer being lithographically formed with
And pattern is easily and deviation, the electricity for the semiconductor devices that its deviation accumulation effect results in occur for actual set position and pattern
Learn degraded performance.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor devices, improves and doped region is formed in substrate
Mask position precision, while process costs are saved, improve the reliability and electric property of semiconductor devices.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Substrate is provided, it is described
Substrate includes first area, second area and the 3rd region, and the first area, second area and the 3rd region are by isolation junction
Structure is kept apart；Form the substrate surface for being covered in second area and first mask layer on isolation structure surface, the first mask layer
Side wall be located at second area isolation structure surface, and first mask layer has antireflection effect；Formed positioned at described the
First photoresist layer of one region surface and part the first mask layer surface, expose the part adjacent with the 3rd region
One mask layer surface；Using first photoresist layer and the first mask layer exposed as mask, the substrate in the 3rd region is entered
Row first adulterates, and forms the first doped region；Form the positioned at the 3rd region surface and part the first mask layer surface
Three photoresist layers, expose the part first mask layer surface adjacent with first area；With the 3rd photoresist layer and exposure
The first mask layer gone out is mask, carries out the second doping to the substrate of first area, forms the second doped region.
Optionally, the forming step of the first mask layer includes：Formation is covered in first area, second area and the 3rd region
The first original mask layer on surface, the first original mask layer have antireflection effect；Form first positioned at second area
Second photoresist layer of original mask layer surface；Using second photoresist layer as mask, the first original mask layer is etched,
Form the substrate surface for being covered in second area and first mask layer on isolation structure surface.
Optionally, the lithographic accuracy of second photoresist layer is higher than the first photoresist layer and the light of the 3rd photoresist layer
Carve precision.
Optionally, the packing material of the isolation structure is insulating materials, and insulating materials is silica.
Optionally, the border of first mask layer is located at isolation structure surface.
Optionally, first mask layer is double-decker, and the first mask layer includes first time mask layer and positioned at the
Mask layer on the first of mask layer surface once.
Optionally, the material of first time mask layer is the Spun-on carbon of cross-linking type, the material of mask layer on described first
For spin coating silicon or siliceous bottom anti-reflective material.
Optionally, the thickness of first time mask layer is 1000 angstroms to 5000 angstroms, the thickness of mask layer on described first
For 200 angstroms to 2000 angstroms.
Optionally, after etching the first original mask layer and forming the first mask layer, etching removes the first photoresist layer.
Optionally, the substrate is in addition to including first area, second area and the 3rd region, in addition to the first mask layer
The region of adjacent doped region to be formed；First mask layer is the part mask for the technique to form the doped region.
Optionally, after the first doped region is formed, in addition to step：Remove first photoresist layer.
Optionally, the technique of the first photoresist layer of removal is：Cineration technics is carried out to the first photoresist layer, after cineration technics
Carry out the wet-etching technology of weak oxide.
Optionally, the etch liquids of the wet-etching technology of the weak oxide are：The mixing of sulfuric acid solution and SC1 solution
Solution, and mixed solution temperature is less than 100 degree, wherein, SC1 solution is the aqueous solution of ammoniacal liquor and hydrogen peroxide.
Optionally, after the second doped region is formed, in addition to step：Remove the 3rd photoresist layer and first
Mask layer；The second mask layer positioned at first area and the 3rd region is formed, and second mask layer has antireflection effect；
The 5th photoresist layer positioned at part the second mask layer surface is formed, exposes part second mask layer adjacent with second area
Surface；Using the 5th photoresist layer and the second mask layer exposed as mask, the 3rd doping is carried out to second area substrate,
Form the 3rd doped region；Remove the 5th photoresist layer.
Optionally, the technique of the first mask layer of removal is：Mask layer on first is removed using dry etch process；Using tool
The wet-etching technology for having strong oxidizing property removes first time mask layer.
Optionally, the etching gas of the dry etch process are CxFyOr CxHyFz；The wet etching of the strong oxidizing property
The etch liquids of technique are：The mixed solution of sulfuric acid solution, hydrogen peroxide solution and SC1 solution, mixed solution temperature are higher than 100
Degree, wherein, SC1 solution is the aqueous solution of ammoniacal liquor and hydrogen peroxide.
Optionally, the forming step of second mask layer includes：Formed in first area, second area and the 3rd region
Second original mask layer；The 4th initial lithographic glue-line is formed in the second original mask layer surface；To second initial light
Photoresist layer is exposed, development treatment, forms the 4th photoresist layer positioned at first area and the 3rd region；With the 4th light
Photoresist layer is mask, etches the second original mask layer, forms the second mask layer positioned at first area and the 3rd region, and carving
During losing the second original mask layer, etching removes the 4th photoresist layer.
Optionally, the substrate is in addition to including first area, second area and the 3rd region, in addition to the second mask layer
The region of adjacent doped region to be formed；Second mask layer is the part mask for the technique to form the doped region.
Optionally, the technique of first doping and the second doping is ion implanting.
Compared with prior art, technical scheme has advantages below：
The present invention forms the first mask layer, the first mask layer side wall in second area substrate surface and isolation structure surface
Positioned at isolation structure surface, and the first mask layer has antireflection effect so that and the position precision of the first mask layer is high, and first
Mask layer is completely covered second area and only covers second area；Subsequently formed to the first doping process of the 3rd region progress
The first photoresist layer when, first photoresist layer can expose part the first mask layer surface, reduce to formed first
(the first photoresist layer can use the photoetching process of more low side, such as 248nm/365nm photoetching work to the technological requirement of photoresist layer
Skill), reduce technology difficulty and process costs, and the first photoresist layer and high the first mask layer conduct of position precision
The mask of first doping process, the position precision of the mask is high, avoids the occurrence of second area and is partly exposed or the 3rd
The situation that region is partially covered, improve the reliability and electric property of the semiconductor devices to be formed.
Meanwhile first mask layer is also used as carrying out first area the part mask of the second doping, is reducing
While carrying out the 3rd photoresist layer formation process difficulty of the second doping, reuse using a photoetching and etching i.e. shape
Into the first mask layer, in the case where not increasing additional technology cost, the position for improving the second doped region to be formed is accurate
Degree.
Further, the present invention forms the first original mask layer on first area, second area and the 3rd area substrate surface,
Because the first original mask layer has antireflection effect, the unnecessary light reflection occurred during exposure-processed is reduced so that
The position precision for the first photoresist layer that the first original mask of second area layer surface is formed is high and has good pattern, enters
One step make it that the position precision of the first mask layer formed using the first photoresist layer as mask layer is high, and the second mask layer covers completely
Lid second area and only cover second area.
Further, the first mask layer be first time mask layer and first on mask layer laminated construction, first time mask
The material of layer is the Spun-on carbon of cross-linking type, and mask layer not only has antireflection effect on first, also acts as and is covered under protection first
Film layer is not by the effect destroyed, then after the completion of subsequently the first photoresist layer technique is removed, first time mask layer still has good
Good pattern and higher position precision；And first time mask layer accounts for great (the first time mask layer of ratio of the first mask layer
(1000 angstroms to 5000 angstroms) of thickness than first on mask layer thickness (200 angstroms to 2000 angstroms)) so that the first mask layer is still
Second area completely is covered in, the first mask layer still has higher position precision, therefore, using the first mask layer as shape
Into the part mask of the second doped region, the position precision to form the second doped region is can further improve, further improves and partly leads
The reliability and electric property of body device.
Further, the substrate is in addition to including first area, second area and the 3rd region, in addition to the first mask
During the region of the adjacent doped region to be formed of layer, first mask layer can also be as the portion for the technique for forming the doped region
Point mask, repeatedly using position precision height and good the first mask layer of pattern as the part mask for forming doped region, not only
So that the position precision of the doped region formed is high, the reliability and electric property for forming semiconductor devices are further improved, and
And it reduce further process costs.
Brief description of the drawings
Fig. 1 is the schematic flow sheet that an embodiment forms semiconductor devices；
Fig. 2 is light reflectogram of the light in active area and isolation structure interface of photoresist layer exposure；
Fig. 3 to Figure 17 is the cross-sectional view for the semiconductor devices forming process that another embodiment of the present invention provides.
Embodiment
As stated in the Background Art, the electric property for the semiconductor devices that prior art is formed is poor.
Therefore, being studied for the forming method of semiconductor devices, the forming method of semiconductor devices includes following step
Suddenly, it refer to Fig. 1：Step S1, substrate is provided, the substrate includes first area and second area, and the first area serves as a contrast
Basal surface has first grid structure, and the second area substrate surface has second grid structure；Step S2, described first
Area substrate surface forms the first side wall, and first side wall is located at first grid structure both sides, in the second area substrate
Surface forms the second side wall, and second side wall is located at second grid structure both sides；Step S3, in the second area substrate table
Face forms photoresist layer；Step S4, using photoresist layer as mask, the first area substrate formation to first grid structure both sides is mixed
It is miscellaneous, form doped region；Step S5, the photoresist layer of second area is removed.
There is deviation, caused in the forming method of the semiconductor devices of above-mentioned offer, the doping zone position easily resulted in
Also adulterated in undesirable region, influence the electric property of semiconductor devices.
For semiconductor devices forming method carry out further study show that, cause adulterate zone position there is the original of deviation
Because being：After forming photoresist layer on second area surface, the figure of photoresist layer and the expected figure formed have deviation, so as to
There is deviation in the position of the doped region resulted in.The figure of the photoresist layer and the expected figure reason devious formed
It is：
First, in photoresist layer exposure process, the light of exposure reflects in substrate surface, causes photoresist layer to expose
Light is uneven.Secondly, in order to prevent being electrically connected in semiconductor devices, first area and second area are used into isolation structure
It is isolated, refer to Fig. 2, AA1 is first area (active area), and AA2 is second area, and STI is isolation structure, and PR is photoresist
Layer；In photoresist layer exposure process, the light 01 of exposure reflects in the interface of first area substrate and isolation structure,
The uneven exposure of side wall of photoresist layer is caused, influences subsequently to form doped region in the substrate of first area.When substrate is including more
, it is necessary to repeatedly form photoresist layer to carry out the ion implantation technology of different zones, repeatedly during the region of individual doped region to be formed
The position of photoresist layer that is formed of photoetching process and pattern easily and deviation, its error occur for actual set position and pattern
The electric property for the semiconductor devices that accumulative effect results in is low.
In order to solve the problems, such as that photoresist layer exposure is uneven, it is proposed that bottom is formed between photoresist layer and substrate and is resisted
The method of reflectance coating, however, not only process costs are high for the above method, and formed after photoetching, an etching technics
Bottom antireflective coating, be only capable of forming a type of doped region in substrate, cause semiconductor devices formation process complicated
And cost is high.
Therefore, the present invention provides a kind of forming method of semiconductor devices, in first area, second area and the 3rd region
The first original mask layer is formed, and the first original mask layer has antireflection effect；In the first original mask layer of second area
Surface forms the first photoresist layer；Using the first photoresist as mask, etching forms the first mask layer positioned at second area；Formed
Cover the first photoresist layer of first area and the mask layer of part first；Using first photoresist layer and the first mask layer to cover
Film, the first doped region is formed in the 3rd area substrate；Form the 3rd photoetching of the 3rd region of covering and the mask layer of part first
Glue-line；Using the 3rd photoresist layer and the first mask layer as mask, the second doped region is formed in the substrate of first area.Present invention weight
Make use of the first mask layer with higher position accuracy to be formed again, while having saved process costs, formed have compared with
The first doped region and the second doped region of high position precision, improve the reliability and electric property of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 17 is the cross-sectional view for the semiconductor devices forming process that another embodiment of the present invention provides.
The semiconductor devices that the present invention is formed includes one or both of MOS transistor or fin formula field effect transistor,
The present embodiment does exemplary illustrated so that the semiconductor devices formed includes MOS transistor as an example.
It refer to Fig. 3, there is provided substrate 100, the substrate 100 include first area I, second area II and the 3rd region
III, and the first area I, second area II and the 3rd region III are kept apart by isolation structure 101.
The substrate 100 is Si substrates, Ge substrates, GeSi substrates or GaAs substrates；The surface of substrate 100 can be with shape
Into some epitaxial interface layers or strained layer to improve the electric property of semiconductor devices.In an embodiment of the present invention, the lining
Bottom 100 is Si substrates.
It should also be noted that, the first area I, second area II and the 3rd region III can be adjacent or interval,
Should not too it limit the scope of the invention.
The isolation structure 101 is used to isolate first area I, second area II and the 3rd region III, prevents adjacent having
Conducted between source region.The isolation structure 101 of the present embodiment is isolated using shallow trench, the filling material of the isolation structure 101
Expect that for insulating materials, the insulating materials can be the one or more in silica, silicon nitride, silicon oxynitride.
There is first grid structure, the second area II with the surface of substrate 100 of the first area I in the present embodiment
The surface of substrate 100 there is second grid structure, the surface of substrate 100 of the 3rd region III has the 3rd grid structure, after
Continuous the second doped region, the 3rd doped region and the first doped region being correspondingly formed is exemplary illustrated to be done exemplified by lightly doped district.
In other embodiments of the present invention, if first area substrate surface is formed without first grid structure, follow-up shape
Into the second doped region be threshold voltage adjustments area；Second area substrate surface is formed without second grid structure, then follow-up shape
Into the 3rd doped region be threshold voltage adjustments area；If the 3rd area substrate surface is formed without the 3rd grid structure, subsequently
The first doped region formed is threshold voltage adjustments area.
The first grid structure includes being located at first gate oxide 111 on the surface of first area I substrates 100 and is located at
The first gate electrode layer 112 on the surface of the first gate oxide 111.
The second grid structure includes the second gate oxide 121 and position positioned at the surface of second area II substrates 100
The second gate electrode layer 122 in the surface of the second gate oxide 121.
3rd grid structure includes the 3rd gate oxide 131 and position positioned at the surface of the 3rd region III substrates 100
The 3rd gate electrode layer 132 in the surface of the 3rd gate oxide 113.
The material of first gate oxide 111, the second gate oxide 121 or the 3rd gate oxide 131 be silica or
High K medium material, the material of the first gate electrode layer 112, the second gate electrode layer 122 or the 3rd gate oxide 132 is polycrystalline
Silicon, the polysilicon or metal of doping.
In order to protect first grid structure, second grid structure and the 3rd gate structure sidewall not to be broken by subsequent technique
It is bad, in first grid structure, second grid structure and the 3rd gate structure sidewall formed with side wall 102.
The side wall 102 is single layer structure or sandwich construction, and the material of the side wall 102 is silica, silicon nitride or nitrogen
Silica.In the present embodiment, the side wall 102 is the laminated construction of silicon oxide layer and silicon nitride layer.
Fig. 4 is refer to, forms the first original mask layer for being covered in first area I, second area II and the 3rd region II,
The first original mask layer has the function that antireflection.
In the present embodiment, because the surface of substrate 100 is formed with first grid structure, second grid structure and the 3rd grid knot
Structure, the first original mask layer are also covered in first grid structure 110, second grid knot in addition to the surface of substrate 100 is covered in
Structure 120 and the surface of the 3rd grid structure 130.
The first original mask layer has antireflection effect so that the subsequently formed in the first original mask layer surface
The pattern of one photoresist layer and position are consistent with the target set；Also, the first original mask layer should also meet following condition：
The technique of follow-up removal photoresist layer is small to the etch rate of the first original mask layer material, ensures that subsequent etching first is initially covered
The pattern that film layer forms the first mask layer is not influenceed by photoresist layer technique is removed.
In the present embodiment, the first original mask layer is double-decker, and the first original mask layer includes the first initial lower mask
Layer 103 and the first initial upper mask layer 104 positioned at the first initial lower surface of mask layer 103.First initial lower mask layer
103 material is cross-linking type (cross-linked type) material, and the material of the first initial upper mask layer 104 is siliceous material
Material.
The material of first initial lower mask layer 103 is the Spun-on carbon (SOC of cross-linking type：Spin on Carbon, first is initial
The material of upper mask layer 104 is spin coating silicon (SOG：Spin on Glass) or siliceous bottom anti-reflective material (Si-BARC).
In the present embodiment, the material of the first initial lower mask layer 103 is Spun-on carbon, and thickness is 1000 angstroms to 5000 angstroms, the
The material of one initial lower mask layer 104 is spin coating silicon, and thickness is 200 angstroms to 2000 angstroms.
Fig. 5 is refer to, the second initial lithographic glue-line is formed in the first original mask layer surface；It is initial to described second
Photoresist layer is exposed development treatment, forms the second photoresist layer 105 positioned at second area II.
Second photoresist layer 105 forms the mask of the first mask layer, therefore, the second photoresist layer as subsequent etching
105 position precision and pattern determines position and the pattern for the first mask layer being subsequently formed.
Because the first original mask layer has the function that antireflection, processing is being exposed to the first initial lithographic glue-line
When, it is suppressed that light transmitting occurs in the first initial lithographic glue-line bottom, prevent due to unnecessary light reflection and caused by not
Desired region has carried out exposure-processed, and therefore, the position precision for the second photoresist layer 105 that the present embodiment is formed is high and has
There is good pattern, form second photoresist layer 105 consistent with predeterminated target.
In the present embodiment, the second photoresist layer 105 of formation is located at second area II and is located only within second area II, with
Beneficial to being subsequently formed the first mask layer for being located only within second area II.
Also, in order to further improve the position precision and pattern of the second photoresist layer 105 of formation, it can use more first
The photoetching process for the lithographic process entered forms second photoresist layer 105, for example, the photoetching process using 193nm/248nm.
Fig. 6 is refer to, with second photoresist layer 105 (refer to Fig. 5) for mask, etches the first original mask layer,
Form the first mask layer for being covered in the surface of second area II substrates 100 and the surface of isolation structure 101, the side of the first mask layer
Wall is located at the surface of isolation structure 101, and first mask layer has antireflection effect.
First mask layer is formed on the basis of the first original mask layer, and the border of first mask layer is located at
The surface of second area II isolation structures 101.In the present embodiment, the first mask layer is double-decker, and the first mask layer includes first
Lower mask layer 113 and the mask layer 114 on the first of first time mask layer surface.
The material of first time mask layer 113 is the Spun-on carbon of cross-linking type, and the material of mask layer 114 is spin coating on first
Silicon or siliceous bottom anti-reflective material；The thickness of first time mask layer 113 is 1000 angstroms to 5000 angstroms, mask layer on first
114 thickness is 200 angstroms to 2000 angstroms.
In the present embodiment, the thinner thickness of mask layer 114 on first, therefore, even if the material of mask layer 114 is on first
Therefore bottom anti-reflective material, has saved work to a certain extent, it is necessary to the thinner thickness of the bottom anti-reflective material layer formed
Skill cost；And in the prior art, if forming bottom anti-reflection layer, the thickness of bottom antireflective coating before photoresist layer formation
Thickness of the degree more than grid structure so that the process costs for forming semiconductor devices are very high.
From Such analysis, the position precision of the second photoresist layer 105 is high and has good pattern, therefore with
Second photoresist layer 105 is that the first mask layer that mask etching is formed also has the characteristic that position precision is high, pattern is good, shape
Into the first mask layer be completely covered in the surface of second area II substrates 100, and first area I and the 3rd region III not by
First mask layer covers.
Mask layer 114 not only has antireflection effect on first, also acts as first time mask layer 113 of protection and is not destroyed
Effect；Mask layer 114 protects first time mask layer 113 not sustain damage on first, and due to the thickness of first time mask layer 113
Spend big more of thickness of mask layer 114 on than first, still can be by the if the pattern of first time mask layer 113 does not sustain damage
For one mask layer as the part mask for being subsequently formed the second doped region, the position for improving the second doped region being subsequently formed is accurate
Degree.
The first original mask layer is etched using dry etch process.It should be noted that at the beginning of etching described first
After beginning mask layer forms the first mask layer, etching removes the second photoresist layer 105 positioned at second area II.
Fig. 7 is refer to, forms the first photoetching positioned at the first area I surfaces and part the first mask layer surface
Glue-line 106, expose the part first mask layer surface adjacent with the 3rd region III.
A part of first photoresist layer 106 as the mask that the first doped region is subsequently formed in the 3rd region III.
The forming step of first photoresist layer 106 includes：Form covering first area I, second area II and the 3rd
Region III the first initial lithographic glue-line；Development treatment is exposed to the first initial lithographic glue-line, is formed and is located at first
Region I surfaces and the first photoresist layer 106 of part the first mask layer surface.
Because the position precision of first mask layer adjacent with the 3rd region III is high and has good pattern, therefore,
The present embodiment requires relatively low to the position precision of the first photoresist layer 106 of formation, and the first photoresist layer 106 is located at the firstth area
Domain I and part the first mask layer surface, the side wall of the first photoresist layer 106 are located at (first in wider width range
In mask layer side to the distance range of opposite side), it is low to be exposed the technological requirement of processing to the first initial lithographic glue-line, drop
The low technology difficulty of semiconductor devices.
From Such analysis, the region of the first doped region to be formed is accurately oriented by the first mask layer, therefore, the
The lithographic accuracy of two photoresist layers 105 (refer to Fig. 5) is higher than the lithographic accuracy of the first photoresist layer 106, and the present embodiment is to shape
Position precision into the first photoresist layer 106 requires relatively low, and the photoetching process of the lithographic process of lower end can be used to form institute
The first photoresist layer 106 is stated, for example, the photoetching process using 248nm/365nm；Photoetching is carried out using the lithographic process of lower end
Technique, reduce the process costs to form semiconductor devices.
Fig. 8 is refer to, using first photoresist layer 106 and the first mask layer exposed as mask, to the 3rd region
III substrate 100 carries out the first doping 107, forms the first doped region 108.
First doping 107 mask by：Position precision is high and pattern is good the first mask layer and accurate to position
Degree and pattern require that the first relatively low photoresist layer 106 collectively constitutes.
Because the position of the first mask layer of formation and pattern are consistent with sets target, the first mask layer is completely covered
Two regions and the 3rd region III is exposed, when carrying out the first doping 107, the first doping 107 is only to the 3rd region III substrates 100
It is doped, avoids and deficiency is adulterated to the 3rd region II substrates 100 or undesirable mix is caused to second area II substrates 100
It is miscellaneous, improve the reliability and electric property of semiconductor devices.
And in the prior art, directly form initial first photoresist in first area, second area and the 3rd region surface
Layer, development treatment is exposed to initial first photoresist layer, forms the first photoresist positioned at first area and second area
Layer；However, because in exposure-processed, light can reflect when passing through the interface between substrate and isolation structure, the reflected light
Undesirable exposure is caused to initial first photoresist layer so that the position of the first photoresist layer of formation and pattern are difficult to strictly
Control.Serious, cause by the second area that the first photoresist layer is completely covered should be partly exposed, to the 3rd area
Domain carries out also having carried out the second area exposed the first doping while the first doping, causes degraded performance or the mistake of device
Effect；Or causing the first photoresist layer to cover the region of part the 3rd, the region of part the 3rd covered by the first photoresist layer can not
The first doping is carried out, will also result in the degraded performance of device.
In the present embodiment, the technique of first doping 107 is ion implanting；Before the first doping 107 is carried out, the 3rd
For the surface of region II substrates 100 formed with the 3rd grid structure, the first doped region 108 of formation is lightly doped district.In other implementations
In example, before the first doping is carried out, when the 3rd area substrate surface does not form three grid structures, the first doped region of formation
For threshold voltage adjustments area.
It should be noted that the doped region that the present invention is formed removes lightly doped district or threshold voltage adjustments that the present embodiment provides
Outside the type in area, the doped region can also be the doped region of other regulation performance of semiconductor device, for example, in other implementations
In example, it is necessary to when multiple regions being carried out with different doping process formation doped regions respectively to adjust the performance of semiconductor devices,
Semiconductor devices can also be formed using the method for the formation semiconductor devices of the present embodiment offer.
After the first doped region 108 is formed, in addition to step：Remove the first photoresist layer 106.
It should be noted that the first mask layer is follow-up also using as the second doped region in formation first area I substrates 100
Mask, therefore, it should which select influences small technique to the first mask layer pattern removes the first photoresist layer 106.
In the present embodiment, the technique for removing the first photoresist layer 106 is：Cineration technics is carried out to the first photoresist layer 106,
The wet-etching technology of weak oxide is carried out after cineration technics.
In the technical process for removing the first photoresist layer 106, because the material of first time mask layer 113 is cross-linked structure
Material, the wet-etching technology of weak oxide is small to the etch rate of first time mask layer 113 with cross-linked structure；And
And positioned at mask layer 114 on the first of first time surface of mask layer 113 in the technical process for removing the first photoresist layer 106,
Also play first time pattern of mask layer 113 of protection is not influenceed by the technique of the first photoresist layer 106 is removed, and therefore, is being removed
After first photoresist layer 106, the first mask layer pattern is not affected by influence, and the first mask layer is still completely covered in the secondth area
Domain II.
As one embodiment, the technological parameter of the cineration technics is：Podzolic gas includes O2, O2Flow is 20sccm
To 200sccm, ashing temperature is 150 as little as 300 degree；The technological parameter of the wet-etching technology of the weak oxide is：Sulfuric acid
The mixed solution of solution and SC1 solution, and mixed solution temperature is less than 100 degree, wherein SC1 solution is the water of ammoniacal liquor and hydrogen peroxide
Solution.The temperature of mixed solution is to ensure the weak oxide of wet-etching technology, prevent wet-etching technology less than 100 degree
Oxidisability too strong first mask layer is had undesirable effect.
Fig. 9 is refer to, forms the 3rd light positioned at the 3rd region III surfaces and part the first mask layer surface
Photoresist layer 109, expose the part first mask layer surface adjacent with first area I.
3rd photoresist layer 109 and the mask layer of part first are subsequently as forming the in the 3rd region III substrates 100
The mask of two doped regions；It is right from the foregoing analysis to the first photoresist layer 106 (refer to Fig. 7), the 3rd photoresist layer 109
The precise requirements of position are relatively low, reduce the technology difficulty to form semiconductor devices, and reason will not be repeated here.
Because the border precise definition of the first mask layer has gone out the region of the second doped region to be formed, therefore, the second light
The lithographic accuracy of photoresist layer 105 (refer to Fig. 5) is higher than the lithographic accuracy of the 3rd photoresist layer 109, can use the light of lower end
The photoetching process for scribing journey forms the 3rd photoresist layer, for example, the photoetching process using 248nm/365nm；Using relatively low
The lithographic process at end carries out photoetching process, reduce further process costs.
Figure 10 is refer to, using the 3rd photoresist layer 109 and the first mask layer exposed as mask, to first area
I substrates 100 carry out the second doping 201, form the second doped region 202.
The technique of second doping 201 is ion implanting.In the present embodiment, before the second doping 201 is carried out, the
For the surface of one region I substrates 100 formed with first grid structure, second doped region 202 is lightly doped district.
In other embodiments, before the second doping is carried out, in first area, substrate surface does not form first grid knot
During structure, the second doped region is threshold voltage adjustments area.
Because the position precision of the first mask layer positioned at second area II is high and has good pattern, the first mask
Layer is completely covered second area II and exposes first area so that using the 3rd photoresist layer 109 and the first mask layer as mask
When carrying out the second doping 201, the first doping 201 is only carried out to first area I and forms the second doped region 202, improves second
The technique degree of accuracy of doping 201, so as to improve the reliability for the semiconductor devices to be formed and electric property.
And in the prior art, before the second doping is carried out to first area substrate, formed in second area and the 3rd region
Photoresist layer；Yet with the exposure process for forming photoresist layer, light occurs for the interface of substrate and isolation structure
Reflection, reflected light have carried out unnecessary exposure-processed to photoresist layer, and the position precision of the photoresist layer resulted in is low,
And then cause to cause the second doping to undesirable region or the second doping is not carried out to part first area.
In the present embodiment, the technique accuracy of the second doping 201 and the first 107 (refer to Fig. 8) of doping is high, only predetermined
The region for being doped technique is doped, and improves the reliability and electric property to form semiconductor devices.Also, improving
While first doping 107 and the second 201 accuracy of doping, extra photoetching, etching technics are not increased, merely through one of light
Carve, etching technics and the first mask layer formed, both the part of the first doped region 108 (refer to Fig. 8) of formation can be used as to cover
Film, it can also save processing step as the part mask for forming the second doped region 202, reduced to form semiconductor devices
Process costs.
Figure 11 is refer to, after the second doped region 202 is formed, in addition to step：Removing the 3rd photoresist layer 109 (please
With reference to figure 10) and the first mask layer of removal.
3rd photoresist layer 109 is removed using cineration technics.As one embodiment, the technique of the cineration technics
Parameter is：Podzolic gas is O2, O2Flow is 20sccm to 200sccm, and ashing temperature is 150 degree to 300 degree.
The technique for removing the first mask layer is：Mask layer 114 on first is removed using dry etch process；Thereafter using tool
The wet-etching technology for having strong oxidizing property removes first time mask layer 113.
The etching gas of the dry etch process are CxFyOr CxHyFz, specifically, the etching gas of dry etch process
Can be CF4、CH2F2Or CHF3；The etch liquids of the wet-etching technology of the strong oxidizing property are：Sulfuric acid solution, dioxygen are water-soluble
The mixed solution of liquid and SC1 solution, mixed solution temperature are higher than 100 degree, wherein, SC1 solution is water-soluble for ammoniacal liquor and hydrogen peroxide
Liquid.
In the wet-etching technology with strong oxidizing property, the carbon-carbon bond being crosslinked in first time material of mask layer 113 is broken
It is bad, so as to reach the purpose for removing first time mask layer 113；Also, the wet-etching technology with strong oxidizing property may be used also
To remove the first photoresist layer 109 of residual.
It should be noted that in the present embodiment, the first mask layer is adjacent with first area I and the 3rd region I, in the firstth area
The 3rd region 202 is formed in the I of domain, the first doped region 108 is formed in the 3rd region III, second is formed in first area I
Doped region 202；In other embodiments of the present invention, substrate is in addition to including first area, second area and the 3rd region, in addition to
The region of the to be formed doped region adjacent with the first mask layer, then first mask layer can also be used as form the doped region
The part mask of the technique in (lightly doped district or threshold voltage adjustments area).Further reuse only by a photoetching, carved
The first mask layer that etching technique is formed；Also, from the analysis to the first doped region and the second doped region, using the first mask
The position precision for the doped region that layer is formed as part mask layer is high, further improves the electric property of device.
Figure 12 is refer to, is formed on the first area I, second area II and the 3rd region the III surface of substrate 100 just
Begin the second original mask layer, and the second original mask layer has antireflection effect.
In the present embodiment, the second original mask layer include second initially lower mask layer 143, positioned at second it is initial under cover
The initial upper mask layer 144 of the second of the surface of film layer 143.
The material of the second original mask layer and effect refer to the material of the first original mask layer of the present embodiment offer
Material and effect, will not be repeated here.
Figure 13 is refer to, the 4th initial lithographic glue-line is formed in the second original mask layer surface；To the 4th initial light
Photoresist layer is exposed, development treatment, forms the 4th photoresist layer 145 positioned at first area I and second area II.
Second original mask layer has antireflection effect, prevents from, when being exposed the 4th initial lithographic glue-line, avoiding
Light reflects in the interface of substrate and isolation structure, therefore, the 4th photoresist layer and predeterminated target that the present embodiment is formed
Unanimously, the 4th photoresist layer that position precision is high and pattern is good is formd, first area I is completely covered in the 4th photoresist layer
With the 3rd region II, and second area II is completely revealed.
The forming step of 4th photoresist layer 145 and effect, which refer to the first photoresist layer of the present embodiment 105, (please join
Examine Fig. 5) forming step and effect, will not be repeated here.
Figure 14 is refer to, with the 4th photoresist layer 145 (refer to Figure 13) for mask, etches the second original mask
Layer, forms the second mask layer positioned at first area I and the 3rd region III, and second mask layer has antireflection effect.
In the present embodiment, the border of the second mask layer of the first area I is located at first area I isolation structure 101
Surface；The border of 3rd region III the second mask layer is located at the 3rd region III surface of isolation structure 101.
Mask (the 4th photoresist layer 145) position precision due to forming the second mask layer is high and pattern is good, therefore
The second mask layer for etching the formation of the second original mask layer also has high position precision and good pattern, the second mask layer
First area I and the 3rd region III is completely covered, and exposes second area II.
Second mask layer includes second time mask layer 153 and on the second of second time surface of mask layer 153
Mask layer 154.The material of second time mask layer 153 is the Spun-on carbon of cross-linking type, the material of mask layer 154 on described second
For spin coating silicon or siliceous bottom anti-reflective material.
The forming step of second mask layer refers to the forming step of the first mask layer of the present embodiment formation, herein
Repeat no more.
In the present embodiment, the material of second time mask layer 153 is the Spun-on carbon of cross-linking type, and thickness is 1000 angstroms to 5000
Angstrom, the material of mask layer 154 is spin coating silicon on second, and thickness is 200 angstroms to 2000 angstroms.
It should be noted that after the second original mask layer is etched, in addition to step：Etching removes the 4th photoresist layer
145。
Figure 15 is refer to, the 5th photoresist layer 146 positioned at part the second mask layer surface is formed, exposes and the secondth area
Part the second mask layer surface adjacent domain II.
Because the position precision of the second mask layer is high, the second mask layer, which has completely correctly defined, is subsequently formed the 3rd
The region of doped region, it is therefore, relatively low in requirement of the 5th photoresist layer 146 that the second mask layer surface is formed to photoetching process,
The second mask layer of covering part of the 5th photoresist layer 146 formed, exposes the second mask layer table adjacent with second area II
Face, reduce technology difficulty.
The forming step of 5th photoresist layer 146 and effect refer to the first photoresist layer 106 (refer to Fig. 8) and
The forming step of 3rd photoresist layer 109 (refer to Fig. 9) and effect, will not be repeated here.
It should be noted that in other embodiments of the present invention, substrate, which removes, includes first area, second area and the 3rd area
The region of overseas in addition to adjacent with the second mask layer doped region to be formed (lightly doped district or threshold voltage adjustments area), then
Second mask layer is also as the part mask for forming the doped region.
Figure 16 is refer to, using the 5th photoresist layer 146 and the second mask layer exposed as mask, to second area
II substrates 100 carry out the 3rd doping 147, form the 3rd doped region 148.
In the present embodiment, before the 3rd doping 147 is carried out, in second area II substrate surfaces formed with second grid knot
Structure, the 3rd doped region 148 are lightly doped district.
In other embodiments, before the 3rd doping is carried out, second grid knot is not formed in second area substrate surface
During structure, the 3rd doped region is threshold voltage adjustments area.
Figure 17 is refer to, removes the 5th photoresist layer 146 (refer to Figure 16) and the second mask layer.
5th photoresist layer 146 is removed using cineration technics, mask layer 154 on second is removed using dry etch process,
Thereafter second time mask layer 153 is removed using the wet-etching technology with strong oxidizing property.Using the wet etching of strong oxidizing property
Technique removes the second mask layer.
As one embodiment, the technological parameter of the cineration technics is：Podzolic gas is O2, O2Flow be 20sccm extremely
200sccm, ashing temperature are 150 degree to 300 degree；The etching gas of the dry etch process are CxFyOr CxHyFz, specifically,
The etching gas of the dry etch process are CF4、CH2F2Or CHF3；The etch liquids of the wet-etching technology of strong oxidizing property
For：The mixed solution of sulfuric acid and hydrogen peroxide, solution temperature are higher than 100 degree.
Under the wet etching effect of strong oxidizing property, the carbon-carbon bond being crosslinked in the material of second time mask layer 153 is interrupted,
Second time mask layer 153 is etched by wet-etching technology and removed.
It should be noted that in other embodiments of the present invention, substrate, which removes, includes first area, second area and the 3rd area
When domain also includes other regions, if the second mask layer of first area substrate surface in addition to adjacent with second area, is gone back and other
The substrate area in lightly doped district or threshold voltage adjustments area to be formed is adjacent, then before the second mask layer for removing first area,
Can also be using the second mask layer as above-mentioned lightly doped district to be formed or the part mask of the doping process in threshold voltage adjustments area；
If second mask layer on the 3rd area substrate surface in addition to adjacent with second area, also with other lightly doped districts or threshold value to be formed
The substrate area in voltage-regulation area is adjacent, then before the second mask layer for removing the 3rd region, can also make the second mask layer
For above-mentioned lightly doped district to be formed or the part mask of the doping process in threshold voltage adjustments area.
To sum up, technical scheme provided by the invention has advantages below：
First, the first original mask layer is formed on first area, second area and the 3rd area substrate surface, due to first
Original mask layer has antireflection effect, reduces the unnecessary light reflection occurred during exposure-processed so that in second area
The position precision for the first photoresist layer that first original mask layer surface is formed is high and has good pattern, further such that
The position precision of the first mask layer formed using the first photoresist layer as mask layer is high, and the secondth area is completely covered in the second mask layer
Domain and only cover second area；Subsequently when forming the first photoresist layer to the first doping process of the 3rd region progress, institute
Part the first mask layer surface can be exposed by stating the first photoresist layer, reduce the technological requirement to forming the first photoresist layer,
Reduce technology difficulty, and the first photoresist layer and high the first mask layer the covering as the first doping process of position precision
Film, the position precision of the mask is high, avoids the occurrence of that second area is partly exposed or the 3rd region is partially covered
Situation, improve the reliability and electric property of the semiconductor devices to be formed.
Secondly, first mask layer is also used as carrying out first area the part mask of the second doping, is reducing
While carrying out the 3rd photoresist layer formation process difficulty of the second doping, reuse using a photoetching and etching i.e. shape
Into the first mask layer, in the case where not increasing additional technology cost, the position for improving the second doped region to be formed is accurate
Degree.
Again, the double-decker including mask layer on first time mask layer and first is formd as the first mask layer, and
The material of first time mask layer is the Spun-on carbon of cross-linking type, and mask layer not only has antireflection effect on first, also acts as protection
First time mask layer be not by the effect destroyed；Mask layer protects first time mask layer not sustain damage on first, and due to the
Once (1000 angstroms to 5000 angstroms) of the thickness of mask layer than first on mask layer big more of thickness (200 angstroms to 2000 angstroms), the
If once the pattern of mask layer does not sustain damage, still can using the first mask layer as the part mask for forming the second doped region,
In the case where not increasing process costs, the reliability and electric property of semiconductor devices are further increased.
Finally, the substrate is in addition to including first area, second area and the 3rd region, in addition to the first mask layer phase
During the region of adjacent doped region to be formed, first mask layer can also be covered as the part for the technique for forming the doped region
Film so that the position precision of the doped region of formation is high, the reliability and electrical property of the formation semiconductor devices further improved
Can, and reduce further process costs.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Substrate is provided, the substrate includes first area, second area and the 3rd region being arranged in order, and firstth area Domain, second area and the 3rd region are kept apart by isolation structure；Form the substrate surface for being covered in second area and first mask layer on isolation structure surface, the side wall of the first mask layer Positioned at second area isolation structure surface, and first mask layer has antireflection effect；The first photoresist layer positioned at the first area surface and part the first mask layer surface is formed, is exposed and the Adjacent part the first mask layer surface in three regions；Using first photoresist layer and the first mask layer exposed as mask, the substrate progress first to the 3rd region is mixed It is miscellaneous, form the first doped region；The 3rd photoresist layer positioned at the 3rd region surface and part the first mask layer surface is formed, is exposed and the Adjacent part the first mask layer surface in one region；Using the 3rd photoresist layer and the first mask layer exposed as mask, the substrate progress second to first area is mixed It is miscellaneous, form the second doped region.
- 2. the forming method of semiconductor devices according to claim 1, it is characterised in that the forming step of the first mask layer Including：The the first original mask layer for being covered in first area, second area and the 3rd region surface is formed, described first initially covers Film layer has antireflection effect；Form the second photoresist layer of the first original mask layer surface positioned at second area；With described Second photoresist layer is mask, etches the first original mask layer, formed the substrate surface that is covered in second area and every From the first mask layer of body structure surface.
- 3. the forming method of semiconductor devices according to claim 2, it is characterised in that the light of second photoresist layer Precision is carved higher than the first photoresist layer and the lithographic accuracy of the 3rd photoresist layer.
- 4. the forming method of semiconductor devices according to claim 1, it is characterised in that the filling material of the isolation structure Expect that for insulating materials, insulating materials be silica.
- 5. the forming method of semiconductor devices according to claim 1, it is characterised in that the border of first mask layer Positioned at isolation structure surface.
- 6. the forming method of semiconductor devices according to claim 1, it is characterised in that first mask layer is bilayer Structure, the first mask layer include first time mask layer and the mask layer on the first of first time mask layer surface.
- 7. the forming method of semiconductor devices according to claim 6, it is characterised in that the material of first time mask layer Expect the Spun-on carbon for cross-linking type, the material of mask layer is spin coating silicon or siliceous bottom anti-reflective material on described first.
- 8. the forming method of semiconductor devices according to claim 6, it is characterised in that the thickness of first time mask layer Spend for 1000 angstroms to 5000 angstroms, the thickness of mask layer is 200 angstroms to 2000 angstroms on described first.
- 9. the forming method of semiconductor devices according to claim 2, it is characterised in that initially covered in etching described first After film layer forms the first mask layer, etching removes the second photoresist layer.
- 10. the forming method of semiconductor devices according to claim 1, it is characterised in that the substrate, which removes, includes first Outside region, second area and the 3rd region, include the region of the to be formed doped region adjacent with the first mask layer；Described first Mask layer is the part mask for the technique to form the doped region.
- 11. the forming method of semiconductor devices according to claim 1, it is characterised in that formed the first doped region it Afterwards, in addition to step：Remove first photoresist layer.
- 12. the forming method of semiconductor devices according to claim 11, it is characterised in that remove the first photoresist layer Technique is：Cineration technics is carried out to the first photoresist layer, the wet-etching technology of weak oxide is carried out after cineration technics.
- 13. the forming method of semiconductor devices according to claim 12, it is characterised in that the wet method of the weak oxide The etch liquids of etching technics are：The mixed solution of sulfuric acid solution and SC1 solution, and mixed solution temperature is less than 100 degree, its In, SC1 solution is the aqueous solution of ammoniacal liquor and hydrogen peroxide.
- 14. the forming method of semiconductor devices according to claim 1, it is characterised in that formed the second doped region it Afterwards, in addition to step：Remove the 3rd photoresist layer and the first mask layer；Formation is located at first area and the 3rd region The second mask layer, and second mask layer has antireflection effect；Form the positioned at part the second mask layer surface the 5th Photoresist layer, expose the part second mask layer surface adjacent with second area；With the 5th photoresist layer and expose The second mask layer be mask, to second area substrate carry out the 3rd doping, formed the 3rd doped region；Remove the 5th photoetching Glue-line.
- 15. the forming method of semiconductor devices according to claim 6, it is characterised in that remove the work of the first mask layer Skill is：Mask layer on described first is removed using dry etch process；Removed using the wet-etching technology with strong oxidizing property First time mask layer.
- 16. the forming method of semiconductor devices according to claim 15, it is characterised in that the dry etch process Etching gas are CxFyOr CxHyFz；The etch liquids of the wet-etching technology of the strong oxidizing property are：Sulfuric acid solution, dioxygen are water-soluble The mixed solution of liquid and SC1 solution, mixed solution temperature are higher than 100 degree, wherein, SC1 solution is water-soluble for ammoniacal liquor and hydrogen peroxide Liquid.
- 17. the forming method of semiconductor devices according to claim 14, it is characterised in that the shape of second mask layer Include into step：The second original mask layer is formed in first area, second area and the 3rd region；In second original mask Layer surface forms the 4th initial lithographic glue-line；The 4th initial lithographic glue-line is exposed, development treatment, formed positioned at the One region and the 4th photoresist layer in the 3rd region；Using the 4th photoresist layer as mask, the second original mask layer, shape are etched Into the second mask layer positioned at first area and the 3rd region, and during the second original mask layer is etched, etching Remove the 4th photoresist layer.
- 18. the forming method of semiconductor devices according to claim 17, it is characterised in that the substrate, which removes, includes first Outside region, second area and the 3rd region, include the region of the to be formed doped region adjacent with the second mask layer；Described second Mask layer is the part mask for the technique to form the doped region.
- 19. the forming method of semiconductor devices according to claim 1, it is characterised in that first doping and second The technique of doping is ion implanting.
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| US6506653B1 (en) * | 2000-03-13 | 2003-01-14 | International Business Machines Corporation | Method using disposable and permanent films for diffusion and implant doping |
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| US6897095B1 (en) * | 2004-05-12 | 2005-05-24 | Freescale Semiconductor, Inc. | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode |
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