CN104796639A - Pixel combination circuit in reading circuit and pixel combination implementation method of pixel combination circuit - Google Patents
Pixel combination circuit in reading circuit and pixel combination implementation method of pixel combination circuit Download PDFInfo
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Abstract
The invention relates to a pixel combination circuit in a reading circuit and a pixel combination implementation method of the pixel combination circuit. Control is achieved by setting a third switch, an eighth switch and a ninth switch, when the three switches are on, the charges of a first capacitor and a second capacitor, a third capacitor and a fourth capacitor, and a fifth capacitor and a sixth capacitor are averaged, that is to say two lines of input/output signals are averaged, signal average values are output by setting an output control switch, and pixel combination purpose is achieved. When input pixel combination technology is used to average the charges of the sampling capacitors, sampling capacitance is doubled, so that the pixel combination circuit tends to use output pixel combination which does not introduce extra capacitance; due to the fact that output sampling capacitance is large, influence of small capacitor mismatch on output after averaging can be neglected, and the combination does not influence final output precision.
Description
Technical field
The invention belongs to field of image sensors, be specifically related to the pixel consolidation circuit in a kind of reading circuit and pixel merging implementation method thereof.
Background technology
Solid state image sensor is mainly divided into CCD (Charge-coupled Device) and CMOS (Complementary Metal-Oxide semiconductor) two kinds according to the difference of element, its function presents more change along with the change of applied environment, the object that pixel merges is exactly on the basis reducing spatial resolution, strengthen photo-detector to the susceptibility of light, reduce data processing amount, improve data processing speed, reduce system power dissipation.The mode realizing pixel merging can be divided into two large classes according to the difference of implementation: pixel physically merges and sub-sampling technology.Sub-sampling technology is carried out interlacing by sequencing control and is read pel data partly every row, thus improves the frame frequency of transducer, and reduces data volume; And merge the frame frequency that can not only promote transducer at pixel physically and reduce data volume, the sensitivity of transducer under subdued light conditions can also be promoted and the dynamic range of extension sensor.
The meaning realizing pixel pooling function is mainly reflected in these aspects following: to the lifting in the sensitivity of subdued light conditions lower sensor, the expansion to dynamic range of sensor and on the basis ensureing output image quality to the optimization of frame frequency and data volume, reduce system power dissipation.
But pixel physics merges also existing defects, 2 × 1 electric charge consolidation circuit schematic diagrames in pixel as shown in Figure 3, this pixel merges implementation method by realizing being averaged to two row photogenerated charges in pixel cell, so not only can reduce pixel fill factor, curve factor and can affect pixel alignment export the amplitude of oscillation, FD point electric capacity is remarkable by technogenic influence, it is average that amalgamation result is difficult to reach high accuracy, merges clock feedthrough that switch introduces and charge injection also cannot be eliminated the contribution of noise simultaneously.
Summary of the invention
The object of the invention is to overcome the shortcoming existed in above-mentioned prior art, provide the pixel consolidation circuit in a kind of reading circuit and pixel thereof to merge implementation method, there is the advantage that amalgamation result precision is high.
For achieving the above object, the present invention by the following technical solutions: comprise the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, the 7th switch, the 8th switch, the 9th switch, the first treatment circuit, the second treatment circuit, the first buffer, the second buffer, the 3rd buffer, the 4th buffer;
The input of described first switch and second switch is connected to arbitrary neighborhood two row pixel signal output part respectively; The output of the first switch and second switch is connected to the input of the first electric capacity and the second electric capacity respectively;
The equal ground connection of output of described first electric capacity and the second electric capacity or fixed level;
Described first treatment circuit input termination first electric capacity, output is connected to the 4th switch in parallel and the 6th switch respectively;
Described second treatment circuit input termination second electric capacity, output is connected to the 5th switch in parallel and the 7th switch respectively;
Described 3rd switch ends connects the input of the first electric capacity and the second electric capacity respectively;
The output of described 4th switch and the 5th switch is connected to the input of the 3rd electric capacity and the 4th electric capacity respectively;
The output of described 6th switch and the 7th switch is connected to the input of the 5th electric capacity and the 6th electric capacity respectively;
Described 8th switch ends is connected to the input of the 3rd electric capacity and the 4th electric capacity respectively;
Described 9th switch ends is connected to the input of the 5th electric capacity and the 6th electric capacity respectively;
The equal ground connection of output of described 3rd electric capacity and the 4th electric capacity or fixed level;
The input of described first buffer and the second buffer is connected to the two ends of the 8th switch respectively;
The input of described 3rd buffer and the 4th buffer is connected to the two ends of the 9th switch respectively;
The output of described first buffer and the 3rd buffer all exports reset voltage signal;
The equal photosignal of output of described second buffer and the 4th buffer.
The first described electric capacity is identical with the capacitance of the second electric capacity.
The capacitance of the 3rd described electric capacity, the 4th electric capacity, the 5th electric capacity and the 6th electric capacity is all equal.
The first described buffer, the second buffer, the 3rd buffer and the 4th buffer are the operational amplifier of same structure.
Be provided with correlated-double-sampling, programmable gain amplifier and buffer function module in the first described treatment circuit, the second treatment circuit, and two treatment circuit structures are identical.
The pixel of the pixel consolidation circuit in reading circuit merges an implementation method, comprises the following steps:
1) read pixel alignment output signal and do the merging of input pixel: closed first switch and second switch, 3rd switch disconnects until signal-obtaining signal sampling completes, rear disconnection first switch and second switch, closed 3rd switch makes the charge value on the first electric capacity of the 3rd switch control rule and the second electric capacity average, thus by Signal transmissions to the first treatment circuit and the second treatment circuit;
2) export sampling, merging treatment is done to double sampling signal: signal is exporting after the first treatment circuit and the second treatment circuit, disconnect the 4th switch, the 5th switch, the 6th switch and the 7th switch, make Signal transmissions to the 8th closed switch and the 9th switch, thus make the 3rd electric capacity and the 4th capacitor charge value average, 5th electric capacity and the 6th capacitor charge value on average, obtain reset/photosignal mean value that two row export;
3) combined signal is exported: reset/photosignal mean value that two row obtained export inputs the first buffer, the second buffer, the 3rd buffer and the 4th buffer respectively, the overall situation/flowing water the signal obtained sampling after first buffer, the second buffer, the 3rd buffer and the 4th buffer process reads, and four bufferings export reset voltage signal and photosignal respectively.
The modes that described four bufferings export reset voltage signal and photosignal are respectively: when the output of the first buffer and the 3rd buffer all exports reset voltage signal; The output output photoelectric signal of the second buffer and the 4th buffer;
When the output of the first buffer and the second buffer all exports reset voltage signal; The output output photoelectric signal of the 3rd buffer and the 4th buffer.
The present invention has following beneficial effect: prior art of comparing, the present invention controls by arranging the 3rd switch, the 8th switch and the 9th switch, when three switches close, can make the first electric capacity and the second electric capacity, the 3rd electric capacity and the 4th electric capacity, the 5th electric capacity and the 6th electric capacity electric charge average, thus make two row input/output signals do average treatment, by arranging output control switch, output signal mean value, the object of pixel merging that Here it is.Input pixel folding is adopted to do on average to the electric charge on sampling capacitance, make capacitance double like this, export pixel merging so be more prone to adopt, it can not introduce extra capacitance, comparatively large owing to exporting sampling capacitance value, the chip area outside meeting occupying volume.Comparatively speaking, export pixel merging and do not have the problems referred to above, simultaneously, answer subordinate's treatment circuit requirement, export sampling capacitance value comparatively large (pF), merge some FD electric capacity (fF) relative to less pixel inside, less capacitance mismatch can be ignored the output impact after average, thus improves final output accuracy.This device is applicable to spread and use.
The technology of the present invention method can complete physics pixel and merge in reading circuit, design is merged compared to pixel inside, pixel fill factor, curve factor will be caused to reduce because of insertion switch, also can not expire due to FD point the amplitude of oscillation that trap capabilities limits affects the output of pixel alignment, meanwhile, relative to pixel, reading circuit area has higher degree of regulation, technique is also more ripe, and the clock feedthrough that switch is introduced and charge injection also can be eliminated by additive method in reading circuit.
Accompanying drawing explanation
Fig. 1 is the pixel combinatorial construction schematic diagram that imageing sensor of the present invention reads in circuit;
Fig. 2 is the structural representation that imageing sensor pixel of the present invention inside merges;
Fig. 3 is that reading circuit pixel of the present invention merges sequencing control schematic diagram;
Fig. 4 is that pixel of the present invention exports the non-combinatorial construction schematic diagram of alignment;
Fig. 5 is that pixel of the present invention exports alignment and to power on pressing structural representation;
Fig. 6 is the PGA/CDS electrical block diagram of band pixel pooling function of the present invention;
Fig. 7 is that pixel of the present invention merges output effect figure.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
See Fig. 1-7, the present invention includes the first K switch 1, second switch K2, the 3rd K switch 3, the 4th K switch 4, the 5th K switch 5, the 6th K switch 6, the 7th K switch 7, the 8th K switch 8, the 9th K switch 9, first treatment circuit A1, the second treatment circuit A2, the first buffer B1, the second buffer B2, the 3rd buffer B3, the 4th buffer B4; The input of the first K switch 1 and second switch K2 is connected to arbitrary neighborhood two row pixel signal output part respectively; The output of the first K switch 1 and second switch K2 is connected to the input of the first electric capacity C1 and the second electric capacity C2 respectively; The equal ground connection of output of the first electric capacity C1 and the second electric capacity C2 or fixed level; First treatment circuit A1 inputs termination first electric capacity C1, and output is connected to the 4th K switch 4 in parallel and the 6th K switch 6 respectively; Second treatment circuit A2 inputs termination second electric capacity C2, and output is connected to the 5th K switch 5 in parallel and the 7th K switch 7 respectively; 3rd K switch 3 two ends connect the input of the first electric capacity C1 and the second electric capacity C2 respectively; The output of the 4th K switch 4 and the 5th K switch 5 is connected to the input of the 3rd electric capacity C3 and the 4th electric capacity C4 respectively; The output of the 6th K switch 6 and the 7th K switch 7 is connected to the input of the 5th electric capacity C5 and the 6th electric capacity C6 respectively; 8th K switch 8 two ends are connected to the input of the 3rd electric capacity C3 and the 4th electric capacity C4 respectively; 9th K switch 9 two ends are connected to the input of the 5th electric capacity C5 and the 6th electric capacity C6 respectively; The equal ground connection of output of the 3rd electric capacity C3 and the 4th electric capacity C4 or fixed level; The input of the first buffer B1 and the second buffer B2 is connected to the two ends of the 8th K switch 8 respectively; The input of the 3rd buffer B3 and the 4th buffer B4 is connected to the two ends of the 9th K switch 9 respectively; The output of the first buffer B1 and the 3rd buffer B3 all exports reset voltage signal; The equal photosignal of output of the second buffer B2 and the 4th buffer B4.First electric capacity C1 is identical with the capacitance of the second electric capacity C2.The capacitance of the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 and the 6th electric capacity C6 is all equal.First buffer B1, the second buffer B2, the 3rd buffer B3 and the 4th buffer B4 are the operational amplifier of same structure, be provided with correlated-double-sampling, programmable gain amplifier and buffer function module in first treatment circuit A1, the second treatment circuit A2, and two treatment circuit structures are identical.
The pixel of the pixel consolidation circuit in reading circuit merges an implementation method, comprises the following steps:
1) read pixel alignment output signal and do the merging of input pixel: closed first K switch 1 and second switch K2,3rd K switch 3 disconnects until signal-obtaining signal sampling completes, rear disconnection first K switch 1 and second switch K2, charge value on the first electric capacity C1 that closed 3rd K switch 3 makes the 3rd K switch 3 control and the second electric capacity C2 is average, thus by Signal transmissions to the first treatment circuit A1 and the second treatment circuit A2;
2) export sampling, merging treatment is done to double sampling signal: signal is exporting after the first treatment circuit A1 and the second treatment circuit A2, disconnect the 4th K switch 4, the 5th K switch 5, the 6th K switch 6 and the 7th K switch 7, make Signal transmissions to the 8th closed K switch 8 and the 9th K switch 9, thus make the 3rd electric capacity C3 and the 4th electric capacity C4 charge value average, 5th electric capacity C5 and the 6th electric capacity C6 charge value on average, obtain reset/photosignal mean value that two row export;
3) combined signal is exported: reset/photosignal mean value that two row obtained export inputs the first buffer B1, the second buffer B2, the 3rd buffer B3 and the 4th buffer B4 respectively, the overall situation/flowing water the signal obtained sampling after first buffer B1, the second buffer B2, the 3rd buffer B3 and the 4th buffer B4 process reads, and four bufferings export reset voltage signal and photosignal respectively.
When the output of the first buffer B1 and the 3rd buffer B3 all exports reset voltage signal; The output output photoelectric signal of the second buffer B2 and the 4th buffer B4;
When the output of the first buffer B1 and the second buffer B2 all exports reset voltage signal; The output output photoelectric signal of the 3rd buffer B3 and the 4th buffer B4.
Based on the pixel combinatorial construction in imageing sensor reading circuit of the present invention as shown in Figure 1, pixel merges Control timing sequence as shown in Figure 2, Col (x) and Col (x+1) is that the signal of adjacent two row exports, when carrying out read operation to the signal of the first row, first K switch 1, second switch K2 closes, the upper reset signal exported of Col (x) and Col (x+1) is stored in the first electric capacity C1 respectively, on second electric capacity C2, reset signal afterwards on column average the 3rd K switch 3 closed pair first electric capacity C1 and the second electric capacity C2 is averaged, 4th K switch 4, voltage signal after 5th K5 closed pair is average carries out sampling and deposits and is stored in the 3rd electric capacity C3 respectively, on 4th electric capacity C4.After completing the sampling to reset signal, consistent with the sampling process of reset signal to the sampling process of the photosignal on Col (x) and Col (x+1) row, be close post-sampling at the 6th K switch 6, the 7th K7 and be stored in respectively on the 5th electric capacity C5, the 6th electric capacity C6.After the sampling completing reset signal and the photosignal that Col (x) row and Col (x+1) are arranged, 8th K switch 8, the 9th K switch 9 close, respectively the reset that Col (x) arranges and Col (x+1) arranges, picture signal are averaged, read in follow-up signal processing circuit the voltage signal after average on the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6 afterwards, the voltage signal that this completes on alignment is average.
As shown in Figure 3, figure comprises four photodiodes adjacent in row, column and their transfer tubes (M1a, M1b, M1c, M1d) corresponding respectively to 2 × 1 electric charge consolidation circuit schematic diagrames in pixel.Wherein upper two the adjacent pixels of row share a set of reset transistor M2 (M2 '), source follower M3 (M3 ') and capablely select switch M4 (M4 '), four pixels merging have two FD points, two pixels on same row share one, FD and FD ' as shown in Figure 3.Can find out, pixel merging can impact the electric capacity of FD point.Be illustrated in figure 4 circuit of the present invention and export principle schematic alignment doing voltage signal merging, six control switchs in figure complete the switching between single pixel output mode and pixel merging output mode, wherein Binning circuit completes and exports the average of data to pixel, wherein have single pixel output mode of the circuit of pixel pooling function as shown in Figure 4, pixel merges output mode as shown in Figure 5.
When needing single pixel signal to export, two Nbin switches close, and Bin switch disconnects, and picture signal directly outputs to the signal processing circuit of next stage without Binning circuit, as shown in Figure 4.When needing pixel to merge to export, as shown in Figure 5, Nbin switch disconnects, and Bin switch closes, the picture signal that two pixels adjacent on row export through Binning circuit average after output to the signal processing circuit of next stage again.
Below for imageing sensor reads the concrete enforcement detailed annotation of pixel consolidation circuit in circuit, as shown in Figure 6, what the first treatment circuit A1 herein and the second treatment circuit A2 adopted is that imageing sensor reads programmable gain amplifier (PGA)/correlated-double-sampling (CDS) functional module common in circuit.The merging of row reading circuit is exactly the mean value in order to obtain two column signals, that is:
Wherein, K is the multiplication factor of programmable gain amplifier, (V
rst < n >-V
int < n >) be the light signals of the n-th row through black-level correction, its value is (V
rst, active < n >-V
int, active < n >)-(V
rst, dark < n >-V
int, dark < n >).Removed Bin signal, other Control timing sequence and non-merging patterns just the same.First consider the positive input of PGA/CDS, before sampling reset signal, the right polar plate voltage of the first electric capacity C1 is Vcm, and before S1 trailing edge arrives, the left polar plate voltage of the first electric capacity C1 is respectively V
rst, active < n >and V
rst, active < n+1 >.Because S2 is now high, operational amplifier is connect as negative feedback type, and making the right polar plate voltage of the second electric capacity C2 is also Vcm, and the electric charge now the first electric capacity C1 and the second electric capacity C2 stored is respectively [(V
rst, active < n >-V
cm)+(V
rst, active < n+1 >-V
cm)] C1 and 0.When TX rising edge arrives, S1 becomes ground, and M1 turns off, now S2 is still high, and operational amplifier is still connect as negative feedback type, and the right polar plate voltage of the second electric capacity C2 is still Vcm, before S1 rising edge arrives, the left polar plate voltage of the first electric capacity C1 is the output voltage (V after pixel integration
int, active < n >-V
cm) and (V
int, active < n+1 >-V
cm), suppose that now the right polar plate voltage of the first electric capacity C1 is V
x, try to please value C1=C2, can obtain V according to principle of charge conservation
xmagnitude of voltage, now circuit completes PGA/CDS function, afterwards, Bin signal participates in circuit working, and completed into column circuits pooling function, its output valve is the averages of two row PGA/CDS before Bin signal is enable, complete pixel pooling function, the output after merging as shown in Figure 7.In Fig. 7, abscissa is exactly the time that time domain exports, and ordinate is alignment output voltage values.Given here is the partial enlarged drawing of Vrst and Vsig merging process in a certain cycle.
Solid line is the first row output voltage 2.7V for merging, and dotted line is secondary series voltage 2.1V, and both finally merge output 2.4V voltage.The merging time is probably 7ns.
Output pixel merging method in reading circuit, when alignment first time exports reset signal, first K switch 1 and second switch K2 close, 3rd K switch 3 does not participate in circuit working, after the first electric capacity C3 and the second electric capacity C2 has sampled, disconnect the first K switch 1 and second switch K2, first treatment circuit A1 and the second treatment circuit A2 now can process sampled signal under signal controlling, and the first described treatment circuit A1 and the second treatment circuit A2 can comprise the functional modules such as correlated-double-sampling, programmable gain amplifier and buffer.When first treatment circuit A1 and the second treatment circuit A2 works, the 4th K switch 4, the 5th K switch 5 close, and the 6th K switch 6, the 7th K switch 7 disconnect.By signal sampling on the 3rd electric capacity C3, the 4th electric capacity C4.Described first buffer B1, the second buffer B2, the 3rd buffer B3 and the 4th buffer B4 are after sampling completes, and namely K5 after disconnection the 4th K switch 4, the 5th switch, reads reset signal data.
When pixel alignment second time output photoelectric signal, first K switch 1 and second switch K2 close, 3rd K switch 3 does not participate in circuit working, after the first electric capacity C1 and the second electric capacity C2 has sampled, disconnect the first K switch 1 and second switch K2, first treatment circuit A1 and the second treatment circuit A2 now can process sampled signal under signal controlling, and the first described treatment circuit A1 and the second treatment circuit A2 can comprise the functional modules such as correlated-double-sampling, programmable gain amplifier and buffer.When first treatment circuit A1 and the second treatment circuit A2 works, the 6th K switch 6, the 7th K switch 7 close, and the 4th K switch 4, the 5th K switch 5 disconnect.By signal sampling on the 5th electric capacity C5, the 6th electric capacity C6.Described first buffer B1, the second buffer B2, the 3rd buffer B3 and the 4th buffer B4, after sampling completes, namely after disconnected 6th K switch 6, the 7th K switch 7, read photosignal data.
Two described row pixel consolidation circuits, comprise two kinds of multi-form merging modes: input pixel merges and exports pixel and merges.On this invention basis, can extend consolidation circuit to multiple row, participate in all electric capacity merged, its value must be identical, and its second current potential that end connects must be identical.
The first described treatment circuit A1 and the second treatment circuit A2, for the module of identical function, specifically can comprise the programmable gain amplifier, Buffer output etc. of correlated-double-sampling, programmable gain amplifier, band correlated-double-sampling, first treatment circuit A1 and second process A2 circuit all comprises two sampling capacitances, its sampling time sequence is closed by the 4th K switch 4, the 5th K switch 5,6th K switch 6, the 7th K switch 7 control, 4th K switch 4 has identical Control timing sequence with the 5th K switch 5, and the 6th K switch 6 and the 7th K switch 7 have identical Control timing sequence.
Described imageing sensor, as the pixel consolidation circuit in reading circuit, can do input to adjacent two row or multiple row pixel output signal and merge, and also can do to export to adjacent two row or multiple row pixel output signal to merge.Meanwhile, also two row or the merging of multiple row pixel can be carried out to odd column or even column.
CCD/CMOS imageing sensor, merging behavior is optional, and under the condition of not selection combining, image exports as inherently pixel.
Embodiment of the present invention are only exemplary, and the object that elaborates of carrying out is that the practitioner of suitable experience can be realized.Certainly, scheme is carried out to a large amount of amendments, variation and the adjustment of equivalence in fact, all should belong to spirit or covering scope that claim subsidiary in the present invention specifies.
Claims (7)
1. the pixel consolidation circuit in reading circuit, is characterized in that: comprise the first switch (K1), second switch (K2), the 3rd switch (K3), the 4th switch (K4), the 5th switch (K5), the 6th switch (K6), the 7th switch (K7), the 8th switch (K8), the 9th switch (K9), the first treatment circuit (A1), the second treatment circuit (A2), the first buffer (B1), the second buffer (B2), the 3rd buffer (B3), the 4th buffer (B4);
The input of described first switch (K1) and second switch (K2) is connected to arbitrary neighborhood two row pixel signal output part respectively; The output of the first switch (K1) and second switch (K2) is connected to the input of the first electric capacity (C1) and the second electric capacity (C2) respectively;
The equal ground connection of output of described first electric capacity (C1) and the second electric capacity (C2) or fixed level;
Described first treatment circuit (A1) inputs termination first electric capacity (C1), and output is connected to the 4th switch (K4) in parallel and the 6th switch (K6) respectively;
Described second treatment circuit (A2) inputs termination second electric capacity (C2), and output is connected to the 5th switch (K5) in parallel and the 7th switch (K7) respectively;
Described 3rd switch (K3) two ends connect the input of the first electric capacity (C1) and the second electric capacity (C2) respectively;
The output of described 4th switch (K4) and the 5th switch (K5) is connected to the input of the 3rd electric capacity (C3) and the 4th electric capacity (C4) respectively;
(output of K6 and the 7th switch (K7) is connected to the input of the 5th electric capacity (C5) and the 6th electric capacity (C6) to described 6th switch respectively;
Described 8th switch (K8) two ends are connected to the input of the 3rd electric capacity (C3) and the 4th electric capacity (C4) respectively;
Described 9th switch (K9) two ends are connected to the input of the 5th electric capacity (C5) and the 6th electric capacity (C6) respectively;
The equal ground connection of output of described 3rd electric capacity (C3) and the 4th electric capacity (C4) or fixed level;
The input of described first buffer (B1) and the second buffer (B2) is connected to the two ends of the 8th switch (K8) respectively;
The input of described 3rd buffer (B3) and the 4th buffer (B4) is connected to the two ends of the 9th switch (K9) respectively;
The output of described first buffer (B1) and the 3rd buffer (B3) all exports reset voltage signal;
The equal photosignal of output of described second buffer (B2) and the 4th buffer (B4).
2. the pixel consolidation circuit in a kind of reading circuit according to claim 1, is characterized in that: described the first electric capacity (C1) is identical with the capacitance of the second electric capacity (C2).
3. the pixel consolidation circuit in a kind of reading circuit according to claim 1, is characterized in that: the capacitance of the 3rd described electric capacity (C3), the 4th electric capacity (C4), the 5th electric capacity (C5) and the 6th electric capacity (C6) is all equal.
4. the pixel consolidation circuit in a kind of reading circuit according to claim 1, is characterized in that: the operational amplifier that described the first buffer (B1), the second buffer (B2), the 3rd buffer (B3) and the 4th buffer (B4) are same structure.
5. the pixel consolidation circuit in a kind of reading circuit according to claim 1, it is characterized in that: be provided with correlated-double-sampling, programmable gain amplifier and buffer function module in described the first treatment circuit (A1), the second treatment circuit (A2), and two treatment circuit structures are identical.
6. the pixel of the pixel consolidation circuit in the reading circuit according to claim 1-5 any one claim merges an implementation method, it is characterized in that: comprise the following steps:
1) read pixel alignment output signal and do the merging of input pixel: closed first switch (K1) and second switch (K2), 3rd switch (K3) disconnects until signal-obtaining signal sampling completes, rear disconnection first switch (K1) and second switch (K2), charge value on the first electric capacity (C1) that closed 3rd switch (K3) makes the 3rd switch (K3) control and the second electric capacity (C2) on average, thus by Signal transmissions to the first treatment circuit (A1) and the second treatment circuit (A2);
2) sampling is exported, merging treatment is done to double sampling signal: signal is exporting after the first treatment circuit (A1) and the second treatment circuit (A2), disconnect the 4th switch (K4), 5th switch (K5), 6th switch (K6) and the 7th switch (K7), make Signal transmissions to the 8th closed switch (K8) and the 9th switch (K9), thus make the 3rd electric capacity (C3) and the 4th electric capacity (C4) charge value average, 5th electric capacity (C5) is average with the 6th electric capacity (C6) charge value, obtain reset/photosignal mean value that two row export,
3) combined signal is exported: reset/photosignal mean value that two row obtained export inputs the first buffer (B1), the second buffer (B2), the 3rd buffer (B3) and the 4th buffer (B4) respectively, the overall situation/flowing water the signal obtained sampling after first buffer (B1), the second buffer (B2), the 3rd buffer (B3) and the process of the 4th buffer (B4) reads, and four bufferings export reset voltage signal and photosignal respectively.
7. the pixel of the pixel consolidation circuit in a kind of reading circuit according to claim 6 merges implementation method, it is characterized in that: the modes that four described bufferings export reset voltage signal and photosignal are respectively: when the output of the first buffer (B1) and the 3rd buffer (B3) all exports reset voltage signal; The output output photoelectric signal of the second buffer (B2) and the 4th buffer (B4);
When the output of the first buffer (B1) and the second buffer (B2) all exports reset voltage signal; The output output photoelectric signal of the 3rd buffer (B3) and the 4th buffer (B4).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105516625A (en) * | 2016-01-13 | 2016-04-20 | 中国科学院上海技术物理研究所 | Pixel merging read-out circuit structure for CMOS (Complementary Metal Oxide Semiconductor) image sensor and signal processing read-out method |
| CN106911332A (en) * | 2017-02-28 | 2017-06-30 | 中国电子科技集团公司第五十八研究所 | It is applied to the generating circuit from reference voltage of ADC |
| CN112420759A (en) * | 2020-11-10 | 2021-02-26 | 大连理工大学 | CMOS image sensor pixel structure based on bionic vision |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040227822A1 (en) * | 2001-07-06 | 2004-11-18 | Cartlidge Andrew G. | Digital images and related methodologies |
| CN102868865A (en) * | 2012-09-12 | 2013-01-09 | 中国科学院西安光学精密机械研究所 | Circuit and method for combining image pixels |
| CN202841351U (en) * | 2012-09-12 | 2013-03-27 | 中国科学院西安光学精密机械研究所 | Image pixel merging circuit |
| CN104243859A (en) * | 2014-09-25 | 2014-12-24 | 中国科学院合肥物质科学研究院 | Satellite-borne spectrometer CCD (charge coupled device) imaging circuit with digital pixel binning function |
-
2015
- 2015-04-20 CN CN201510188479.0A patent/CN104796639B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040227822A1 (en) * | 2001-07-06 | 2004-11-18 | Cartlidge Andrew G. | Digital images and related methodologies |
| CN102868865A (en) * | 2012-09-12 | 2013-01-09 | 中国科学院西安光学精密机械研究所 | Circuit and method for combining image pixels |
| CN202841351U (en) * | 2012-09-12 | 2013-03-27 | 中国科学院西安光学精密机械研究所 | Image pixel merging circuit |
| CN104243859A (en) * | 2014-09-25 | 2014-12-24 | 中国科学院合肥物质科学研究院 | Satellite-borne spectrometer CCD (charge coupled device) imaging circuit with digital pixel binning function |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105516625A (en) * | 2016-01-13 | 2016-04-20 | 中国科学院上海技术物理研究所 | Pixel merging read-out circuit structure for CMOS (Complementary Metal Oxide Semiconductor) image sensor and signal processing read-out method |
| CN105516625B (en) * | 2016-01-13 | 2018-10-19 | 中国科学院上海技术物理研究所 | Cmos image sensor pixel merges reading circuit structure and signal processing reading method |
| CN106911332A (en) * | 2017-02-28 | 2017-06-30 | 中国电子科技集团公司第五十八研究所 | It is applied to the generating circuit from reference voltage of ADC |
| CN106911332B (en) * | 2017-02-28 | 2020-03-31 | 中国电子科技集团公司第五十八研究所 | Reference voltage generation circuit applied to ADC |
| CN112420759A (en) * | 2020-11-10 | 2021-02-26 | 大连理工大学 | CMOS image sensor pixel structure based on bionic vision |
| CN112420759B (en) * | 2020-11-10 | 2023-11-17 | 大连理工大学 | Complementary Metal Oxide Semiconductor (CMOS) image sensor pixel structure based on bionic vision |
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| CN104796639B (en) | 2018-02-16 |
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