CN104793688A - Voltage regulator - Google Patents
Voltage regulator Download PDFInfo
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- CN104793688A CN104793688A CN201510195085.8A CN201510195085A CN104793688A CN 104793688 A CN104793688 A CN 104793688A CN 201510195085 A CN201510195085 A CN 201510195085A CN 104793688 A CN104793688 A CN 104793688A
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- auxiliary switch
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Abstract
The invention provides a voltage regulator which comprises a power transistor, an error amplifier, a logic control unit, a first auxiliary switching tube and a second auxiliary switching tube. A first connecting end of the power transistor is connected with a power source end, and a second connecting end of the power transistor is connected with the output end of the voltage regulator. A first input end of the error amplifier is connected with the output end of the voltage regulator, a second input end of the error amplifier receives reference voltage, and the output end of the error amplifier is connected with a control end of the power transistor. A first connecting end of the first auxiliary switching tube is connected with the power source end, a second connecting end of the first auxiliary switching tube is connected with the output end of the voltage regulator, and a control end of the first auxiliary switching tube is connected with the logic control unit. A first connecting end of the second auxiliary switching tube is connected with the power source end, a second connecting end of the second auxiliary switching tube is connected with the output end of the voltage regulator, and a control end of the second auxiliary switching tube is connected with the logic control unit. The voltage regulator can efficiently output voltage within a large range and meanwhile reduce urgent current.
Description
[technical field]
The present invention relates to technical field of circuit design, particularly a kind of voltage regulator.
[background technology]
Please refer to shown in Fig. 1, it is the circuit diagram of traditional a kind of low difference voltage regulator (Low Dropout regulator, LDO).This low difference voltage regulator comprises error amplifier EA, power transistor MP1, output capacitance C1.The source electrode of described power transistor MP1 is connected with power end Vext, drain electrode is connected with output end vo ut, output capacitance C1 connect and between output end vo ut and ground, described output end vo ut is connected with the normal phase input end of described error amplifier EA, and the negative-phase input of described error amplifier connects a reference voltage Vref.One input voltage Vext is adjusted to the output voltage of output end vo ut by described power transistor MP1 under the control of described error amplifier EA.Described output end vo ut provides load current Iload to load.
Described low difference voltage regulator is linear regulator, and its efficiency is the ratio of input voltage and output voltage.Therefore, described regulator efficiency when the linear zone of power transistor MP1 is best, now has the pressure drop of hundreds of millivolt between input voltage Vext and output voltage Vout.Fig. 2 shows the working range of the drain-source voltage of power transistor, and the drain-source voltage of power transistor is also the voltage difference between input voltage and output voltage.
The maximal value of the output voltage Vout of described low difference voltage regulator is the difference of input voltage Vext and minimum drain-source voltage Vsd.Be close in some application equaling input voltage Vext at output voltage Vout, this low difference voltage regulator is then helpless.
In some embodiments, described power transistor is set to power switch, or they are by full conducting, or by contract fully.This power switch can minimize the voltage difference between the source electrode of described power switch and drain electrode when its conducting.Through suitable design, the power loss of described power switch can be minimized, and its efficiency also can higher than the low difference voltage regulator shown in Fig. 1.But the disadvantage of the design of power switch to carry out voltage-regulation, and described power switch can only be opened and close.Another shortcoming of the design of power switch is that its size is large compared with the size of corresponding LDO.
Another problem is, after described low difference voltage regulator is opened, the initial voltage on described output capacitance C1 is very low, can flow through a large amount of electric currents like this from power transistor MP1.These anxious galvanizations (Rush-through current) can continue a few microsecond to several milliseconds, and this depends on the size of power transistor and the capacitance of output capacitance C1.And these anxious galvanizations will bring adverse influence to LDO, therefore need in some application to design special circuit to reduce these anxious galvanizations.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of voltage regulator, it can provide large-scale output voltage efficiently, the anxious galvanization simultaneously also reduced.
In order to solve the problem, the invention provides a kind of voltage regulator, it comprises: power transistor, and its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator; Error amplifier, its first input end is connected with the output terminal of described voltage regulator, and its second input end receives a reference voltage, and its output terminal is connected with the control end of described power transistor; Logic control element; First auxiliary switch, its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected; Second auxiliary switch, its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected.
Further, described voltage regulator also comprises: sample circuit, and the output voltage of the output terminal of its described voltage regulator of sampling obtains described sampled voltage, and described sampled voltage is supplied to the first input end of described error amplifier.
Further, sample circuit be connected on described voltage regulator output and ground between the first resistance and the second resistance, the voltage of the intermediate node between the first resistance and the second resistance is described sampled voltage.
Further, described voltage regulator also comprises: output capacitance, and it is connected between the output and ground of described voltage regulator, and described power transistor is PMOS transistor.
Further, voltage regulator has three mode of operations, these three mode of operations are respectively shaping modes, open mode and " shut " mode", when shaping modes, first auxiliary switch and the second auxiliary switch turn off, error amplifier normally works, and the input voltage that described power transistor lowers economize on electricity source in the control of error amplifier obtains output voltage, and now output voltage is lower than described input voltage; When open mode, the first auxiliary switch and the second auxiliary switch conducting, described power transistor turns off, and now output voltage equals described input voltage substantially; When " shut " mode", the first auxiliary switch and the second auxiliary switch turn off, and described power transistor turns off, and now described output voltage equals 0.
Further, be shaping modes at present mode, when needing to enter open mode, first conducting first auxiliary switch, after the schedule time of interval, then conducting second auxiliary switch, output voltage is drawn high to substantially equaling described input voltage by the first auxiliary switch and the second auxiliary switch; Be shaping modes at present mode, when needing to enter " shut " mode", error amplifier described in disable forces the output of error amplifier that described power transistor is turned off.
Further, be open mode at present mode, when needing to enter shaping modes, first turn off the second auxiliary switch, after the scheduled time slot of interval, then turn off the first auxiliary switch; Current be open mode, when needing to enter " shut " mode", first turn off the second auxiliary switch, after the scheduled time slot of interval, then turn off the first auxiliary switch, error amplifier described in disable forces the output of error amplifier that described power transistor is turned off afterwards.
Further, be " shut " mode" at present mode, when needing to enter shaping modes, first conducting first auxiliary switch, after the schedule time of interval, then conducting second auxiliary switch, first turn off the second auxiliary switch afterwards, after the schedule time of interval, then turn off the first auxiliary switch, enable described error amplifier is with power transistor described in conducting; Be " shut " mode" at present mode, when needs enter open mode, first conducting first auxiliary switch, after the schedule time of interval, then conducting second auxiliary switch, enable described error amplifier.
Compared with prior art, the present invention adds the first auxiliary power switch and the second power auxiliary switch on the basis of low difference voltage regulator, what output voltage can be made like this to be similar to equals described input voltage, simultaneously when starting described low difference voltage regulator, the first auxiliary power switch and the second power auxiliary switch can be opened successively, thus can reduce start be anxious galvanization.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the circuit diagram of traditional a kind of low difference voltage regulator;
Fig. 2 is the i-v curve schematic diagram of the low difference voltage regulator in Fig. 1;
Fig. 3 is the circuit diagram of the present invention's voltage regulator in one embodiment.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Fig. 3 is the circuit diagram of the present invention's voltage regulator in one embodiment.As shown in Figure 3, described voltage regulator comprises power transistor MP1, error amplifier EA, output capacitance C1.
First link of described power transistor MP1 is connected with power end Vext, and the second link is connected with the output end vo ut of voltage regulator.Described power end receives input voltage Vext, and the output terminal of described voltage regulator obtains output voltage Vout.The first input end of described error amplifier receives the sampled voltage of the output voltage of the output terminal of described voltage regulator, and its second input end receives a reference voltage Vref, and its output terminal is connected with the control end of described power transistor MP1.
Described output capacitance C1 is connected between the output end vo ut of described voltage regulator and earth terminal.
In one embodiment, described power transistor MP1 is PMOS (P-channel Metal OxideSemiconductor) transistor, and described source electrode is its first link, and its drain electrode is its second link, and its grid is its control end.The normal phase input end of described error amplifier is its first input end, and its negative-phase input is the second input end.
Described voltage regulator can also comprise sample circuit, and the output voltage of the output terminal of its described voltage regulator of sampling obtains described sampled voltage, and described sampled voltage is supplied to the first input end of described error amplifier.In one embodiment, directly the output terminal of described voltage regulator can be connected to the first input end of described error amplifier EA, now can think that described sampled voltage is exactly the output voltage of the output terminal of described voltage regulator, oversampling ratio is 1:1.
In another embodiment, sample circuit comprises and is connected on the first resistance R1 between the output end vo ut of described voltage regulator and earth terminal and the second resistance R2, the voltage of the intermediate node between the first resistance R1 and the second resistance R2 is described sampled voltage, and this intermediate node is connected with the first input end of described error amplifier EA.
Described power transistor MP1, error amplifier EA and output capacitance C1 form low difference voltage regulator, and described power transistor MP1 is adjusted to output voltage Vout at the control decline input voltage Vext of described error amplifier EA.
As shown in Figure 3, described voltage regulator also includes logic control element (not shown), the first auxiliary switch PS1 and the second auxiliary switch PS1.First link of the first auxiliary switch PS1 is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected, the control signal en_few that this control end receive logic control module exports.First link of the second auxiliary switch PS2 is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected, the control signal en_rest that this control end receive logic control module exports.
The size of this first auxiliary switch PS1 is little compared with the size of the second auxiliary switch PS2.In one embodiment, described switching tube PS1 and PS2 is PMOS (P-channel Metal Oxide Semiconductor) transistor, and described source electrode is its first link, and its drain electrode is its second link, and its grid is its control end.
In order to reduce anxious galvanization (rush-through current), when opening auxiliary switch PS1 and PS2, first opening the first auxiliary switch PS1, after scheduled time slot, then opening the second auxiliary switch PS2.When turning off auxiliary switch PS1 and PS2, first turning off the second auxiliary switch PS2, after scheduled time slot, then turning off the first auxiliary switch PS1.
Described voltage regulator has three mode of operations.These three mode of operations are respectively shaping modes, open mode and " shut " mode".
When shaping modes, first auxiliary switch PS1 and the second auxiliary switch PS2 turns off, error amplifier EA normally works, the input voltage Vext that described power transistor MP1 lowers economize on electricity source in the control of error amplifier obtains output voltage Vout, and now output voltage is lower than described input voltage.
When open mode, the first auxiliary switch PS1 and the second auxiliary switch PS2 conducting, now output voltage equals described input voltage substantially.Now, error amplifier EA exports and power transistor MP1 is turned off, inoperative.Due to adopt is switching tube, therefore its conducting resistance can design very little, the conduction voltage drop on it is very little, and therefore output voltage can equal described input voltage substantially, and now the efficiency of voltage regulator is very high.
When " shut " mode", the first auxiliary switch PS1 and the second auxiliary switch PS1 turns off, error amplifier EA described in disable, and described power transistor MP1 turns off, and now described output voltage equals 0.
The switching time of three kinds of mode of operations and mode are also very important.
Current be shaping modes, when needing to enter open mode, first conducting first auxiliary switch PS1, after the schedule time of interval, conducting second auxiliary switch PS2 again, output voltage is drawn high to substantially equaling described input voltage Vext gradually by the first auxiliary switch PS1 and the second auxiliary switch PS2.Owing to have employed the actuating switch pipe of sectional type, reduce anxious galvanization.Now, output voltage Vout is higher than reference voltage Vref, and error is amplified power transistor MP1 described in Control of Voltage and turned off.
Current be shaping modes, when needing to enter " shut " mode", disable error amplifier EA makes described power transistor MP1 turn off to force the output of error amplifier EA.Now, output voltage is 0V.
Be open mode at present mode, when needing to enter shaping modes, first turn off the second auxiliary switch PS2, after the scheduled time slot of interval, then turn off the first auxiliary switch PS1.Like this can the switching of gradual change type of implementation pattern, avoid occurring anxious galvanization.
Be open mode at present mode, when needing to enter " shut " mode", first turn off the second auxiliary switch PS2, after the scheduled time slot of interval, turn off the first auxiliary switch PS1 again, disable error amplifier EA makes described power transistor MP1 turn off to force the output of error amplifier EA subsequently.
Be " shut " mode" at present mode, when needing to enter shaping modes, first conducting first auxiliary switch PS1, after the schedule time of interval, conducting second auxiliary switch PS2 again, first turns off the second auxiliary switch PS2, after the scheduled time slot of interval afterwards, turn off the first auxiliary switch P S1, enable described error amplifier EA again.Anxious galvanization when starting low difference voltage regulator can be reduced like this by simply digital control and auxiliary switch that is classification conducting.
Be " shut " mode" at present mode, when needs enter open mode, first conducting first auxiliary switch, after the schedule time of interval, then conducting second auxiliary switch, enable described error amplifier EA.
Voltage regulator apparatus in Fig. 3 has the following advantages:
The first, output voltage range is from 0V to input voltage, and scope is wide, and efficiency is high;
The second, be input voltage at output voltage, when namely pressure drop is 0, keep high-level efficiency;
Three, the anxious galvanization of unlatching when LDO starts is reduced.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. a voltage regulator, is characterized in that, it comprises:
Power transistor, its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator;
Error amplifier, its first input end is connected with the output terminal of described voltage regulator, and its second input end receives a reference voltage, and its output terminal is connected with the control end of described power transistor;
Logic control element;
First auxiliary switch, its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected;
Second auxiliary switch, its first link is connected with power end, and the second link is connected with the output terminal of voltage regulator, and its control end andlogic control unit is connected.
2. voltage regulator according to claim 1, is characterized in that, it also comprises:
Sample circuit, the output voltage of the output terminal of its described voltage regulator of sampling obtains described sampled voltage, and described sampled voltage is supplied to the first input end of described error amplifier.
3. voltage regulator according to claim 2, it is characterized in that, sample circuit be connected on described voltage regulator output and ground between the first resistance and the second resistance, the voltage of the intermediate node between the first resistance and the second resistance is described sampled voltage.
4. voltage regulator according to claim 1, is characterized in that, it also comprises:
Output capacitance, it is connected between the output and ground of described voltage regulator,
Described power transistor is PMOS transistor, and the source electrode of PMOS transistor is its first link, and drain as its second link, grid is its control end.
5., according to the arbitrary described voltage regulator of claim 1-4, it is characterized in that, it has three mode of operations, and these three mode of operations are respectively shaping modes, open mode and " shut " mode",
When shaping modes, first auxiliary switch and the second auxiliary switch turn off, error amplifier normally works, and the input voltage that described power transistor lowers economize on electricity source in the control of error amplifier obtains output voltage, and now output voltage is lower than described input voltage;
When open mode, the first auxiliary switch and the second auxiliary switch conducting, described power transistor turns off, and now output voltage equals described input voltage substantially;
When " shut " mode", the first auxiliary switch and the second auxiliary switch turn off, and described power transistor turns off, and now described output voltage equals 0.
6. voltage regulator according to claim 5, is characterized in that,
Be shaping modes at present mode, when needing to enter open mode, first conducting first auxiliary switch, after the schedule time of interval, conducting second auxiliary switch again, output voltage is drawn high to substantially equaling described input voltage by the first auxiliary switch and the second auxiliary switch;
Be shaping modes at present mode, when needing to enter " shut " mode", error amplifier described in disable forces the output of error amplifier that described power transistor is turned off.
7. voltage regulator according to claim 5, is characterized in that,
Be open mode at present mode, when needing to enter shaping modes, first turn off the second auxiliary switch, after the scheduled time slot of interval, then turn off the first auxiliary switch;
Current be open mode, when needing to enter " shut " mode", first turn off the second auxiliary switch, after the scheduled time slot of interval, then turn off the first auxiliary switch, error amplifier described in disable forces the output of error amplifier that described power transistor is turned off afterwards.
8. voltage regulator according to claim 5, is characterized in that,
Be " shut " mode" at present mode, when needing to enter shaping modes, first conducting first auxiliary switch, after the schedule time of interval, conducting second auxiliary switch, first turns off the second auxiliary switch afterwards again, after the schedule time of interval, turn off the first auxiliary switch again, enable described error amplifier is with power transistor described in conducting;
Be " shut " mode" at present mode, when needs enter open mode, first conducting first auxiliary switch, after the schedule time of interval, then conducting second auxiliary switch, enable described error amplifier.
9. voltage regulator according to claim 1, is characterized in that, the size of the first auxiliary switch is less than the size of the second auxiliary switch.
10. voltage regulator according to claim 9, is characterized in that, the first auxiliary switch and the second auxiliary switch are PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510195085.8A CN104793688A (en) | 2015-04-22 | 2015-04-22 | Voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510195085.8A CN104793688A (en) | 2015-04-22 | 2015-04-22 | Voltage regulator |
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| CN104793688A true CN104793688A (en) | 2015-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510195085.8A Withdrawn CN104793688A (en) | 2015-04-22 | 2015-04-22 | Voltage regulator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116540817A (en) * | 2023-05-24 | 2023-08-04 | 深圳飞渡微电子有限公司 | Self-powered charge pump type high-power supply rejection ratio LDO circuit and control method thereof |
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| US20080116862A1 (en) * | 2006-11-21 | 2008-05-22 | System General Corp. | Low dropout regulator with wide input voltage range |
| US20090153122A1 (en) * | 2007-12-13 | 2009-06-18 | Kawagishi Norihiro | Dropper-type regulator |
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| CN103324234A (en) * | 2013-06-07 | 2013-09-25 | 灿芯半导体(上海)有限公司 | Output dynamic regulation circuit of low dropout linear regulator (LDO) |
| JP2014182487A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Semiconductor Ltd | Power source circuit, and semiconductor device |
| CN104252193A (en) * | 2013-06-28 | 2014-12-31 | 爱思开海力士有限公司 | Voltage Stabilizer Soft Start |
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2015
- 2015-04-22 CN CN201510195085.8A patent/CN104793688A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080116862A1 (en) * | 2006-11-21 | 2008-05-22 | System General Corp. | Low dropout regulator with wide input voltage range |
| US20090153122A1 (en) * | 2007-12-13 | 2009-06-18 | Kawagishi Norihiro | Dropper-type regulator |
| CN102055311A (en) * | 2009-10-29 | 2011-05-11 | 炬力集成电路设计有限公司 | Linear voltage-stabilized power supply device and soft start method thereof |
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
| JP2014182487A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Semiconductor Ltd | Power source circuit, and semiconductor device |
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| CN116540817A (en) * | 2023-05-24 | 2023-08-04 | 深圳飞渡微电子有限公司 | Self-powered charge pump type high-power supply rejection ratio LDO circuit and control method thereof |
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Application publication date: 20150722 |