CN104779271A - MOS structure, manufacturing method thereof and metal silicide manufacturing method - Google Patents

MOS structure, manufacturing method thereof and metal silicide manufacturing method Download PDF

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CN104779271A
CN104779271A CN201410010653.8A CN201410010653A CN104779271A CN 104779271 A CN104779271 A CN 104779271A CN 201410010653 A CN201410010653 A CN 201410010653A CN 104779271 A CN104779271 A CN 104779271A
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metal
region
temperature
value
drain region
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CN104779271B (en
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闻正锋
黄杰
马万里
赵文魁
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Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to the technical field of semiconductors, and particularly relates to a method of manufacturing a metal silicide in an MOS structure, so as to solve the problem that a metal silicide formed in a gate area, a source area and a drain area has large a resistance value in the prior art. The method of manufacturing the metal silicide in the MOS structure provided by the embodiment of the invention comprises steps: in a first temperature condition, metal is deposited on a substrate on which a gate area, a source area, a drain area and an insulated area are formed; the metal on the gate area, the source area and the drain area reacts with a silicon material on the gate area, the source area and the drain area respectively to generate a metal silicide, wherein the value of the first temperature is no smaller than that of a temperature at which the metal reacts with the gate area, the source area and the drain area; first-time quick thermal annealing treatment is carried out on the substrate; cleaning treatment is carried out on the substrate after the first-time quick thermal annealing treatment; and second-time quick thermal annealing treatment is carried out on the substrate after cleaning treatment. The metal silicide finally generated by the embodiment of the invention has a small resistance value.

Description

The method of MOS structure and preparation method thereof and making metal silicide
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of MOS structure and preparation method thereof and make the method for metal silicide in MOS structure.
Background technology
In the semiconductor device, comprise MOS(Metal-oxide-semicondutor) device of structure, such as MOS device, CMOS(complementary metal oxide semiconductors (CMOS)) device, BCD(bipolar transistor-complementary metal oxide semiconductors (CMOS)-double-diffused metal oxide semiconductor) device and RF LDMOS(rf-ldmos semiconductor) device application widely.
Wherein, make the method for the MOS structure in semiconductor device, comprising:
Steps A 1, in the substrate formation source region and drain region, and form grid region and insulation layer over the substrate; Wherein, source region and drain region lay respectively at the both sides in described grid region, and insulation layer is between described grid region and described source region and between described grid region and described drain region, for making source region and drain region and grid region mutually insulated;
Steps A 2, form the oxide layer covering grid region, source region, drain region and insulation layer;
Steps A 3, patterned process is carried out to described oxide layer, formed expose grid region the first via hole, expose second via hole in source region and expose the 3rd via hole in drain region;
Steps A 4, in the oxide layer comprising described first via hole, the second via hole and the 3rd via hole, form metal level, such as, Al(aluminium) layer; Wherein, the metal of described metal level can drop in described first via hole, contacts with described grid region, forms gate electrode; The metal of described metal level can drop in described second via hole, with described source contact, forms source electrode; The metal of described metal level can drop in described 3rd via hole, with described drain contact, forms drain electrode.
Because the material in grid region is the polysilicon that resistance value is larger, therefore gate resistance is larger; In addition, the grid region larger with resistance value due to the metal of metal level contacts, therefore described metal is larger with the contact resistance in grid region, and, because the material in source region and drain region is monocrystalline silicon, therefore the contact resistance in described metal and source region and described metal also larger with the contact resistance in drain region.Due to the gate resistance of MOS structure and contact resistance larger, thus cause the power dissipation ratio of the semiconductor device comprising MOS structure larger.
At present in order to reduce described gate resistance and contact resistance, to reduce the power consumption comprising the semiconductor device of MOS structure, general meeting, before described steps A 2, described grid region, source region and drain region forms metal silicide, and then performs steps A 2 and subsequent step.For gate resistance, because the resistance value being positioned at the metal silicide on grid region is less than the gate resistance in grid region, therefore in parallel with described grid region by described metal silicide, the gate resistance value in grid region can be reduced; For contact resistance, because metal silicide is positioned on grid region, source region and drain region, the direct Metal-silicides Contact smaller with described resistance value of metal of the described metal level therefore in steps A 4, thus described contact resistance can be reduced.
Wherein, on described grid region, source region and drain region, form metal silicide at present, comprising:
Step B1, be room temperature at depositing temperature, vacuum, deposition power is under the condition of setting deposition power, and be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer, deposition duration is setting deposition duration;
Wherein, in step bl is determined., the value setting deposition power and setting deposition duration rule of thumb or can need setting; Such as, when the metal deposited is titanium, the value of setting deposition power is generally 2.5kw(kilowatt), the value of setting deposition duration is generally 10s(second)-15s;
By arranging the value of setting deposition power and setting deposition duration, can realize the thickness controlling plated metal, such as, be 2.5kw in the value of setting deposition power, when the value of setting deposition duration is 10s-15s, the one-tenth-value thickness 1/10 of the metal of deposition is generally 200A(dust)-1000A.
Wherein, in step bl is determined., metal targets is included in the reaction chamber of depositing device; Be formed grid region, source region, drain region and insulation layer substrate be arranged in the reaction chamber of depositing device; Depositing device, by controlling argon gas ion bombardment metal targets, realizes in the deposited on substrates layer of metal being formed with grid region, source region, drain region and insulation layer; Thus, depositing temperature is the temperature of the reaction chamber of depositing device, is vacuum state in the reaction chamber of depositing device, and deposition power is the energy of argon gas ion bombardment metal targets, and deposition duration is the duration of argon gas ion bombardment metal targets.
Wherein, in step bl is determined., the instruction from user of depositing device by receiving, controls described depositing temperature, the reaction chamber of depositing device is vacuum state, deposition power and deposition duration.
Step B2, be setting first rapid thermal annealing temperature at rapid thermal annealing temperature, under the condition of nitrogen, carry out first time quick thermal annealing process to substrate grid region, source region, drain region and insulation layer depositing metal, rapid thermal annealing duration is setting first rapid thermal annealing duration; A part of metal is reacted with grid region, source region and drain region respectively, generates 49 phase metal silicides; Part metal and nitrogen react, and generate metal nitride; Part metal has neither part nor lot in reaction;
Wherein, depositing temperature is less than first time rapid thermal annealing temperature, and deposition duration is less than first time rapid thermal annealing duration;
The value setting the first rapid thermal annealing temperature and setting the first rapid thermal annealing duration rule of thumb or can need setting; Such as, the span setting the first rapid thermal annealing duration is 20s-40s, and when the metal deposited is titanium, the span setting the first rapid thermal annealing temperature is 650 DEG C-750 DEG C.
Wherein, in step B2, substrate grid region, source region, drain region and insulation layer depositing metal is arranged in the reaction chamber of rapid thermal annealers, and rapid thermal annealing temperature is the temperature of reaction chamber, and the gas in the reaction chamber of rapid thermal annealers is nitrogen; The instruction from user of rapid thermal annealers by receiving, controls the gas in described rapid thermal annealing temperature, its reaction chamber and duration.
Wherein, in step B2, the material of insulation layer is silicon dioxide, and when temperature is the first rapid thermal annealing temperature, metal and the silicon dioxide of deposition do not react.
Step B3, wash metal nitride and do not participate in react metal;
Wherein, in step B3, the part metals on insulation layer has neither part nor lot in reaction, therefore, can be washed.
Step B4, be setting second rapid thermal annealing temperature at rapid thermal annealing temperature, under the condition of nitrogen, second time quick thermal annealing process is carried out to substrate grid region, source region and drain region being formed with 49 phase metal silicides, rapid thermal annealing duration is setting second rapid thermal annealing duration, makes described 49 phase metal silicides change 54 phase metal silicides into; Wherein the resistance value of 54 phase metal silicides is probably 1/3rd of 49 phase metal silicides.
Wherein, rapid thermal annealing temperature is less than second time rapid thermal annealing temperature for the first time, and rapid thermal annealing duration can be less than, be equal to or greater than second time rapid thermal annealing duration for the first time;
The value setting the second rapid thermal annealing temperature and setting the second rapid thermal annealing duration rule of thumb or can need setting; Such as, the span setting the second rapid thermal annealing duration is 20s-40s, and when the metal deposited is titanium, the span setting the second rapid thermal annealing temperature is 800 DEG C-900 DEG C.
In above-mentioned steps B2, because the gas in the reaction chamber of rapid thermal annealers is nitrogen, thus when carrying out first time quick thermal annealing process, part metals meeting and nitrogen react, generation can by the metal nitride washed, thus decrease and grid region, the metal of source region and drain region reaction, make grid region, the reaction of source region and drain region and metal is insufficient, the one-tenth-value thickness 1/10 of the metal silicide generated is smaller, make the resistance value of the final metal silicide generated larger, and then make the effect reducing described gate resistance and contact resistance not so good, further, reduce the effect comprising the power consumption of the semiconductor device of MOS structure also not so good.
In sum, the resistance value of the metal silicide formed on grid region, source region and drain region is at present larger, makes the effect reducing gate resistance and contact resistance not so good, causes that to reduce the effect comprising the power consumption of the semiconductor device of MOS structure also not so good.
Summary of the invention
A kind of MOS structure that the embodiment of the present invention provides and preparation method thereof and make the method for metal silicide in MOS structure, resistance value in order to solve the current metal silicide formed on grid region, source region and drain region existed in prior art is larger, make the effect reducing gate resistance and contact resistance not so good, thus cause and reduce the also not so good problem of the effect that comprises the power consumption of the semiconductor device of MOS structure.
First aspect, the embodiment of the present invention provide the first in MOS structure, make the method for metal silicide, comprising:
Steps A, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; The temperature value that the value of wherein said first temperature is not less than described metal and described grid region, the silicon materials in source region and drain region react;
Step B, first time quick thermal annealing process is carried out to described substrate;
Step C, clean is carried out to the described substrate after first time quick thermal annealing process;
Step D, carry out second time quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
In embodiments of the present invention, compared with prior art, in step, depositing temperature during plated metal is risen to the first temperature of the temperature value that value is not less than metal and grid region, the silicon materials in source region and drain region react; Can make when plated metal, deposit to metal on grid region, source region and drain region and to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; That is, when performing the step of plated metal, the described metal of deposition will react with the silicon materials in described grid region, source region and drain region respectively, and described grid region, source region and drain region form metal silicide;
Thus make by carrying out first time quick thermal annealing process to described substrate, the silicon materials in the metal of deposition and described grid region, source region and drain region continue to react, the reaction of the silicon materials in the metal and the described grid region that make to deposit, source region and drain region is more abundant, the one-tenth-value thickness 1/10 of the metal silicide of final generation is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good.
Preferably, when carrying out first time quick thermal annealing process to described substrate, the gas of the reaction chamber that described substrate is positioned at is inert gas.
In embodiments of the present invention, due to when carrying out first time quick thermal annealing process to described substrate, inert gas does not react with the described metal of deposition, therefore, described metal can not be consumed, avoid the described metal of waste to a certain extent, and avoid to a certain extent reducing the metal reacted with the silicon materials in described grid region, source region and drain region, make described metal and grid region, source region and drain region the extent of reaction of silicon materials more abundant.
Preferably, the temperature value that the material that the value of described first temperature is less than described metal and described insulation layer reacts.
In embodiments of the present invention, grid region, source region and drain region can be avoided to interconnect.
Preferably, described metal is titanium.
Those skilled in the art in embodiments of the present invention, provide a kind of embodiment of metal, so that can realize technical scheme of the present invention easily.It should be noted that, the described concrete metal in the embodiment of the present invention only for explaining the present invention, and is not limited to the present invention, and other metal that may be used for realizing technical solution of the present invention is also within protection scope of the present invention.
Second aspect, the second that the embodiment of the present invention provides makes the method for metal silicide in MOS structure, comprising:
Steps A, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer, deposition duration is the first duration; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively, generate metal silicide; Wherein, the value of described first temperature is not less than abundant reaction temperature threshold value, described abundant reaction temperature threshold value is the difference of the temperature value that reacts of the material of described metal and described insulation layer and fluctuating temperature value, and the span of described fluctuating temperature value is [50 DEG C, 100 DEG C]; The span of described first duration is [20s, 40s];
Step B, clean is carried out to described substrate;
Step C, carry out quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
In embodiments of the present invention, compared with prior art, in step, depositing temperature during plated metal is risen to the first temperature that value is not less than abundant reaction temperature threshold value, and deposition duration is extended for the first duration; Can making when performing the step of plated metal, depositing to metal on grid region, source region and drain region and with the silicon materials in described grid region, source region and drain region, abundant reaction occurring respectively and generate metal silicide; That is, when performing the step of plated metal, the described metal of deposition can occur fully to react with the silicon materials in described grid region, source region and drain region respectively, and described grid region, source region and drain region form metal silicide;
Due to when performing the step of plated metal, the described metal of deposition occurs fully to react with the silicon materials in described grid region, source region and drain region respectively, described grid region, source region and drain region form metal silicide, make that the one-tenth-value thickness 1/10 of the final metal silicide generated is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good;
And due to when performing the step of plated metal, the described metal of deposition occurs fully to react with the silicon materials in described grid region, source region and drain region respectively, described grid region, source region and drain region form metal silicide, thus the step of described substrate being carried out to first time quick thermal annealing process can be omitted, reduce the cost making metal silicide in MOS structure, and reduce the complexity making metal silicide in MOS structure.
Preferably, when depositing described layer of metal, the value of deposition power and the value negative correlation of described first duration.
In embodiments of the present invention, the thickness of metal deposited can be controlled, thus the amount of the silicon materials in the grid region realizing controlling to react with described metal, source region and drain region, and then ensure the electrical property of MOS structure.
Preferably, the temperature value that the material that the value of described first temperature is less than described metal and described insulation layer reacts.
In embodiments of the present invention, grid region, source region and drain region can be avoided to interconnect.
Preferably, described metal is titanium.
Those skilled in the art in embodiments of the present invention, provide a kind of embodiment of metal, so that can realize technical scheme of the present invention easily.It should be noted that, the described concrete metal in the embodiment of the present invention only for explaining the present invention, and is not limited to the present invention, and other metal that may be used for realizing technical solution of the present invention is also within protection scope of the present invention.
The third aspect, the embodiment of the present invention provides a kind of manufacture method of MOS structure, comprising:
Form source region and drain region in the substrate, and form grid region and insulation layer over the substrate;
The method making metal silicide in MOS structure described in employing, the grid region of described substrate, source region and drain region are formed the metal silicide changing phase;
Form the oxide layer covering described metal silicide and insulation layer, patterned process is carried out to described oxide layer, and form metal level in the oxide layer after patterned process, to form gate electrode, source electrode and drain electrode respectively.
In embodiments of the present invention, the first described in adopting makes the method for metal silicide in MOS structure, when the grid region of described substrate, source region and drain region are formed the metal silicide changing phase, make that the one-tenth-value thickness 1/10 of the final metal silicide formed is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good; And
The second described in adopting makes the method for metal silicide in MOS structure, when the grid region of described substrate, source region and drain region are formed the metal silicide changing phase, not only make that the one-tenth-value thickness 1/10 of the final metal silicide formed is larger and resistance value is smaller, the effectiveness comparison reducing described gate resistance and contact resistance is good, reduces the effect comprising the power consumption of the semiconductor device of MOS structure also relatively good; And make it possible to omit the step of described substrate being carried out to first time quick thermal annealing process, reduce the cost of manufacture of MOS structure, and reduce the making complexity of MOS structure.
Fourth aspect, the embodiment of the present invention provides a kind of MOS structure, wherein: this MOS structure is made by the manufacture method of described MOS structure.
In embodiments of the present invention, gate resistance and the contact resistance of MOS structure are smaller, and the power consumption comprising the semiconductor device of this MOS structure is also smaller; In addition, the cost of manufacture of this MOS structure smaller and make complexity lower.
Compared with prior art, make in MOS structure in the method for metal silicide in the first of the embodiment of the present invention, depositing temperature during plated metal is risen to the first temperature of the temperature value that value is not less than metal and grid region, the silicon materials in source region and drain region react; Can make when plated metal, deposit to metal on grid region, source region and drain region and to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; Thus make by carrying out first time quick thermal annealing process to described substrate, the silicon materials in the metal of deposition and described grid region, source region and drain region continue to react, the reaction of the silicon materials in the metal and the described grid region that make to deposit, source region and drain region is more abundant, the one-tenth-value thickness 1/10 of the metal silicide of final generation is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good.
Compared with prior art, make in MOS structure in the method for metal silicide at the second of the embodiment of the present invention, depositing temperature during plated metal is risen to the first temperature that value is not less than abundant reaction temperature threshold value, and deposition duration is extended for the first duration; Can making when performing the step of plated metal, depositing to metal on grid region, source region and drain region and with the silicon materials in described grid region, source region and drain region, abundant reaction occurring respectively and generate metal silicide; Make that the one-tenth-value thickness 1/10 of the final metal silicide generated is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect that reduction comprises the power consumption of the semiconductor device of MOS structure is also relatively good; And eliminate the step of described substrate being carried out to first time quick thermal annealing process, reduce the cost making metal silicide in MOS structure, and reduce the complexity making metal silicide in MOS structure.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram that in the embodiment of the present invention, the first makes metal silicide in MOS structure;
Fig. 2 is the method flow schematic diagram that in the embodiment of the present invention, the second makes metal silicide in MOS structure;
Fig. 3 A ~ Fig. 3 E is the generalized section of MOS structure in the process making metal silicide in the embodiment of the present invention in MOS structure;
Fig. 4 is the manufacture method schematic flow sheet of MOS structure in the embodiment of the present invention.
Embodiment
In embodiments of the present invention, in MOS structure, make the method for metal silicide for the first, depositing temperature during plated metal is risen to the first temperature of the temperature value that value is not less than metal and grid region, the silicon materials in source region and drain region react; Can make when plated metal, deposit to metal on grid region, source region and drain region and to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; Thus make by carrying out first time quick thermal annealing process to described substrate, the silicon materials in the metal of deposition and described grid region, source region and drain region continue to react, the reaction of the silicon materials in the metal and the described grid region that make to deposit, source region and drain region is more abundant, the one-tenth-value thickness 1/10 of the metal silicide of final generation is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good;
In MOS structure, make the method for metal silicide for the second, depositing temperature during plated metal is risen to the first temperature that value is not less than abundant reaction temperature threshold value, and deposition duration is extended for the first duration; Can making when performing the step of plated metal, depositing to metal on grid region, source region and drain region and with the silicon materials in described grid region, source region and drain region, abundant reaction occurring respectively and generate metal silicide; Make that the one-tenth-value thickness 1/10 of the final metal silicide generated is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect that reduction comprises the power consumption of the semiconductor device of MOS structure is also relatively good; And eliminate the step of described substrate being carried out to first time quick thermal annealing process, reduce the cost making metal silicide in MOS structure, and reduce the complexity making metal silicide in MOS structure.
Below in conjunction with Figure of description, the embodiment of the present invention is described in further detail.
It should be noted that, in embodiments of the present invention, provide the method that two kinds make metal silicide in MOS structure, will be introduced respectively below.
As shown in Figure 1, the method that the first of the embodiment of the present invention makes metal silicide in MOS structure comprises the following steps:
Step 101, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; The temperature value that the value of wherein said first temperature is not less than described metal and described grid region, the silicon materials in source region and drain region react;
Step 102, first time quick thermal annealing process is carried out to described substrate;
Step 103, clean is carried out to the described substrate after first time quick thermal annealing process;
Step 104, carry out second time quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
In enforcement, compared with prior art, in a step 101, depositing temperature during plated metal is risen to the first temperature of the temperature value that value is not less than metal and grid region, the silicon materials in source region and drain region react; Can make when plated metal, deposit to metal on grid region, source region and drain region and to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; That is, when performing the step of plated metal, the described metal of deposition will react with the silicon materials in described grid region, source region and drain region respectively, and described grid region, source region and drain region form metal silicide;
Thus make by carrying out first time quick thermal annealing process to described substrate, the silicon materials in the metal of deposition and described grid region, source region and drain region continue to react, the reaction of the silicon materials in the metal and the described grid region that make to deposit, source region and drain region is more abundant, the one-tenth-value thickness 1/10 of the metal silicide of final generation is larger and resistance value is smaller, and then make the effectiveness comparison of the gate resistance in reduction MOS structure and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good.
Preferably, in embodiments of the present invention, the metal of deposition can be any one metal in prior art, such as, and T i(titanium), C o(cobalt) or N i(nickel).
Preferably, in a step 101, the temperature value that the silicon materials that the temperature value that the silicon materials in described metal and described grid region react equals described metal and source region and drain region react;
The material in described grid region is polysilicon, and the material in described source region and drain region is monocrystalline silicon; The temperature value that described metal and polysilicon react equals the temperature value that described metal and monocrystalline silicon react.
In enforcement, the temperature value that the value of the first temperature is not less than described metal and described grid region, the silicon materials in source region and drain region react, can ensure under the first temperature conditions, the silicon materials in described metal and described grid region, source region and drain region all react generation metal silicide.
Preferably, in a step 101, the temperature value that the material that the value of the first temperature is less than described metal and described insulation layer reacts;
The material of described insulation layer is silicon dioxide; The value of described first temperature is less than the temperature value that described metal and silicon dioxide react.
In enforcement, the temperature value that the material that the value of the first temperature is less than described metal and described insulation layer reacts, can avoid grid region, source region and drain region to interconnect.
In concrete enforcement, in a step 101, depositing temperature is the temperature of the reaction chamber of depositing device.
In concrete enforcement, in a step 101, be formed grid region, source region, drain region and insulation layer deposited on substrates layer of metal time, other parameters except depositing temperature, such as, execution mode and the execution mode of the prior art of vacuum degree, deposition power and deposition duration in the reaction chamber of depositing device are similar.
In concrete enforcement, in a step 102, to described substrate carry out first time quick thermal annealing process execution mode can be similar with execution mode of the prior art.
Preferably, in a step 102, when carrying out first time quick thermal annealing process to described substrate, the gas of the reaction chamber (that is, the reaction chamber of rapid thermal annealers) that described substrate is positioned at is inert gas, such as, and argon gas.
In enforcement, when carrying out first time quick thermal annealing process to described substrate, inert gas does not react with the described metal of deposition, therefore, described metal can not be consumed, avoid the described metal of waste to a certain extent, and avoid to a certain extent reducing the metal reacted with the silicon materials in described grid region, source region and drain region, make described metal and grid region, source region and drain region the extent of reaction of silicon materials more abundant.
In concrete enforcement, in step 103, the execution mode of clean is carried out to the described substrate after first time quick thermal annealing process and execution mode of the prior art similar;
Wherein, if in a step 102, when carrying out first time quick thermal annealing process to described substrate, the gas of the reaction chamber that described substrate is positioned at is inert gas; Then in step 103, the metal not participating in reacting only is washed;
If in a step 102, when carrying out first time quick thermal annealing process to described substrate, the gas of the reaction chamber that described substrate is positioned at is nitrogen; Then in step 103, except washing the metal not participating in reacting, also need to wash the metal nitride that nitrogen and metal reaction generate.
In concrete enforcement, at step 104, similar to the execution mode and execution mode of the prior art that carry out second time quick thermal annealing process through cleaned described substrate.
It should be noted that, in embodiments of the present invention, in a step 101, the metal silicide of generation is 49 phase metal silicides; In a step 102, first time quick thermal annealing process is carried out to described substrate, make the metal the deposited metal silicide generated that continues with the silicon materials in grid region, source region and drain region respectively to react be 49 phase metal silicides; At step 104, the 49 phase metal silicides that described grid region, source region and drain region are formed are changed into 54 phase metal silicides.
As shown in Figure 2, the method that the second of the embodiment of the present invention makes metal silicide in MOS structure comprises the following steps:
Step 201, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer, deposition duration is the first duration; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively, generate metal silicide; Wherein, the value of described first temperature is not less than abundant reaction temperature threshold value, described abundant reaction temperature threshold value is the difference of the temperature value that reacts of the material of described metal and described insulation layer and fluctuating temperature value, and the span of described fluctuating temperature value is [50 DEG C, 100 DEG C]; The span of described first duration is [20s, 40s];
Step 202, clean is carried out to described substrate;
Step 203, carry out quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
In enforcement, compared with prior art, in step 201, depositing temperature during plated metal is risen to the first temperature that value is not less than abundant reaction temperature threshold value, and deposition duration is extended for the first duration; Can making when performing the step of plated metal, depositing to metal on grid region, source region and drain region and with the silicon materials in described grid region, source region and drain region, abundant reaction occurring respectively and generate metal silicide; That is, when performing the step of plated metal, the described metal of deposition just can occur fully to react with the silicon materials in described grid region, source region and drain region respectively, and described grid region, source region and drain region form metal silicide;
Due to when performing the step of plated metal, the described metal of deposition occurs fully to react with the silicon materials in described grid region, source region and drain region respectively, described grid region, source region and drain region form metal silicide, make that the one-tenth-value thickness 1/10 of the final metal silicide generated is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good;
And due to when performing the step of plated metal, the described metal of deposition occurs fully to react with the silicon materials in described grid region, source region and drain region respectively, described grid region, source region and drain region form metal silicide, thus the step of described substrate being carried out to first time quick thermal annealing process can be omitted, reduce the cost making metal silicide in MOS structure, and reduce the complexity making metal silicide in MOS structure.
Preferably, in embodiments of the present invention, the metal of deposition can be any one metal in prior art, such as, and T i(titanium), C o(cobalt) or N i(nickel).
Preferably, in step 201, the value of the first temperature is not less than abundant reaction temperature threshold value, described abundant reaction temperature threshold value is the difference of the temperature value that reacts of the material of described metal and described insulation layer and fluctuating temperature value, the span of described fluctuating temperature value is [50 DEG C, 100 DEG C]; Namely the lower limit of the span of the first temperature is described abundant reaction temperature threshold value;
The material of described insulation layer is silicon dioxide, and described abundant reaction temperature threshold value is the difference of the temperature value that reacts of described metal and silicon dioxide and fluctuating temperature value.Wherein, the lower limit of the span of the first temperature in step 201 is greater than the lower limit of the span of the first temperature in step 101.
Preferably, in step 201, the temperature value that the material that the value of described first temperature is less than described metal and described insulation layer reacts; Namely the higher limit of the span of the first temperature is the temperature value that the material of described metal and described insulation layer reacts;
The material of described insulation layer is silicon dioxide, and the value of described first temperature is less than the temperature value that described metal and silicon dioxide react.
In enforcement, the temperature value that the material that the value of the first temperature is less than described metal and described insulation layer reacts, can avoid grid region, source region and drain region to interconnect.
Preferably, in step 201, the difference of the lower limit of the higher limit of the span of the first temperature and the span of described first temperature is between 50 DEG C-100 DEG C.
In enforcement, the value of the first temperature is not less than described abundant reaction temperature threshold value, and deposition duration is the first duration, described metal and described grid region can be ensured, the silicon materials in source region and drain region occur fully to react, the larger and metal silicide that resistance value is smaller of generation one-tenth-value thickness 1/10.
Preferably, in step 201, when depositing described layer of metal, the value of deposition power and the value negative correlation of described first duration.
In enforcement, when the value negative correlation of the value of deposition power and described first duration, the thickness of metal that can control to deposit can not be too thick, thus the amount of the silicon materials in the grid region realizing controlling to react with described metal, source region and drain region can not be too many, and then ensure the electrical property of MOS structure.
In concrete enforcement, in step 201, depositing temperature is the temperature of the reaction chamber of depositing device, and deposition duration is the duration of argon gas ion bombardment metal targets, and deposition power is the energy of argon gas ion bombardment metal targets.
In concrete enforcement, in step 201, be formed grid region, source region, drain region and insulation layer deposited on substrates layer of metal time, execution mode and the execution mode of the prior art of the vacuum degree in the reaction chamber of depositing device are similar.
In enforcement, in step 201, be vacuum state in the reaction chamber of depositing device, can ensure the metal that deposits not with the silicon materials except described grid region, source region and drain region except material react, avoid to a certain extent reducing the metal reacted with the silicon materials in described grid region, source region and drain region, make described metal and grid region, source region and drain region the extent of reaction of silicon materials more abundant.
In concrete enforcement, in step 202., the execution mode of clean is carried out to described substrate and execution mode of the prior art similar;
In step 202., the metal not participating in reacting only is washed.
In concrete enforcement, in step 203, similar to the execution mode and execution mode of the prior art that carry out quick thermal annealing process through cleaned described substrate.
It should be noted that, in embodiments of the present invention, in step 201, the metal silicide of generation is 49 phase metal silicides; In step 203, the 49 phase metal silicides that described grid region, source region and drain region are formed are changed into 54 phase metal silicides.
In order to the scheme of the embodiment of the present invention in detail, is clearly described, below with deposition metal for T i, the method the first of the embodiment of the present invention being made in MOS structure to metal silicide describes in detail.
Embodiment one
As shown in Figure 3A, MOS structure comprises substrate 1, is arranged in the source region 2 of substrate 1 and drain region 3 and the grid region 4 be positioned on substrate 1 and insulation layer 5; Wherein the material in source region 2 and drain region 3 is monocrystalline silicon, and the material in grid region 4 is polysilicon, and the material of insulation layer 5 is silicon dioxide; T ithe temperature value reacted with monocrystalline silicon and polysilicon is 200 DEG C, T ithe temperature value reacted with silicon dioxide is 750 DEG C, the span of depositing temperature be [200 DEG C, 750 DEG C).
Steps A 1, be 200 DEG C ~ 500 DEG C at depositing temperature, the vacuum degree of the reaction chamber of depositing device is 3mt(millitorr), deposition power is under the condition of 2.5kw, is being formed with deposited on substrates one deck T of grid region, source region, drain region and insulation layer i, deposition duration is 10s-15s; Make to be positioned at the T on described grid region, source region and drain region ireact with the silicon materials in described grid region, source region and drain region generation 49 phase T respectively i-S icompound;
Wherein, after execution of step A1, as shown in Figure 3 B, the part T on grid region 4 is positioned at i6 to react generation 49 phase T with the silicon materials in grid region 4 i-S icompound 7, is positioned at the part T on source region 2 i6 to react generation 49 phase T with the silicon materials in source region 2 i-S icompound 7, and be positioned at the part T on drain region 3 i6 to react generation 49 phase T with the silicon materials in drain region 3 i-S icompound 7.
Wherein, in steps A 1, when depositing duration and be 10s-15s and deposition power being 2.5kw, the T of deposition ione-tenth-value thickness 1/10 within the scope of 200A ~ 1000A.Steps A 2, be 650 DEG C ~ 750 DEG C at rapid thermal annealing temperature, and the gas of the reaction chamber of rapid thermal annealers is under the condition of nitrogen, carries out first time quick thermal annealing process to described substrate, rapid thermal annealing duration is 20s-40s; Make to be positioned at the T on described grid region, source region and drain region icontinue to react with the silicon materials in described grid region, source region and drain region generation 49 phase T i-S icompound; Nitrogen and a small amount of T ireact, generate T i-N compound;
Wherein, after execution of step A2, as shown in Figure 3 C, part T ithe generation 49 phase T that reacts is continued with the silicon materials in grid region 4 i-S icompound 7, part T ithe generation 49 phase T that reacts is continued with the silicon materials in source region 2 i-S icompound 7, and part T ithe generation 49 phase T that reacts is continued with the silicon materials in drain region 3 i-S icompound 7; The part T contacted with nitrogen ireact with nitrogen, generate T i-N compound 8.
Steps A 3, employing ammoniacal liquor and the mixed liquor of hydrogen peroxide or the mixed liquor of sulfuric acid and hydrogen peroxide, by T i-N compound and insulation layer have neither part nor lot in the T of reaction iwash;
Wherein, after execution of step A3, as shown in Figure 3 D, source region 2, drain region 3 and grid region 4 are formed with 49 phase T i-S icompound 7; Without 49 described phase T on insulation layer 5 i-S icompound 7.
Steps A 4, be 800 DEG C ~ 900 DEG C at rapid thermal annealing temperature, and the gas of the reaction chamber of rapid thermal annealers is under the condition of nitrogen, carries out second time quick thermal annealing process to described substrate, rapid thermal annealing duration is 20s-40s; Change the 49 phase T that described grid region, source region and drain region are formed i-S ithe phase of compound, by described 49 phase T i-S icompound changes 54 phase T into i-S icompound.
Wherein, after execution of step A4, as shown in FIGURE 3 E, source region 2, drain region 3 and grid region 4 define 54 phase T i-S icompound 9.
Wherein, 54 described phase T i-S ithe resistance of compound probably only has 49 phase T i-S i/ 3rd of a compound.
Wherein, to deposit T ione-tenth-value thickness 1/10 be 400A when testing, adopt the 54 phase T that the method making metal silicide in MOS structure of the prior art is formed i-S ithe one-tenth-value thickness 1/10 of compound is about 580A, and square resistance is about 9.2ohm(ohm); Adopt the 54 phase T that the method making metal silicide in the embodiment of the present invention one in MOS structure is formed i-S ithe one-tenth-value thickness 1/10 of compound is about 900A, and square resistance is about 5.7ohm.
As shown in Figure 4, the manufacture method of the MOS structure of the embodiment of the present invention comprises the following steps:
Step 401, in the substrate formation source region and drain region, and form grid region and insulation layer over the substrate;
Step 402, adopt described in the method making metal silicide in MOS structure, the grid region of described substrate, source region and drain region are formed and change the metal silicide of phase;
Step 403, formation cover the oxide layer of described metal silicide and insulation layer, carry out patterned process, and form metal level in the oxide layer after patterned process, to form gate electrode, source electrode and drain electrode respectively to described oxide layer.
In enforcement, the first described in adopting makes the method for metal silicide in MOS structure, when the grid region of described substrate, source region and drain region are formed the metal silicide changing phase, make that the one-tenth-value thickness 1/10 of the final metal silicide formed is larger and resistance value is smaller, and then make the effectiveness comparison reducing described gate resistance and contact resistance good, further, the effect comprising the power consumption of the semiconductor device of MOS structure is reduced also relatively good; And
The second described in adopting makes the method for metal silicide in MOS structure, when the grid region of described substrate, source region and drain region are formed the metal silicide changing phase, not only make that the one-tenth-value thickness 1/10 of the final metal silicide formed is larger and resistance value is smaller, the effectiveness comparison reducing described gate resistance and contact resistance is good, reduces the effect comprising the power consumption of the semiconductor device of MOS structure also relatively good; And make it possible to omit the step of described substrate being carried out to first time quick thermal annealing process, reduce the cost of manufacture of MOS structure, and reduce the making complexity of MOS structure.
In concrete enforcement, in step 401, form source region and drain region in the substrate, and formed over the substrate in the execution mode of grid region and insulation layer and prior art and form source region and drain region in the substrate, and the execution mode forming grid region and insulation layer is over the substrate similar, does not repeat them here.
Preferably, in step 402, the method making metal silicide in MOS structure described in employing, the execution mode that the grid region of described substrate, source region and drain region are formed the metal silicide changing phase can see the execution mode making the method part of metal silicide in MOS structure of the embodiment of the present invention.
In concrete enforcement, in step 403, form the execution mode forming gate electrode, source electrode and drain electrode in the execution mode of gate electrode, source electrode and drain electrode and prior art similar, do not repeat them here.
In concrete enforcement, when making MOS structure, form the processing step formed after gate electrode, source electrode and drain electrode in processing step after gate electrode, source electrode and drain electrode and prior art similar, such as, formation protective layer.
Preferably, embodiments provide a kind of MOS structure, described MOS structure is made by the method for described making MOS structure.
In enforcement, gate resistance and the contact resistance of MOS structure are smaller, and the power consumption comprising the semiconductor device of described MOS structure is also smaller; In addition, the cost of manufacture of described MOS structure smaller and make complexity lower.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims (10)

1. in MOS structure, make a method for metal silicide, it is characterized in that, comprising:
Steps A, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively generation metal silicide; The temperature value that the value of wherein said first temperature is not less than described metal and described grid region, the silicon materials in source region and drain region react;
Step B, first time quick thermal annealing process is carried out to described substrate;
Step C, clean is carried out to the described substrate after first time quick thermal annealing process;
Step D, carry out second time quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
2. the method for claim 1, is characterized in that, when carrying out first time quick thermal annealing process to described substrate, the gas of the reaction chamber that described substrate is positioned at is inert gas.
3. the method for claim 1, is characterized in that, the temperature value that the material that the value of described first temperature is less than described metal and described insulation layer reacts.
4. the method as described in as arbitrary in claims 1 to 3, it is characterized in that, described metal is titanium.
5. in MOS structure, make a method for metal silicide, it is characterized in that, comprising:
Steps A, under depositing temperature is the first temperature conditions, be formed with the deposited on substrates layer of metal of grid region, source region, drain region and insulation layer, deposition duration is the first duration; Make to be positioned at described metal on described grid region, source region and drain region to react with the silicon materials in described grid region, source region and drain region respectively, generate metal silicide; Wherein, the value of described first temperature is not less than abundant reaction temperature threshold value, described abundant reaction temperature threshold value is the difference of the temperature value that reacts of the material of described metal and described insulation layer and fluctuating temperature value, and the span of described fluctuating temperature value is [50 DEG C, 100 DEG C]; The span of described first duration is [20s, 40s];
Step B, clean is carried out to described substrate;
Step C, carry out quick thermal annealing process to through cleaned described substrate, change the phase of the metal silicide that described grid region, source region and drain region are formed.
6. method as claimed in claim 5, is characterized in that, when depositing described layer of metal, and the value of deposition power and the value negative correlation of described first duration.
7. method as claimed in claim 5, is characterized in that, the temperature value that the material that the value of described first temperature is less than described metal and described insulation layer reacts.
8. the method as described in as arbitrary in claim 5 ~ 7, it is characterized in that, described metal is titanium.
9. a manufacture method for MOS structure, is characterized in that, comprising:
Form source region and drain region in the substrate, and form grid region and insulation layer over the substrate;
Adopt as arbitrary in claim 1 ~ 8 as described in the method making metal silicide in MOS structure, the grid region of described substrate, source region and drain region are formed and change the metal silicide of phase;
Form the oxide layer covering described metal silicide and insulation layer, patterned process is carried out to described oxide layer, and form metal level in the oxide layer after patterned process, to form gate electrode, source electrode and drain electrode respectively.
10. a MOS structure, is characterized in that, this MOS structure is made by method according to claim 9.
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EP0651076B1 (en) * 1993-10-29 1999-08-11 International Business Machines Corporation Method for lowering the phase transformation temperature of a metal silicide
US20020151170A1 (en) * 1996-06-04 2002-10-17 Karen Maex Method of forming polycrystalline CoSi2 salicide and products obtained thereof
US20040201066A1 (en) * 2003-04-08 2004-10-14 Jae-Won Han Method for manufacturing silicide and semiconductor with the silicide

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EP0651076B1 (en) * 1993-10-29 1999-08-11 International Business Machines Corporation Method for lowering the phase transformation temperature of a metal silicide
US20020151170A1 (en) * 1996-06-04 2002-10-17 Karen Maex Method of forming polycrystalline CoSi2 salicide and products obtained thereof
US20040201066A1 (en) * 2003-04-08 2004-10-14 Jae-Won Han Method for manufacturing silicide and semiconductor with the silicide

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107305847A (en) * 2016-04-18 2017-10-31 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method thereof

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