CN107305847A - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN107305847A CN107305847A CN201610240602.3A CN201610240602A CN107305847A CN 107305847 A CN107305847 A CN 107305847A CN 201610240602 A CN201610240602 A CN 201610240602A CN 107305847 A CN107305847 A CN 107305847A
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- metal silicide
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- metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 106
- 239000002184 metal Substances 0.000 claims abstract description 106
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 76
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 63
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000137 annealing Methods 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 35
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims abstract description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 210000004483 pasc Anatomy 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 21
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 9
- 229910021529 ammonia Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000010494 dissociation reaction Methods 0.000 claims description 6
- 230000005593 dissociations Effects 0.000 claims description 6
- 230000002285 radioactive effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000006698 induction Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 33
- 239000012212 insulator Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 8
- 229910008486 TiSix Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 229910005889 NiSix Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- -1 TiSix) 101 Chemical compound 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, and the preparation method includes：Semiconductor substrate is provided, the surface of the Semiconductor substrate includes at least one silicon area；Metal level is formed on the surface of the silicon area；The first annealing process is carried out, so that the metal in the metal level and the pasc reaction in the silicon area, form the first metal silicide；Remove the unreacted remaining metal level；Nitrogen treatment and the second annealing process are carried out to first metal silicide, to form the second metal silicide of nitrogen doped.According to the preparation method of the present invention, by the nitrogen doped in metal silicide, contact resistance is reduced, and then improve the yield and performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Preparation method.
Background technology
In existing MOS transistor technique, in order to improve the grid of transistor, source electrode and
Drain electrode and the Ohmic contact of filling connector, it will usually in grid, source electrode and the surface of drain electrode shape
Into metal silicide.At present, it is to utilize self-aligned metal silicate (Silicidation) mostly
Technique reduces contact resistance to form metal silicide.Forming source electrode and drain electrode
Afterwards, re-form and source electrode, drain and gate top be covered in by metal levels such as cobalt, titanium or nickel,
Then by one or multi-step rta technique (RTA), metal level and grid, source are made
Pasc reaction in pole and drain electrode, forms the metal silicide of low-resistivity, so as to reduce source electrode
With the sheet resistance of drain electrode.
However as semiconductor devices continuous diminution, it is necessary to further reduce contact resistance
To meet the demand of device performance, therefore, it is urgently to be resolved hurrily in the industry for how reducing contact resistance
One of technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Preparation method, this method includes：
Semiconductor substrate is provided, the surface of the Semiconductor substrate includes at least one silicon area；
Metal level is formed on the surface of the silicon area；
The first annealing process is carried out, so that in the metal in the metal level and the silicon area
Pasc reaction, forms the first metal silicide；
Remove the unreacted remaining metal level；
Nitrogen treatment and the second annealing process are carried out to first metal silicide, to be formed
Second metal silicide of nitrogen doped.
Further, it is passed through ammonia to realize the nitrogen while second annealing process is carried out
Change is handled.
Further, the nitrogen treatment is carried out to first metal silicide first, then carried out
Second annealing process.
Further, the nitrogen treatment is the method using nitrogenous plasma nitridation process.
Further, described is to induce dissociation by the ultraviolet radioactive of processing gas containing nitrogen plasma
And formed, or, it is to be dissociated and formed by the Microwave Induced Plasma of the processing gas,
Either formed by the plasma-induced dissociation of the processing gas, wherein, the place
Process gases includes at least one nitrogenous gas.
Further, the nitrogenous gas is combined from nitrogen or ammonia or both.
Further, it is characterised in that second annealing process is moved back from samming annealing, spike
Fire, Millisecond annealing or microwave annealing.
Further, the temperature range of second annealing process is 500~1300 DEG C.
Further, the material of the metal level includes the Ti or Ti/TiN stacked gradually.
Another aspect of the present invention provides a kind of semiconductor devices, including：Semiconductor substrate, institute
The surface for stating Semiconductor substrate includes at least one silicon area, the shape on the surface of the silicon area
Into the metal silicide for having nitrogen doped.
According to the preparation method of the present invention, by the nitrogen doped in metal silicide, obtain
Less contact resistance, and then improve the yield and performance of semiconductor devices.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the diagrammatic cross-section of semiconductor devices according to an embodiment of the present invention；
Fig. 2 shows the step flow chart of preparation method according to an embodiment of the present invention；
Fig. 3 shows the detail flowchart of the preparation method according to the first embodiment of the present invention；
Fig. 4 shows the detail flowchart of preparation method according to the second embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
The semiconductor devices provided in one embodiment of the invention includes Semiconductor substrate, described half
The surface of conductor substrate includes at least one silicon area, is formed with the surface of the silicon area
The metal silicide of nitrogen doped.
The silicon area can include grid, source electrode for different product demand and technological design
The structures such as/drain region, wordline or resistance and the semiconductor for forming Schottky diode
Substrate surface, wherein metal silicide/silicon substrate, which are constituted, to carry out volume to Semiconductor substrate
The Schottky diode of outer doping.
Wherein, Fig. 1 shows that the section of semiconductor devices according to an embodiment of the present invention shows
It is intended to, now by taking structure shown in Fig. 1 as an example, the semiconductor devices of the present invention is retouched in detail
State.
As shown in figure 1, the semiconductor devices of the present invention includes Semiconductor substrate 100, in this hair
Semiconductor substrate 100 described in bright can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, on insulator it is laminated germanium
SiClx (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.Isolation structure is also formed with Semiconductor substrate 100, the isolation structure is shallow trench
Isolate (STI) structure or selective oxidation silicon (LOCOS) isolation structure.The Semiconductor substrate
The channel layer of various traps (well) structure and substrate surface is also formed with 100.In general, shape
Into the ion doping conduction type and channel layer ion doping conduction type phase of trap (well) structure
Together, but concentration is low compared with gate channel layer, the depth of ion implanting is general to enclose relatively wide, while need to reach
To the depth more than isolation structure.To put it more simply, herein only with a blank semiconductor substrate 100
Diagram.
In one example, MOS device is formed with a semiconductor substrate 100, the MOS
Device includes the grid structure 102 being formed in Semiconductor substrate 100, is formed at grid structure
Sidewall structure 103 on 102 two sides, and it is formed at partly leading for the grid structure both sides
Regions and source/drain in body substrate 100, wherein regions and source/drain are silicon area.
Grid structure 102 typically may include gate dielectric and grid layer, and grid layer is formed at grid
On the dielectric layer of pole.In one example, grid layer is made up of polycrystalline silicon material, typically can also be used
Metal, metal nitride, metal silicide or similar compound as grid layer material.
Sidewall structure 103 can include at least one layer of oxide skin(coating) and/or at least one layer of nitride
Layer.It should be noted that sidewall structure 103 is optional rather than required, it is mainly used in
Be subsequently etched or during ion implanting protection grid structure side wall it is injury-free.
Regions and source/drain can be by Semiconductor substrate progress N-type or p-type ion implanting
Formed.
In one example, it is formed with nitrogen doped on the surface of regions and source/drain
Metal silicide 101.
Exemplarily, the material of the metal silicide can include but is not limited to TiSix, NiSix
Or CoSix, or other suitable metal silicide materials are equally applicable to the present invention.And it is golden
Belong in silicide doped with nitrogen, for example, may be constructed TiSixN, NiSixN or CoSixN.
In one example, when the material of the grid structure is polysilicon, in grid structure
Top surface on can also be formed with the metal silicide of nitrogen doped.
It can also include other composed components for complete semiconductor devices, not go to live in the household of one's in-laws on getting married herein
State.
In summary, semiconductor devices of the invention includes the metal silicide of nitrogen-doping,
Contact resistance is reduced, therefore the semiconductor devices has higher performance, when the semiconductor device
When part is Schottky diode, because the metal silicide of nitrogen-doping reduces contact electricity
Resistance, correspondingly reduces schottky barrier height, and then the performance of Schottky diode is obtained
Improve.
In order to obtain foregoing semiconductor device structure, present invention also offers a kind of semiconductor device
The preparation method of part, as shown in Fig. 2 the key step of the preparation method includes：
Step S201 is there is provided Semiconductor substrate, and the surface of the Semiconductor substrate is comprising at least
One silicon area；
Step S202, metal level is formed on the surface of the silicon area；
Step S203, carries out the first annealing process, so that metal and institute in the metal level
The pasc reaction in silicon area is stated, the first metal silicide is formed；
Step S204, removes the unreacted remaining metal level；
Step S205, nitrogen treatment and the second annealing are carried out to first metal silicide
Technique, to form the second metal silicide of nitrogen doped.
The silicon area can include grid, source electrode for different product demand and technological design
The structures such as/drain region, wordline or resistance and the semiconductor for forming Schottky diode
Substrate surface, wherein metal silicide/silicon substrate, which are constituted, to carry out volume to Semiconductor substrate
The Schottky diode of outer doping.
The semiconductor devices formed by above-mentioned manufacture method of the present invention includes nitrogen-doping
Metal silicide, reduce contact resistance, therefore the semiconductor devices has higher performance,
When the semiconductor devices is Schottky diode, because the metal silicide of nitrogen-doping drops
Low contact resistance, correspondingly reduces schottky barrier height, and then cause Schottky diode
Performance be improved.
Embodiment one
Below with reference to Fig. 1 and Fig. 3 to the semiconductor devices of the first embodiment of the present invention
Preparation method is described in detail, and Fig. 3 shows the making side according to the first embodiment of the present invention
The detail flowchart of method.
According to a first embodiment of the present invention, the preparation method of semiconductor devices of the invention is specifically wrapped
Include following steps：
First there is provided Semiconductor substrate, the surface of the Semiconductor substrate includes at least one silicon
Region.
Specifically, as shown in figure 1, in the present invention the Semiconductor substrate 100 can be with
Under at least one of the material that is previously mentioned：Silicon, silicon-on-insulator (SOI), insulator upper strata
Stacking SiGe (S-SiGeOI), germanium on insulator SiClx on folded silicon (SSOI), insulator
And germanium on insulator (GeOI) etc. (SiGeOI).Shape is gone back in Semiconductor substrate 100
Into there is isolation structure, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation
Silicon (LOCOS) isolation structure.Various traps (well) are also formed with the Semiconductor substrate 100
The channel layer of structure and substrate surface.In general, the ion doping of trap (well) structure is formed
Conduction type is identical with channel layer ion doping conduction type, but concentration is compared with gate channel layer
Low, the depth of ion implanting is general to enclose relatively wide, while the depth more than isolation structure need to be reached.For
Simplification, is herein only illustrated with a blank semiconductor substrate 100.
The silicon area can include grid, source electrode for different product demand and technological design
The structures such as/drain region, wordline or resistance and the semiconductor for forming Schottky diode
Substrate surface, wherein metal silicide/silicon substrate, which are constituted, to carry out volume to Semiconductor substrate
The Schottky diode of outer doping.
In one example, MOS device is formed with a semiconductor substrate 100, the MOS
Device includes the grid structure 102 being formed in Semiconductor substrate 100, is formed at grid structure
Sidewall structure 103 on 102 two sides, and it is formed at partly leading for the grid structure both sides
Regions and source/drain in body substrate 100, wherein regions and source/drain are silicon area.
Grid structure 102 typically may include gate dielectric and grid layer, and grid layer is formed at grid
On the dielectric layer of pole.In one example, grid layer is made up of polycrystalline silicon material, typically can also be used
Metal, metal nitride, metal silicide or similar compound as grid layer material.
Sidewall structure 103 can include at least one layer of oxide skin(coating) and/or at least one layer of nitride
Layer.It should be noted that sidewall structure is optional rather than required, it is mainly used in rear
It is continuous be etched or during ion implanting protection grid structure side wall it is injury-free.
Regions and source/drain can be by Semiconductor substrate progress N-type or p-type ion implanting
Formed.
Then, prerinse is carried out to Semiconductor substrate.
Because the metal silicide containing cobalt, nickel or titanium is more sensitive to silicon face, if silicon table
There are pollutant or oxide in face, can influence the performance for the metal silicide to be formed, such as resistance
Rate.Thus before deposited metal layer, prerinse can be carried out to substrate, to remove depollution
Thing or oxide.According to an aspect of the present invention, 100 can be used：1 H2O and
HF solution is cleaned to semiconductor substrate surface.
Then, metal level is formed on the surface of the silicon area.
Exemplarily, the regions and source/drain on deposited metal layer covering semiconductor substrate surface.
In one example, when the material of the grid structure is polysilicon, the metal level can also shape
Into on the top surface of grid structure.The material of metal level can include but is not limited to Ti, Ni,
The Co or Ti/TiN stacked gradually.TiN is also optionally used as the guarantor of metal level
Sheath.Physical vapour deposition (PVD) (PVD), sputtering method, vapour deposition method or chemical vapor deposition can be used
The methods such as product form the metal level.
Then, the first annealing process is carried out, so that the metal in the metal level and the silicon area
Pasc reaction in domain, forms the first metal silicide.
Exemplarily, the first annealing process is carried out to the Semiconductor substrate comprising metal level.Pass through
Metal (such as Ti) and the silicon of source electrode and drain surface in first annealing process, metal level is anti-
Should, form the first metal silicide TiSix.Now the first annealing process uses process annealing work
Skill, such as annealing region are 210 DEG C~350 DEG C.The first metal silicide formed is height
Hinder phase metal silicide.Because resistivity is higher, be not suitable for directly as contact layer, therefore also
Follow-up step reduction resistivity need to be carried out, to reduce filling connector and source, leakage, grid table
The contact resistance in face, improves device performance and reduces power consumption.
First annealing process can select samming annealing, spike annealing, Millisecond annealing or microwave
Annealing etc., above-mentioned method for annealing is not only construed as limiting the invention as example, for it
Its suitable method for annealing is applied equally to the present invention.
Exemplarily, the first annealing process is carried out in the environment of anaerobic, for example, the first annealing
Technique can also be carried out in a nitrogen atmosphere, and the nitrogen can also use the indifferent gas such as helium or argon gas
Body.
Then, the unreacted remaining metal level is removed.
Can be by having wet etching method removal with high selectivity unreacted to metal level
Metal level.Exemplarily, the corrosive liquid of wet etching is using the mixed of sulfuric acid and hydrogen peroxide (SPM)
Close solution, or aqua ammonia and hydrogen peroxide (SC1) the aqueous solution and phosphoric acid, nitric acid and formic acid
(MII) mixed solution.After etching, remaining first metal silication on source/drain surface
Thing.
In one example, when being formed with such as TiN protective layer on the metal layer, walk herein
Need to remove in the lump in rapid.
Then, ammonia is passed through to realize nitrogen treatment while the second annealing process is carried out, enter
And the second metal silicide is formed, make in second metal silicide doped with nitrogen.
Second metal silicide is low-resistance phase metal silicide.It is by the second annealing process by
The high resistant inversion of phases of one metal silicide is the low-resistance phase of the second metal silicide, reduces resistance
Rate.Exemplarily, the temperature range of second annealing process is 500~1300 DEG C, described
Second annealing process can select samming annealing, spike annealing, Millisecond annealing or microwave annealing
Deng above-mentioned method for annealing is not only construed as limiting the invention as example, for other suitable
The method for annealing of conjunction is applied equally to the present invention.Wherein, because the decomposition temperature of ammonia is relatively low,
Therefore within the temperature range of the second annealing process, ammonia can dissociate free radical, Jin Er
Nitrogen-doping has been carried out to the second metal silicide while forming the second metal silicide.
Complete after above-mentioned steps, semiconductor device structure as described in Figure 1 is obtained, in grid knot
The second metal silicide is formd on the surface of the regions and source/drain of the both sides of structure 102 (for example
TiSix) 101, doped with nitrogen in second metal silicide 101.The present invention's passes through
The semiconductor devices of above-mentioned manufacture method formation includes the metal silicide of nitrogen-doping, reduces
Contact resistance, therefore the semiconductor devices has higher performance, when the semiconductor devices is
During Schottky diode, because the metal silicide of nitrogen-doping reduces contact resistance, phase
Schottky barrier height should be reduced, and then the performance of Schottky diode is improved.
Embodiment two
Below with reference to Fig. 1 and Fig. 4 to the semiconductor devices of the second embodiment of the present invention
Preparation method is described in detail, and Fig. 4 shows making side according to the second embodiment of the present invention
The detail flowchart of method.
According to a second embodiment of the present invention, the preparation method of semiconductor devices of the invention is specifically wrapped
Include following steps：
First there is provided Semiconductor substrate, the surface of the Semiconductor substrate includes at least one silicon
Region；Prerinse is carried out to Semiconductor substrate；Metal level is formed on the surface of the silicon area；
The first annealing process is carried out, so that the metal in the metal level and silicon in the silicon area are anti-
Should, form the first metal silicide；Remove the unreacted remaining metal level；First to institute
State the first metal silicide and carry out the nitrogen treatment, then carry out second annealing process, with
Form the second metal silicide and the N doping to metal silicide.
The silicon area can include grid, source electrode for different product demand and technological design
The structures such as/drain region, wordline or resistance and the semiconductor for forming Schottky diode
Substrate surface, wherein metal silicide/silicon substrate, which are constituted, to carry out volume to Semiconductor substrate
The Schottky diode of outer doping.
For step identical with aforementioned first embodiment in second embodiment herein no longer
Repeat.
Difference step in second embodiment with aforementioned first embodiment is essentially consisted in：First to described
First metal silicide carries out the nitrogen treatment, then carries out second annealing process.
Exemplarily, the nitrogen treatment is the side using nitrogenous plasma nitridation process
Method.Described can be dissociated and shape by the ultraviolet radioactive induction of processing gas containing nitrogen plasma
Into or by the processing gas Microwave Induced Plasma dissociation and formed, or
Person is formed by the plasma-induced dissociation of the processing gas, wherein, the processing
Gas includes at least one nitrogenous gas.Further, the nitrogenous gas can from nitrogen or
Person's ammonia or both is combined, or other suitable nitrogenous gas.
Exemplarily, the temperature range of second annealing process is 500~1300 DEG C, for
Other suitable annealing temperatures are equally applicable to the present invention.
Further, the second annealing process is carried out in the environment of anaerobic, for example, the second lehr attendant
Skill can be carried out in a nitrogen atmosphere, can also be carried out under the inert gas atmosphere such as helium or argon gas.
Complete after the step in second embodiment, can also obtain semiconductor devices as described in Figure 1
Structure, the second gold medal is formd on the surface of the regions and source/drain of the both sides of grid structure 102
Belong in silicide (such as TiSix) 101, second metal silicide 101 doped with nitrogen.
It is worth noting that, the preparation method of the present invention goes in finfet technology
The making of TiSix/Si Schottky diodes.By the preparation method of the present invention, in TiSix
Nitrogen doped, reduces schottky barrier height, can improve the pole of TiSix/Si Schottky two
The performance of pipe.
It is understood that either in first embodiment or second embodiment in semiconductor
Device manufacture method not only include above-mentioned steps, before above-mentioned steps, among or may be used also afterwards
Including other desired step, it is included in the range of this implementation preparation method.
In summary, according to the preparation method of the present invention, the nitrogen that adulterated in metal silicide is passed through
Element, reduces contact resistance, therefore improve the performance and yield of device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided, the surface of the Semiconductor substrate includes at least one silicon area；
Metal level is formed on the surface of the silicon area；
The first annealing process is carried out, so that in the metal in the metal level and the silicon area
Pasc reaction, forms the first metal silicide；
Remove the unreacted remaining metal level；
Nitrogen treatment and the second annealing process are carried out to first metal silicide, to be formed
Second metal silicide of nitrogen doped.
2. preparation method according to claim 1, it is characterised in that described in carrying out
Ammonia is passed through while second annealing process to realize the nitrogen treatment.
3. preparation method according to claim 1, it is characterised in that first to described
First metal silicide carries out the nitrogen treatment, then carries out second annealing process.
4. preparation method according to claim 3, it is characterised in that at the nitridation
Manage as using the method for nitrogenous plasma nitridation process.
5. preparation method according to claim 4, it is characterised in that described nitrogenous etc.
Gas ions are to be dissociated and formed by the ultraviolet radioactive induction of processing gas, or, it is by institute
State the Microwave Induced Plasma dissociation of processing gas and formed, or pass through the processing gas
The plasma-induced dissociation of body and formed, wherein, the processing gas contains including at least one
Nitrogen.
6. preparation method according to claim 5, it is characterised in that described to contain nitrogen
Body is combined from nitrogen or ammonia or both.
7. preparation method according to any one of claim 1 to 6, it is characterised in that
Second annealing process selects samming annealing, spike annealing, Millisecond annealing or microwave annealing.
8. preparation method according to claim 1, it is characterised in that described second moves back
The temperature range of ignition technique is 500~1300 DEG C.
9. preparation method according to claim 1, it is characterised in that the metal level
Material include the Ti or Ti/TiN that stacks gradually.
10. a kind of semiconductor devices, it is characterised in that including：Semiconductor substrate, described half
The surface of conductor substrate includes at least one silicon area, is formed with the surface of the silicon area
The metal silicide of nitrogen doped.
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| US20040188240A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for in-situ nitridation of salicides |
| CN101312231A (en) * | 2007-05-24 | 2008-11-26 | 财团法人工业技术研究院 | Phase change memorizer apparatus and method of manufacture |
| CN104779271A (en) * | 2014-01-09 | 2015-07-15 | 北大方正集团有限公司 | MOS structure, manufacturing method thereof and metal silicide manufacturing method |
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| US5536684A (en) * | 1994-06-30 | 1996-07-16 | Intel Corporation | Process for formation of epitaxial cobalt silicide and shallow junction of silicon |
| US20040188240A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for in-situ nitridation of salicides |
| CN101312231A (en) * | 2007-05-24 | 2008-11-26 | 财团法人工业技术研究院 | Phase change memorizer apparatus and method of manufacture |
| CN104779271A (en) * | 2014-01-09 | 2015-07-15 | 北大方正集团有限公司 | MOS structure, manufacturing method thereof and metal silicide manufacturing method |
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