CN104766074B - A kind of voltage bias type fingerprint recognition system of logic-based enhanced processing - Google Patents
A kind of voltage bias type fingerprint recognition system of logic-based enhanced processing Download PDFInfo
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- CN104766074B CN104766074B CN201510217200.7A CN201510217200A CN104766074B CN 104766074 B CN104766074 B CN 104766074B CN 201510217200 A CN201510217200 A CN 201510217200A CN 104766074 B CN104766074 B CN 104766074B
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Abstract
The invention discloses a kind of voltage bias type fingerprint recognition system of logic-based enhanced processing, by single-chip microcomputer（1）, fingerprint signal acquisition module（6）, with uniprocessor（1）The pre-stored module being connected（2）, wireless transmitter module（3）, video camera（4）, alarm（5）, triode bias processing module（8）, and with triode bias processing module（8）The power module being connected（7）Composition；It is characterized in that：In fingerprint signal acquisition module（6）With single-chip microcomputer（1）Between be additionally provided with logic enhanced processing module（9）；The present invention can carry out logic enhanced processing to the fingerprint signal collected, and therefore, even if the fingerprint signal that fingerprint signal acquisition module is collected is weaker, accurately fingerprint signal can also be identified for fingerprint recognition system.
Description
Technical field
The present invention relates to fingerprint recognition field, in particular to a kind of voltage bias type fingerprint recognition system of logic-based enhanced processing
System.
Background technology
Traditional identity identifying method includes identity article identification (such as key, certificate, atm card) and identity
Knowledge identifies (such as username and password).But above-mentioned authentication method is mainly by external thing, once prove the marking articles of identity
It is stolen or forgets with mark knowledge, its identity is easy for being pretended to be or being substituted by other people.In order to solve this problem, biological identification technology
Just arise at the historic moment, it passes through the high-tech means such as computer and optics, acoustics, biology sensor and biostatistics principle is close
Combination is cut, the identification of personal identification is carried out using the intrinsic physiological property of human body and behavioral trait.Particularly, fingerprint recognition obtains
Widest application is arrived.
Fingerprint recognition analyzes fingerprint characteristic indeed through specific mathematical algorithm, and judges two groups of fingerprint characteristics
Similarity, it includes two big processes of fingerprint characteristic analysis and matching.Fingerprint image is more complicated, and it has many to be different from it
The feature of its image.Therefore, it is necessary to carry out substantial amounts of data operation and data storage in identification process, its place to processor
Reason function and running environment have very high requirement.Wet finger can be run into unavoidably in fingerprint identification process, that is, come in and go out personnel's hand
It is wet, the fingerprint signal that at this moment fingerprint recognition system can collect is weaker, largely have impact on fingerprint recognition
Precision, fingerprint recognition system None- identified, or the situation of wrong identification is often occurred, bring very big trouble.
The content of the invention
It is an object of the invention to overcome traditional fingerprint recognition system its accuracy of identification when running into wet finger not high
A kind of defect, there is provided voltage bias type fingerprint recognition system of logic-based enhanced processing.
The purpose of the present invention is achieved through the following technical solutions：A kind of voltage bias type fingerprint recognition of logic-based enhanced processing
System, by single-chip microcomputer, fingerprint signal acquisition module, the pre-stored module being connected with uniprocessor, wireless transmitter module, shooting
Machine, alarm, triode bias processing module, and the power module being connected with triode bias processing module, in fingerprint
Logic enhanced processing module is additionally provided between signal acquisition module and single-chip microcomputer.
Further, described logic enhanced processing module is by amplifier P1, and amplifier P2, triode VT3, negative pole is through electricity
It is connected after resistance R12 with amplifier P1 positive pole, positive pole then inputs the polarity of pole as one of the logic enhanced processing module
Electric capacity C10, resistance R13, the P pole being serially connected between amplifier P1 positive pole and output end is connected with amplifier P1 positive pole, N
Diode D11, the N pole that pole is then connected with triode VT3 emitter stage is connected with amplifier P1 negative pole, P poles are then through pole
Property electric capacity C11 after the diode D9 that is grounded, N poles are connected after polar capacitor C12 with amplifier P1 output end, P poles ground connection
Diode D10, the resistance that one end is connected with amplifier P1 output end, the other end is then connected with amplifier P2 positive pole
R14, and the resistance R15 compositions being serially connected between amplifier P2 positive pole and output end；The base stage of the triode VT3 is with putting
Big device P1 output end is connected, output end of its colelctor electrode then with amplifier P2 is connected；The negative pole of the amplifier P2 point
P poles not with diode D9 and diode D10 are connected.The P poles of the diode D9 are as the logic enhanced processing module 9
Another input pole, and it forms the input of the logic enhanced processing module 9 together with polar capacitor C10 positive pole；It is described
Triode VT3 emitter stage then forms the output end of the logic enhanced processing module 9 together with amplifier P2 output end.
Described triode bias processing module is by voltage detecting circuit, the bias processing being connected with voltage detecting circuit
Circuit, and formed with the transforming circuit that bias process circuit is connected.
Described voltage detecting circuit is by FET Q, and negative pole is connected with FET Q grid, positive pole then conduct
The polar capacitor C1 of one input pole of the voltage detecting circuit, process circuit is connected negative pole, positive pole then sequentially passes through with bias
The polar capacitor C2 being connected after resistance R4 and resistance R1 with FET Q grid, positive pole are connected with FET Q source electrode
Connect, the polar capacitor C3 that negative pole is then connected after resistance R2 with FET Q grid, the resistance being in parallel with resistance R2
R3, one end is connected with FET Q source electrode, the resistance R5 compositions of other end ground connection；The company of the resistance R1 and resistance R4
Contact is connected with bias process circuit, and FET Q drain electrode is connected with polar capacitor C2 positive pole, polar capacitor C3's
Negative pole is also connected with bias process circuit.Meanwhile polar capacitor C3 negative pole is as the voltage detecting circuit（81）It is another
One input pole, and it forms the voltage detecting circuit together with polar capacitor C1 positive pole（81）Input.
Described bias process circuit is by process chip U, triode VT1, triode VT2, and positive pole is with process chip U's
The polar capacitor C4 that HIN pins are connected, negative pole is then connected with process chip U SD pins, one end is with process chip U's
Resistance R6, the N pole that LIN pins are connected, the other end is then connected with polar capacitor C3 negative pole and process chip U SD pins
Be connected, diode D1, N pole that P poles are then connected with process chip U COM pins after resistance R9 with process chip U's
The voltage-regulator diode D2 that VCC pins are connected, P poles are then connected with diode D1 P poles, the N of positive pole and voltage-regulator diode D2
The polar capacitor C7 that pole is connected, negative pole is then connected with triode VT2 colelctor electrode, one end and process chip U LO pins
It is connected, resistance R8, the N pole that the other end is then connected with triode VT2 base stage is connected with triode VT1 emitter stage, P
The diode D3 that pole is then sequentially connected after polar capacitor C6 and polar capacitor C5 with process chip U VB pins, one end with
The resistance R7 that process chip U HO pins are connected, the other end is then connected with triode VT1 base stage, and N poles and processing
The diode D4 compositions that chip U VB pins are connected, P poles are then connected with triode VT1 colelctor electrode；The process chip
U VDD pins are connected with resistance R1 and resistance R4 tie point, its HIN pin is then connected with polar capacitor C2 negative pole,
VSS pins are connected with diode D1 N poles, VS pins are then connected with diode D3 P poles, HO pins and polar capacitor C6
It is connected with polar capacitor C5 tie point；The colelctor electrode of the triode VT1 is connected with transforming circuit, its emitter stage then with
Triode VT2 emitter stage is connected；The colelctor electrode of the triode VT2 respectively with voltage-regulator diode D2 P poles and transformation
Circuit is connected.
Described transforming circuit is by transformer T, and unidirectional thyristor D5, unidirectional thyristor D7, N pole is with unidirectional thyristor D5's
Two poles that control pole is connected, P poles are then sequentially connected after resistance R10 and polar capacitor C8 with unidirectional thyristor D5 P poles
Pipe D6, the resistance R11 that one end is connected with unidirectional thyristor D5 P poles, the other end is then connected with unidirectional brilliant lock D7 P poles,
And positive pole is connected with transformer T secondary inductance coils L2 Same Name of Ends, negative pole then after voltage-regulator diode D8 with transformer T
The polar capacitor C9 compositions that secondary inductance coil L3 non-same polarity is connected；The P poles of the unidirectional thyristor D5 and diode
D4 P poles are connected, its N pole ground connection, unidirectional thyristor D7 N poles ground connection, control pole and polar capacitor C8 and resistance R10 company
Contact is connected；The P poles of the diode D6 are connected with diode D1 P poles；The transformer T primary side inductance coils L1's
Same Name of Ends is connected with unidirectional thyristor D5 P poles, its non-same polarity is then connected with diode D6 P poles, transformer T secondary
Inductance coil L2 non-same polarity is connected with transformer T secondary inductance coils L3 Same Name of Ends.
Described process chip U is IR2110 integrated circuits.
The triode VT1 and triode VT2 are negative-positive-negative transistor.
The present invention compared with the prior art, has advantages below and beneficial effect：
（1）The triode bias processing module of the present invention can carry out bias processing to the operating voltage of identifying system, from
And improve the accuracy of identification of the present invention.
（2）Using IR2110 integrated circuits as process chip, it is used in conjunction with the present invention with reference to triode, makes at bias
The speed of reason is faster.
（3）The present invention can carry out logic enhanced processing to the fingerprint signal collected, therefore, even if fingerprint signal gathers
The fingerprint signal that module is collected is weaker, and accurately fingerprint signal can also be identified for fingerprint recognition system.
Brief description of the drawings
Fig. 1 is the overall structure diagram of the present invention；
The triode that Fig. 2 is the present invention biases processing module electrical block diagram；
Fig. 3 is the logic enhanced processing modular circuit structural representation of the present invention.
Reference in the figures above is entitled：
1-single-chip microcomputer, 2-it is pre-stored module, 3-wireless transmitter module, 4-video camera, 5-alarm, 6-fingerprint letter
Number acquisition module, 7-power module, 8-triode bias processing module, 81-voltage detecting circuit, 82-bias processing electricity
Road, 83-transforming circuit, 9-logic enhanced processing module.
Embodiment
The present invention is described in further detail with reference to embodiment, but embodiments of the present invention are not limited to
This.
Embodiment
As shown in figure 1, the present invention is by single-chip microcomputer 1, the pre-stored module 2 being connected with uniprocessor 1, wireless transmitter module
3rd, video camera 4, alarm 5, logic enhanced processing module 9, triode bias processing module 8, processing module 8 is biased with triode
The power module 7 being connected, and formed with the fingerprint signal acquisition module 6 that logic enhanced processing module 9 is connected.
Wherein, control centre of the single-chip microcomputer 1 as fingerprint recognition system, pre-stored module 2 are used to store normally to go out in advance
Enter the fingerprint signal of personnel.Fingerprint signal acquisition module 6 is used for the fingerprint signal for gathering discrepancy personnel, logic enhanced processing module
9 fingerprint signals for being used to fingerprint signal acquisition module 6 be collected carry out logic enhanced processing, the fingerprint signal after processing
Become apparent from.And power module 7 is then used to provide power supply to fingerprint recognition system, the power supply biases processing module 8 through triode
Single-chip microcomputer 1 is conveyed to after doing bias processing.
During work, as long as discrepancy personnel are placed on its finger on fingerprint signal acquisition module 6, fingerprint signal acquisition module 6
Its fingerprint signal can be then acquired automatically and be sent to single-chip microcomputer 1.If the hand of the personnel of discrepancy is wet, at this moment fingerprint is believed
The fingerprint signal that number acquisition module 6 is collected is then weaker, and at this moment logic enhanced processing module 9 can be then patrolled fingerprint signal
Enhanced processing is collected, becomes apparent from fingerprint signal.Fingerprint signal is then sent to pre-stored module 2 by single-chip microcomputer 1, is pre-stored module
2 fingerprint signals that fingerprint signal is internal with having previously been stored in it are matched, the fingerprint recognition success if successful matching.Such as
Fruit pairing is unsuccessful, and pre-stored module 2 then sends a signal to single-chip microcomputer 1, and start video camera 4 by single-chip microcomputer 1 enters to disengaging personnel
Row shooting, while start alarm 5 and alarm, and wireless transmitter module 3 is then sent to disengaging personnel's image by wireless network
The computer of rear end is stored, if the image storage of same personnel must be more, targetedly the personnel can be carried out
Pay close attention to.
The fingerprint signal acquisition module 6 is preferentially from the FL-727-FV types of Shanghai Ferly Digital Technologies Co., Ltd.'s production
Fingerprint acquisition instrument, it has good applicability to wet finger, dirty finger, damaged finger.It is and power module 7, single-chip microcomputer meeting, pre-
Memory module 2, wireless transmitter module 3, video camera 4 and alarm 5 can be achieved using prior art.
As shown in Fig. 2 triode biases processing module 8 by voltage detecting circuit 81, it is connected with voltage detecting circuit 81
Bias process circuit 82, and formed with the transforming circuit 83 that is connected of bias process circuit 82.
Voltage detecting circuit 81 therein is by FET Q, and negative pole is connected with FET Q grid, positive pole is then made
For one of the voltage detecting circuit 81 polar capacitor C1 for inputting pole, negative pole is connected with biasing process circuit 82, positive pole then
The polar capacitor C2 being sequentially connected after resistance R4 and resistance R1 with FET Q grid, the source of positive pole and FET Q
The polar capacitor C3 that pole is connected, negative pole is then connected after resistance R2 with FET Q grid, it is in parallel with resistance R2
Resistance R3, one end is connected with FET Q source electrode, the resistance R5 compositions of other end ground connection.The resistance R1 and resistance R4
Tie point be connected with bias process circuit 82, FET Q drain electrode is connected with polar capacitor C2 positive pole, and polarity is electric
The negative pole for holding C3 is also connected with bias process circuit 82.Meanwhile polar capacitor C3 negative pole is as the voltage detecting circuit
81 another input pole, and it forms the input of the voltage detecting circuit 81 together with polar capacitor C1 positive pole.
Described bias process circuit 82 is then by process chip U, triode VT1, triode VT2, positive pole and process chip U
HIN pins be connected, the polar capacitor C4 that negative pole is then connected with process chip U SD pins, one end and process chip U's
Resistance R6, the N pole that LIN pins are connected, the other end is then connected with polar capacitor C3 negative pole and process chip U SD pins
Be connected, diode D1, N pole that P poles are then connected with process chip U COM pins after resistance R9 with process chip U's
The voltage-regulator diode D2 that VCC pins are connected, P poles are then connected with diode D1 P poles, the N of positive pole and voltage-regulator diode D2
The polar capacitor C7 that pole is connected, negative pole is then connected with triode VT2 colelctor electrode, one end and process chip U LO pins
It is connected, resistance R8, the N pole that the other end is then connected with triode VT2 base stage is connected with triode VT1 emitter stage, P
The diode D3 that pole is then sequentially connected after polar capacitor C6 and polar capacitor C5 with process chip U VB pins, one end with
The resistance R7 that process chip U HO pins are connected, the other end is then connected with triode VT1 base stage, and N poles and processing
The diode D4 compositions that chip U VB pins are connected, P poles are then connected with triode VT1 colelctor electrode；The process chip
U VDD pins are connected with resistance R1 and resistance R4 tie point, its HIN pin is then connected with polar capacitor C2 negative pole,
VSS pins are connected with diode D1 N poles, VS pins are then connected with diode D3 P poles, HO pins and polar capacitor C6
It is connected with polar capacitor C5 tie point.The colelctor electrode of the triode VT1 is connected with transforming circuit 83, its emitter stage then
It is connected with triode VT2 emitter stage.The colelctor electrode of the triode VT2 respectively with voltage-regulator diode D2 P poles and change
Volt circuit 83 is connected.In order to ensure the implementation result of the present invention, process chip U is preferentially using IR2110 integrated circuits come real
It is existing, and triode VT1 and triode VT2 are then preferentially realized using negative-positive-negative transistor.
Described transforming circuit 83 is by transformer T, unidirectional thyristor D5, unidirectional thyristor D7, N pole and unidirectional thyristor D5
Control pole be connected, two that P poles are then sequentially connected after resistance R10 and polar capacitor C8 with unidirectional thyristor D5 P poles
Pole pipe D6, the resistance that one end is connected with unidirectional thyristor D5 P poles, the other end is then connected with unidirectional brilliant lock D7 P poles
R11, and positive pole is connected with transformer T secondary inductance coils L2 Same Name of Ends, negative pole then after voltage-regulator diode D8 with change
The polar capacitor C9 compositions that depressor T secondary inductance coils L3 non-same polarity is connected；The P poles and two of the unidirectional thyristor D5
Pole pipe D4 P poles are connected, its N pole ground connection, unidirectional thyristor D7 N poles ground connection, control pole and polar capacitor C8 and resistance R10
Tie point be connected；The P poles of the diode D6 are connected with diode D1 P poles；The transformer T primary side inductance coils
L1 Same Name of Ends is connected with unidirectional thyristor D5 P poles, its non-same polarity is then connected with diode D6 P poles, transformer T
Secondary inductance coil L2 non-same polarity is connected with transformer T secondary inductance coils L3 Same Name of Ends.The polar capacitor C9
Positive pole and negative pole together as circuit output end.
Logic enhanced processing module 9 is then the emphasis place of the present invention, as shown in figure 3, it is by amplifier P1, amplifier
P2, triode VT3, negative pole is connected after resistance R12 with amplifier P1 positive pole, positive pole is then used as the logic enhanced processing mould
The polar capacitor C10 of one of block 9 input pole, be serially connected in resistance R13, P pole between amplifier P1 positive pole and output end with
Diode D11, the N pole that amplifier P1 positive pole is connected, N poles are then connected with triode VT3 emitter stage and amplifier P1
Negative pole be connected, diode D9, N pole that P poles are then grounded after polar capacitor C11 after polar capacitor C12 with amplifier P1
Output end be connected, P poles ground connection diode D10, one end is connected with amplifier P1 output end, the other end then with amplification
The resistance R14 that device P2 positive pole is connected, and the resistance R15 compositions being serially connected between amplifier P2 positive pole and output end.
The base stage of the triode VT3 is connected with amplifier P1 output end, output end of its colelctor electrode then with amplifier P2 is connected
Connect.P pole of the negative pole of the amplifier P2 respectively with diode D9 and diode D10 is connected.Make the P poles of the diode D9
Pole is inputted for another of the logic enhanced processing module 9, and it forms logic amplification together with polar capacitor C10 positive pole
The input of processing module 9；The emitter stage of the triode VT3 then forms logic amplification together with amplifier P2 output end
The output end of processing module 9.
As described above, the present invention can be realized well.
Claims (5)
- A kind of 1. voltage bias type fingerprint recognition system of logic-based enhanced processing, by single-chip microcomputer (1), fingerprint signal acquisition module (6) the pre-stored module (2) that, is connected with uniprocessor (1), wireless transmitter module (3), video camera (4), alarm (5), three Pole pipe bias processing module (8), and the power module (7) being connected with triode bias processing module (8) form；Its feature It is：Logic enhanced processing module (9) is additionally provided between fingerprint signal acquisition module (6) and single-chip microcomputer (1)；Described patrols Volume enhanced processing module (9) by amplifier P1, amplifier P2, triode VT3, negative pole after resistance R12 with amplifier P1 just Pole is connected, positive pole then inputs the polar capacitor C10 of pole as one of the logic enhanced processing module (9), is serially connected in amplification Resistance R13, P pole between device P1 positive pole and output end is connected with amplifier P1 positive pole, N poles are then with triode VT3's Diode D11, the N pole that emitter stage is connected is connected with amplifier P1 negative pole, P poles are then grounded after polar capacitor C11 Diode D9, N pole is connected after polar capacitor C12 with amplifier P1 output end, P poles ground connection diode D10, one end with The resistance R14 that amplifier P1 output end is connected, the other end is then connected with amplifier P2 positive pole, and it is serially connected in amplification Resistance R15 compositions between device P2 positive pole and output end；The base stage of the triode VT3 is connected with amplifier P1 output end Connect, output end of its colelctor electrode then with amplifier P2 is connected；The negative pole of the amplifier P2 respectively with diode D9 and two poles Pipe D10 P poles are connected；Another input pole of the P poles of the diode D9 as the logic enhanced processing module (9), and It forms the input of the logic enhanced processing module (9) together with polar capacitor C10 positive pole；The hair of the triode VT3 Emitter-base bandgap grading then forms the output end of the logic enhanced processing module (9) together with amplifier P2 output end；Described triode is inclined Processing module (8) is pressed by voltage detecting circuit (81), the bias process circuit (82) being connected with voltage detecting circuit (81), with And the transforming circuit (83) being connected with bias process circuit (82) forms；Described voltage detecting circuit (81) is by FET Q, and negative pole is connected with FET Q grid, positive pole then conduct The polar capacitor C1 of one input pole of the voltage detecting circuit (81), negative pole is connected with bias process circuit (82), positive pole The polar capacitor C2 being then sequentially connected after resistance R4 and resistance R1 with FET Q grid, positive pole is with FET Q's The polar capacitor C3 that source electrode is connected, negative pole is then connected after resistance R2 with FET Q grid, is in parallel with resistance R2 Resistance R3, one end is connected with FET Q source electrode, the other end ground connection resistance R5 composition；The resistance R1 and resistance R4 tie point is connected with bias process circuit (82), and FET Q drain electrode is connected with polar capacitor C2 positive pole, pole Property electric capacity C3 negative pole be also connected with bias process circuit (82)；Meanwhile polar capacitor C3 negative pole is examined as the voltage Another input pole of slowdown monitoring circuit (81), and it forms the defeated of the voltage detecting circuit (81) together with polar capacitor C1 positive pole Enter end.
- A kind of 2. voltage bias type fingerprint recognition system of logic-based enhanced processing according to claim 1, it is characterised in that： Described bias process circuit (82) is managed by process chip U, triode VT1, triode VT2, the HIN of positive pole and process chip U The polar capacitor C4 that pin is connected, negative pole is then connected with process chip U SD pins, one end and process chip U LIN pins Be connected, resistance R6, the N pole that the other end is then connected with polar capacitor C3 negative pole is connected with process chip U SD pins, VCC pin phase of diode D1, the N pole that P poles are then connected with process chip U COM pins after resistance R9 with process chip U Connection, the voltage-regulator diode D2 that is then connected with diode D1 P poles of P poles, positive pole is connected with voltage-regulator diode D2 N poles, The polar capacitor C7 that negative pole is then connected with triode VT2 colelctor electrode, one end are connected, separately with process chip U LO pins Resistance R8, the N pole that one end is then connected with triode VT2 base stage is connected with triode VT1 emitter stage, P poles then sequentially The diode D3 being connected after polar capacitor C6 and polar capacitor C5 with process chip U VB pins, one end and process chip U HO pins be connected, the resistance R7 that the other end is then connected with triode VT1 base stage, and N poles and process chip U VB The diode D4 compositions that pin is connected, P poles are then connected with triode VT1 colelctor electrode；The VDD pipes of the process chip U Pin is connected with resistance R1 and resistance R4 tie point, its HIN pin is then connected with polar capacitor C2 negative pole, VSS pins It is connected with diode D1 N poles, VS pins are then connected with diode D3 P poles, HO pins and polar capacitor C6 and polarity Electric capacity C5 tie point is connected；The colelctor electrode of the triode VT1 is connected with transforming circuit (83), its emitter stage is then with three Pole pipe VT2 emitter stage is connected；The colelctor electrode of the triode VT2 is respectively with voltage-regulator diode D2 P poles and becoming piezoelectricity Road (83) is connected.
- A kind of 3. voltage bias type fingerprint recognition system of logic-based enhanced processing according to claim 2, it is characterised in that： Described transforming circuit (83) is by transformer T, unidirectional thyristor D5, unidirectional thyristor D7, N pole and unidirectional thyristor D5 control The diode D6 that pole is connected, P poles are then sequentially connected after resistance R10 and polar capacitor C8 with unidirectional thyristor D5 P poles, The resistance R11, Yi Jizheng that one end is connected with unidirectional thyristor D5 P poles, the other end is then connected with unidirectional brilliant lock D7 P poles Pole is connected with transformer T secondary inductance coils L2 Same Name of Ends, negative pole is then electric with transformer T secondary after voltage-regulator diode D8 The polar capacitor C9 compositions that sense coil L3 non-same polarity is connected；The P poles of the unidirectional thyristor D5 and diode D4 P poles It is connected, its N pole ground connection, unidirectional thyristor D7 N poles ground connection, control pole and polar capacitor C8 and resistance R10 tie point phase Connection；The P poles of the diode D6 are connected with diode D1 P poles；The Same Name of Ends of the transformer T primary side inductance coils L1 It is connected with unidirectional thyristor D5 P poles, its non-same polarity is then connected with diode D6 P poles, transformer T secondary inductance lines Circle L2 non-same polarity is connected with transformer T secondary inductance coils L3 Same Name of Ends.
- A kind of 4. voltage bias type fingerprint recognition system of logic-based enhanced processing according to claim 3, it is characterised in that： Described process chip U is IR2110 integrated circuits.
- A kind of 5. voltage bias type fingerprint recognition system of logic-based enhanced processing according to claim 3, it is characterised in that： The triode VT1 and triode VT2 are negative-positive-negative transistor.
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| CN106056073B (en) * | 2016-05-27 | 2018-01-23 | 广东欧珀移动通信有限公司 | A kind of unlocked by fingerprint method and equipment |
| CN105975835B (en) * | 2016-05-27 | 2017-11-07 | 广东欧珀移动通信有限公司 | A kind of unlocked by fingerprint control method and terminal device |
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