CN104756407B - For the method and apparatus using stack type metal oxide semiconductor (MOS) transistor to carry out matched transmission line characteristic - Google Patents

Abstract

The output driver protected for static discharge (ESD) includes first pair of stack type metal oxide semiconductor field effect transistor (MOS) device being coupling between power supply terminal and the first Differential output terminals.This output driver also includes the second pair of stack MOS device being coupling between the second Differential output terminals and ground terminal.

Description

For use stack type metal oxide semiconductor (MOS) transistor come matched transmission line characteristic method and Equipment

Technical field

The disclosure relates generally to voltage mode driver.More specifically, it relates to be used for using stacking Formula MOS transistor carrys out the method and apparatus of matched transmission line characteristic.

Background technology

When static discharge (ESD) flows into integrated semiconductor chip, the internal circuit in this semiconductor chip It is likely to be broken or breaks down.ESD mainly flows into input/output driver level.Traditionally, input protection Circuit can be used in input driver-level to hold suitable static discharge stream.But, similar input protection circuit can Output driver level can be used in because design constraint disapprove output buffer and Interface Terminal it Chien shih resistance.Additionally, output driver design is designated as meeting some minimum ESD specification.

General introduction

According to an aspect of this disclosure, describe a kind of output driver.Described output driver includes coupling The first pair of stack type metal oxide semiconductor field effect being combined between power supply terminal and the first Differential output terminals Answer transistor (MOS) device.Described output driver farther includes to be coupling in the second Differential output terminals And second pair of stack MOS device between ground terminal.

According to another aspect of the present disclosure, describe a kind of method operating output driver.The method includes It is inclined that first pair of stack MOS device for being coupling between power supply terminal and the first Differential output terminals generates first Put voltage to mate the first transmission line characteristics.The method also includes for being coupling in the second Differential output terminals and ground connection Second pair of stack MOS device between terminal generates the second bias voltage to mate the second transmission line characteristics.

According to the further one side of the disclosure, describe a kind of output driver.This output driver includes For switching the first device for switching electronic signal of stacking on the second device of electronic signal.First He Second switching device is coupling between power supply terminal and the first Differential output terminals.This output driving is gone back device and is included For switching the 3rd device for switching electronic signal of stacking on the 4th device of electronic signal.3rd He 4th switching device is coupling between the second Differential output terminals and ground terminal.

This feature sketching the contours of the disclosure and technical advantage so that detailed description below is permissible the most broadly It is better understood.Other feature and advantage of the disclosure will be described below.Those skilled in the art should Understanding, the disclosure can be easily used as amendment or be designed to carry out other of the purpose identical with the disclosure The basis of structure.Those skilled in the art it will also be appreciated that such equivalent constructions is without departing from appended right The teaching of the disclosure illustrated in requirement.Be considered as the novel feature of characteristic of the disclosure at its tissue and Operational approach two aspect will be by when being considered in conjunction with the accompanying following description together with further purpose and advantage It is more fully understood that.But, mediate a settlement description mesh it is to be expressly understood that provide each width accompanying drawing to be all only used for solution , and it is not intended as the definition of restriction of this disclosure.

Accompanying drawing is sketched

Specific descriptions because illustrating below in conjunction with accompanying drawing are become more by the feature of the disclosure, nature and advantages Substantially.

Fig. 1 has explained orally the exemplary copy circuit system of the voltage mode driver of the one side according to the disclosure System.

Fig. 2 is the exemplary voltage including stack nmos pass transistor explaining orally the one side according to the disclosure The schematic diagram of mode drivers.

Fig. 3 has explained orally the electricity including stack nmos pass transistor for operation of the one side according to the disclosure The method of die pressing type driver.

Fig. 4 is shown in which can be advantageously with the example wireless communications of the one side of the disclosure.

Fig. 5 is the frame of the design station explaining orally circuit, layout and logical design for semiconductor subassembly Figure.

Describe in detail

The following detailed description of the drawings is intended to the description as various configurations, and be not intended to represent can be real Trample only configuration of concept described herein.This detailed description includes detail to provide respectively The thorough understanding of the conception of species.But, those skilled in the art will be apparent that do not have these to have Body details also can put into practice these concepts.In some instances, illustrate in form of a block diagram well-known structure and Assembly is to avoid falling into oblivion this genus.As described herein, the use of term "and/or" be intended to represent " can Facultative or ", and the use of term "or" is intended to represent " exclusiveness or ".

The each side of the disclosure can include a kind of improved output driver and for this output driver Improved ESD guard method.

Specifically, some aspects of the disclosure generate the electric conduction of the impedance operator being substantially equal to transmission line Resistance (Ron), meets the electrostatic discharge specifications of output buffer design simultaneously.An aspect of this disclosure is used Transistor stack (such as, n-type metal oxide semiconductor field-effect transistor (nmos pass transistor)) Generate the 50 ohm of conducting resistance matched with transmission line impedance characteristic.Stack nmos pass transistor includes It is arranged in more than one between the Differential output terminals of voltage mode driver and the power supply of output buffer Transistor.Stack nmos pass transistor also include being arranged in the Differential output terminals of voltage mode driver with More than one transistor between the ground terminal of output buffer.

With reference to Fig. 1 and 2, show the copy of voltage mode driver 200 according to an aspect of this disclosure Circuits System 100.The voltage mode driver 200 current/voltage to being provided by copy Circuits System 100 / impedance (or its scaled version) replicates.Based on the electric current provided by copy Circuits System 100/ Voltage/impedance (or its scaled version), voltage mode driver 200 is configured to control to drive with output The output impedance that the output driver circuit 260 of device level 240 is associated.

In this configuration, copy Circuits System 100 includes first, second and third circuit portion. First circuit part includes the first current source I1 and resistor R1, R2, R3 and R4.Second circuit portion Divide and include the second current source I2, operational amplifier 102, transistor T1 and resistor R5.Tertiary circuit portion Divide and include that the 3rd current source I3, operational amplifier the 104, second driver transistor T2, the 3rd driver are brilliant Body pipe T3 and resistor R6.In third circuit portion, transistor T2 and T3 is arranged to stacking Formula structure.Transistor T1, T2 and/or T3 can be nmos pass transistors.

In FIG shown in configuration in, each current source in current source be coupled to voltage source VDD and by Programmable current controls source Ictrl and controls.Specifically, each defeated in current source I1, I2 and I3 Enter to be coupled to power vd D.In one configures, current source I1, I2 and I3 generate substantially the same Output electric current.Each circuit part in first, second, and third circuit part is coupled to ground terminal 106.Operational amplifier 102 and 104 can be copy Circuits System 100 output voltage (such as, Vr or Vb). In this configuration, the expectation resistance of copy Circuits System 100 is reached based on voltage.

In FIG, the voltage at the drain D 1 of transistor T1 is by the output electricity from the second current source I2 Press with transistor T1 at impedance and the amassing of combination of resistance of resistor R5 define.As mentioned above, Second current source I2 coupled to the programmable current for controlling current source I1, I2 and I3 and controls source Ictrl. The grid G 1 of transistor T1 coupled to the output of operational amplifier 102 at terminal 110.At terminal 110 Voltage can be equal to the output voltage Vr of operational amplifier 102.The source S 1 of transistor T1 coupled to electricity The terminal 112 of resistance device R5.The terminal 114 of resistor R5 coupled to ground terminal 106.Operational amplifier Second input terminal 120 of 102 can coupled to the terminal 128 of the first circuit part.Electricity at terminal 128 Pressure is Vs.First input end 108 of operational amplifier 102 coupled to the output of the second current source I2.

As shown in Fig. 1 further, the drain D 2 of transistor T2 coupled to the terminal 116 of resistor R6. Voltage at the terminal 124 of resistor R6 is by from the electric current of the 3rd current source I3, transistor T2 and T3 The impedance at place defines with the amassing of combination of the resistance of transistor R6.The grid G 2 of transistor T2 is at terminal The output of operational amplifier 102 it is coupled at 110.Voltage at terminal 110 is equal to operational amplifier 102 Output voltage Vr.The source S 2 of transistor T2 coupled to the drain electrode (D3) of transistor T3.Transistor The grid G 3 of T3 coupled to the output of operational amplifier 104 at terminal 118.This operational amplifier defeated The voltage in source is Vb.The source S 3 of transistor T3 coupled to ground terminal 106.Operational amplifier 104 The second input terminal 126 coupled to the first circuit by the second input terminal 120 of operational amplifier 102 The terminal 128 of part.Voltage Vs at second input terminal 126 is equal to terminal 128 and the second input terminal Voltage defined at 120.First input end 122 of operational amplifier 104 coupled to the 3rd current source The output of I3.

In the configuration of Fig. 1, supply voltage Vs is the second input of operational amplifier 102 and 104 respectively Terminal 120 and the supply voltage of the second input terminal 126.Specifically, the first current source I1 generated Electric current and resistor R1, R2, R3 and R4 define the supply voltage Vs at terminal 128.With electricity The voltage at terminal 130 that resistance device R2, R3 and R4 are associated is equal to Vs.A side in the disclosure Face, resistor R2, R3 and R4 are arranged to parallel configuration.Resistor R1 can be with resistors in parallel R2, R3 and R4 connect.First current source I1 coupled to terminal 128.Terminal 132 be resistor R1, The shared terminal of R2, R3 and R4.The terminal 134 of resistor R1 coupled to ground terminal 106.

In one configures, resistor R1, R2, R3 and R4 are calibrated to predetermined value (such as, R1 Equal to 1.5 thousand (1.5K) ohm) and the resistance of combination of resistors in parallel R2, R3 and R4 be calibrated To 500 ohm.Resistor R1, R2, R3 and R4 are carried out calibration maintain across resistor R1, R2, R3 and R4 with temperature, power and the consistent resistance of change in voltage.

In an aspect of this disclosure, resistor R5 corresponds to calibrated resistance R1, and across transistor The impedance of T1 is corresponding to the resistance across resistors in parallel R2, R3 and R4.Specifically, resistor R5 Equal to 1.5K ohm or the resistance that is substantially equal to R1, and the impedance of transistor T1 is 500 ohm or base Equal to the resistance across resistors in parallel R2, R3 and R4 in basis.Therefore, from terminal 128 to earth terminal The all-in resistance of son 106 is equal or substantially equal to the total electricity from first input end 108 to ground terminal 106 Resistance.Because the electric current by first input end 108 and terminal 128 is the most equal (that is, from the electric current of I1 Equal to from the electric current of I2), so the voltage at first input end 108 and terminal 128 is the most equal.Cause For the electricity when transistor T1 turns on, at the voltage defined at terminal 128 and the second input terminal 120 Press identical, so when transistor T1 enlivens, first input end 108 of operational amplifier 102 and the Input voltage at two input terminals 120 is the most identical.If it occur that any difference, then the work of this circuit so that Input voltage is identical.

Similarly, resistor R6 corresponds to calibrated resistance R1, and across the impedance of transistor T2 and T3 Summation corresponding to across the resistance of resistors in parallel R2, R3 and R4.Specifically, resistor R6 etc. In 1.5K ohm or the resistance that is substantially equal to R1, and the summation of the impedance of transistor T2 and T3 is 500 Ohm or be substantially equal to the resistance across resistors in parallel R2, R3 and R4.Therefore, from terminal 128 All-in resistance to ground terminal 106 is equal or substantially equal to from first input end 122 to ground terminal The all-in resistance of 106.Because by the electric current of terminal 128 and first input end 122 be equal (i.e., Electric current from current source I1 is equal to the electric current from current source I3), so terminal 128 and the first input Voltage at terminal 122 is the most equal.Because at terminal 128 definition voltage with at first input end 122 The voltage of place's definition is identical, so first input end 122 of operational amplifier 104 and first input end Input voltage at 122 is identical.

The bias voltage Vr that transistor T1, T2 and T3 can be generated by operational amplifier 102 and 104 It is biased to they corresponding impedances with Vb.Specifically, output voltage Vr is from operational amplifier 102 Output loopback to be biased to they corresponding impedances by transistor T1 and T2, and from operational amplifier 104 Output transistor T3 is biased.It addition, bias voltage Vr and Vb can change, so that brilliant The impedance of body pipe T1, T2 and T3 is corresponding to the corresponding calibrated resistance of the first circuit configuration.

Fig. 2 is to explain orally to drive according to the voltage mode including stack nmos pass transistor of the one side of the disclosure The schematic diagram of dynamic device 200.As mentioned above, Fig. 2 voltage mode driver 200 to Fig. 1 by copy The current/voltage/impedance (or its scaled version) that Circuits System 100 is provided replicates.Relative to Respective transistor T4 of voltage mode driver 200 of Fig. 2, the impedance spy of T5, T6, T7 and T9 Property, transistor T1, T2 and T3 of copy Circuits System 100 have the ratio of 1:10.Such as, though So the copy Circuits System 100 of Fig. 1 generates across transistor T1 and 500 of the combination across transistor T2 and T3 Ohmage, but at the output driver level 240 of Fig. 2, across corresponding transistor T4 or T6 or crystalline substance The total impedance of the corresponding combination producing of body pipe T5 and T9 or T7 and T9 is 50 ohm.That is, output drives 50 ohmages at device level 240 are owing to the transistor AND gate voltage mode of copy Circuits System 100 drives 1:10 impedance ratio between the transistor of device 200 and cause.

In this configuration, the total impedance at output driver level 240 is 50 ohm, because voltage mode The output driver level 240 of driver 200 is by the respective transistor relative to copy Circuits System 100 The impedance operator of T1, T2 and T3 have the ratio of 10:1 transistor T4, T5, T6, T7 and T9 realizes.As a result, the Single-end output resistance of the voltage mode driver 200 of Fig. 2 is 50 ohm of (examples As, 500/10 ohm is caused because of the ratio of 10:1).In this configuration, total impedance (such as, 50 Ohm) with the matches impedances of the transmission line being associated with voltage mode driver 200.

As shown in Figure 2, voltage mode driver 200 is via Differential output terminals outp 270 and outn 272 It is selectively coupled to transmission line.Transmission line can have 50 ohm characteristic impedance.In this configuration, electricity Die pressing type driver 200 includes pre-driver level 210 and output driver level 240.Pre-driver level 210 Including the first power rail circuit 220 and pre-driver circuit 230.Output driver level 240 includes the second merit Rate rail circuit 250 and output driver circuit 260.

In an aspect of this disclosure, the copy Circuits System 100 of Fig. 1 controls pre-driver level 210, and And pre-driver level controls the output impedance of output driver level 240.In this configuration, copy circuit system System 100 generates voltage Vr for pre-driver level 210.The output voltage of pre-driver level 210 swings by powering Voltage Vr sets.Specifically, pre-driver level 210 is (such as electric with real voltage at such as 0 volt Pressure Vr) between overturn.The upper rail of pre-driver level output is that Vr1 is (that is, at the second input terminal 214 With the voltage of definition at the drain D 10 of transistor T10), Vr1 is equal to Vr.Specifically, output voltage Vr1 is looped back to the second input terminal 214 of operational amplifier 222 from the drain D 10 of transistor T10.Come Can adjust to control output voltage with current source I4 from the tail current of prime amplifier level 210 to swing.

In this configuration, the first power rail circuit 220 includes operational amplifier 222, power vd D and crystalline substance Body pipe T10.The source S 10 of transistor T10 is coupled to power vd D, and grid G 10 coupled to computing and puts The output of device 222, and drain D 10 greatly coupled to terminal 234.The first terminal 226 of capacitor Cr couples The second terminal 228 to terminal 234 and capacitor Cr coupled to DC earthing terminal 216.Operational amplifier First first input end 212 of 222 receives the voltage Vr generated by copy Circuits System 100.At this In one configuration, the output of pre-driver circuit 230 swings the power supply electricity generated by copy Circuits System 100 Pressure Vr sets.Second input terminal 214 of operational amplifier 222 coupled to drain D 10 to receive The voltage of definition at drain D 10.

Pre-driver circuit 230 can be based on current mode logic configuration.Typically, pre-driver circuit 230 can include transistor T11 and T12, resistor R7 and R8, ground terminal 218 and current source I4.The source S 11 of transistor T11 coupled to the terminal 238 of current source I4；Grid G 11 coupled to difference Input terminal inp 202；And the terminal 232 that drain D 11 coupled between resistor R7 and drain D 11. The terminal 239 of current source I4 coupled to ground terminal 218.The source S 12 of transistor T12 coupled to electric current The terminal 238 of source I4；Grid G 12 coupled to differential input terminals inn 204；And drain D 12 coupled to Terminal 236.Each resistor in resistor R7 and R8 can coupled to terminal 234.Resistor R7 and The resistance of R8 is about 200 ohm.Differential input terminals (inp 202 and inn 204) receives Differential Input Signal.In an aspect of this disclosure, transistor T10 is p-type metal oxide semiconductor field effect transistor Pipe (PMOS transistor) and transistor T11 and T12 is nmos pass transistor.In operation, as The result worked in saturation, transistor T10, T11 and T12 can have the impedance of increase.

As shown in Figure 2, voltage mode driver 200 also includes that the second power rail circuit 250 and output are driven Dynamic device circuit 260.In an aspect of this disclosure, the second power rail circuit 250 include operational amplifier 252, Power vd D and transistor T8.The source S 8 of transistor T8 coupled to power vd D；Grid G 8 coupling It is bonded to the output of operational amplifier 252；Drain D 8 coupled to first end of capacitor Cs by terminal 262 Son 264；And second terminal 269 of Cs coupled to ground terminal 246 to provide DC earthing.At this In configuration, first input end 242 of operational amplifier 252 receives and is generated by copy Circuits System 100 Voltage Vs.Second input terminal 244 of operational amplifier 252 can coupled to drain D 8 to receive in leakage The voltage generated at the D8 of pole.Specifically, the output of output driver level 240 swings by supply voltage Vs Set.Second power rail circuit 250 of output driver level 240 provides output driver circuit 260 Upper rail output voltage Vs1 at terminal 262.Specifically, at the second input terminal 244 with in drain D 8 The voltage of place's definition is equal to Vs.In this configuration, output voltage Vs1 is from the drain D 8 of transistor T8 It is looped back to the second input terminal 244 of operational amplifier 252.

Output driver circuit 260 can include transistor T4, T5, T6, T7 and T9.Transistor T4, T5, T6 and T7 are arranged to cross-over configuration, as explained in Figure 2, are used for facilitating electric current to pass through defeated Go out drive circuit 260.The source S 4 of transistor T4 coupled to the drain D 5 of transistor T5, and crystal The grid G 4 of pipe T4 coupled to the drain D 11 of transistor T11 by terminal 232.The source of transistor T5 Pole S5 coupled to the drain D 9 of transistor T9, and the grid G 5 of transistor T5 is coupled by terminal 236 Drain D 12 to transistor T12.The source S 9 of transistor T9 coupled to ground terminal 248, and crystal The grid G 9 of pipe T9 receives the voltage Vb from copy Circuits System 100.The source S 6 of transistor T6 It coupled to the drain D 7 of transistor T7, and the grid G 6 of transistor T6 coupled to drain D 12 and coupling It is bonded to grid G 5.The source S 7 of transistor T7 coupled to drain D 9, and the grid G 7 of transistor T7 It coupled to drain D 11 and coupled to grid G 4.In an aspect of this disclosure, transistor T8 is PMOS Transistor and transistor T4, T5, T6, T7 and T9 are nmos pass transistors.

In this configuration, transistor T5 with T9 of output driver level 240 or T7 with T9 is corresponding Transistor T2 and T3 in copy Circuits System 100.Transistor T4 or T6 of output driver level 240 Also correspond to the transistor T1 of copy Circuits System 100.Voltage mode driver 200 is by copy Circuits System 100 drive, so that the transistor of copy Circuits System 100 and the correspondence of voltage mode driver 200 The impedance of transistor is the most equal or is substantially identical.Specifically, copy circuit system The transistor T1 of system 100 is the duplication of transistor T4 or T6 in voltage mode driver 200.Similar Ground, transistor T2 and T3 of copy Circuits System 100 is the transistor in voltage mode driver 200 The duplication of T5 and T9 or T7 and T9.Because coupling output impedance is desired, therefore output driver level The impedance that 240 outputs are equal with the characteristic impedance of transmission line.

Differential signal is driven into pre-driver circuit 230 via differential input terminals inp 202 and inn 204 In, and transistor T11 and T12 according at pre-driver level 210 switching realize biased.Such as, In a particular logic state, the logic low of differential input terminals is designed to of a sufficiently low to end crystal Pipe T11 and T12.Turn on so that output driver level 240 at the transistor T11 of pre-driver level 210 Transistor T4 when being also switched on, transistor T4 is identical with the transistor T1 with copy Circuits System 100 Mode is biased (seeing Fig. 1).In the normal operation period, the impedance of transistor T4 and copy Circuits System The impedance of the transistor T1 of 100 is identical.Turn on so that exporting at the transistor T12 of pre-driver level 210 When transistor T5 and T6 of driver-level 240 is also switched on, transistor T6 with copy Circuits System 100 Mode identical for transistor T1 biased.In the normal operation period, the impedance of transistor T6 also with copy The impedance of the transistor T1 of Circuits System 100 is identical.

In some applications (such as, memorizer physical layer (M-PHY)), output driver level 240 Second power rail circuit 250 can be designated as 200 millivolts (mv) or 400mv.In 200mv applies, Such as, current source I1, I2 and the I3 in copy Circuits System 100 electric current generated is set as 100 Microampere.In this configuration, terminal 128, second input terminal 120 of copy Circuits System 100 and Voltage Vs at second input terminal 126 is 200mv (that is, the 100 microamperes impedances being multiplied by terminal 128 (2 kilo-ohms)).In this configuration, first input end 242 of operational amplifier 252 receives by pair The voltage Vs (that is, 200mv) that this Circuits System 100 is generated.Because Vs is equal to Vs1, so fortune Calculating the voltage at the second input terminal 244 of amplifier 252 is also 200mv.

As shown in Figure 2, output is combined by the electric current of output driver circuit 260 by this voltage Vs The impedance of the transistor of drive circuit defines.Such as, transistor T4 impedance (that is, 50 ohm), The impedance of the impedance (that is, 50 ohm) of transistor T5 and T9 and transmission line (that is, 100 ohm, Wherein 50 ohm be output impedance and 50 ohm be input impedance) combine voltage Vs determine by output The electric current of drive circuit 260.Output driver electric current also can by the impedance of voltage Vs binding crystal pipe T6, The impedance of transistor T7 and T9 and the impedance of transmission line determine.Transistor T4 or T6 can be implemented as Potentiometer.

In operation, the input terminal 202 and 204 of the pre-driver circuit 230 of pre-driver level is in conducting Overturn between state and cut-off state.As a result, transistor T11 and T12 of pre-driver circuit conducting with Overturn between cut-off state.When transistor T11 is in the conduction state, in the grid G 4 of transistor T4 With at the grid G 7 of transistor T7 generate voltage so that transistor T4 and T7 be switched on.As a result, Electric current flows through transistor T4 from the second power rail circuit 250 and arrives Differential output terminals outn 272 and arrive Transmission line.Electric current passes the second lead-out terminal 266 via difference output end subpad outp 270, through crystal Pipe T7 and T9 the ground terminal 248 that arrives soon after reflux from transmission line.It is at transistor T12 During state, at the grid G 5 of transistor T5 and the grid G 6 of transistor T6, generate voltage, so that Transistor T5 and T6 is switched on.As a result, electric current from the second power rail circuit 250 flow through transistor T6 to Reach outfan subpad outp 270, flow through the first lead-out terminal 266 and arrive transmission line.Electric current is via output Terminal pad outn 272 is through the second lead-out terminal 268, through transistor T5 and T9 ground connection of arriving soon after Terminal 248 refluxes from transmission line.

In an aspect of this disclosure, it is arranged on lead-out terminal and the power supply (example of voltage mode driver 200 Such as, VDD) and/or ground terminal 248 between multiple stack transistor driving output driver circuits The lead-out terminal of 260.Stack transistor can include stack nmos pass transistor.Stack NMOS The impedance of transistor is biased to 50 ohm (in the example present) impedance operator with matched transmission line. Such as, see into output driver level 240 to ground terminal 248 from the first lead-out terminal 266, exist Two stack nmos pass transistors, i.e. transistor T7 and T9.Similarly, two stack NMOS Transistor T5 and T9 is illustrated between the second lead-out terminal 268 and ground terminal 248.Stack crystal The summation of the impedance of pipe T5 and T9 or T7 and T9 is 50 ohm (in the example present), it and transmission The impedance operator of line matches.

Similarly, see into output driver level 240 to power vd D from the first lead-out terminal 266, There are two stack transistors, i.e. nmos pass transistor T6 and PMOS transistor T8.It addition, heap Stacked nmos pass transistor T4 and PMOS transistor T8 are arranged on power vd D and the second lead-out terminal Between 268.Capacitor Cs includes the first terminal 264 coupleding to terminal 262 and coupled to ground terminal Second terminal 269 of 246.As a result, transistor T4 or T6 is such as biased to 50 ohm, with transmission The impedance operator of line matches.Therefore, the impedance of transistor T4 or T6 corresponds to copy Circuits System 100 The impedance of transistor T1.Similarly, transistor T4 is biased to 50 ohm, with the resistance with transmission line Anti-characteristic matches.

There is between ground terminal 248 and lead-out terminal stack transistor T5 and T9 or T7 and T9 Static discharge is met by there is more than one transistor between lead-out terminal and ground terminal 248 (ESD) specification.Such as, if the summation of the impedance of stack transistor T2 and T3 is 50 ohm, Then the impedance of stack transistor T5 and T9 is also 50 ohm.Based on the switching at pre-driver level 210 Realizing, this feature of stack transistor T5 and T9 is also applied for stack transistor T7 and T9.

Similarly, there is between power vd D and lead-out terminal stack transistor T6 and T8 or T4 With T8 meets static discharge by having more than one transistor between lead-out terminal and power vd D (ESD) specification.Such as, if the impedance of transistor T1 is 50 ohm, then the impedance of transistor T4 Also it it is 50 ohm.Realizing based on the switching at pre-driver 210, this feature of transistor T4 is the most applicable In transistor T6.

Fig. 3 has explained orally the electricity for realizing including stack nmos pass transistor of the one side according to the disclosure The method 300 of die pressing type driver.At frame 302, the method starts from as being coupling in power supply terminal and the first difference It is special to mate the first transmission line that first pair of stack MOS device between lead-out terminal generates the first bias voltage Property.Solution at Fig. 2 is right, the first pair of stack MOS device include transistor T6 and T8 or T4 and T8.At frame 304, the method includes for being coupling in second between the second Differential output terminals and ground terminal Stack MOS device is generated the second bias voltage to mate the second transmission line characteristics.Explanation at Fig. 2 In, second pair of stack MOS device includes transistor T5 and T9 or T7 and T9.

In one configures, output driver includes the device for generating the first bias voltage and for generating The device of the second bias voltage.In an aspect of this disclosure, the first and/or second bias voltage device is permissible It is arranged to perform by the first power rail circuit of the function described in the first and/or second bias voltage device 220, the second power rail circuit 250 and/or pre-driver circuit 230.

One configure in, output driver include for switch electronic signal first, second, third with And the 4th device.In an aspect of this disclosure, first, second, third and the 4th switching device permissible It is transistor, the transistor T4 of the output driver level 240 of the voltage mode driver 200 of such as Fig. 2, T5, T6, T7, T8 and/or T9.

Fig. 4 is shown in which can be advantageously with the voltage mode driver including stack nmos pass transistor The example wireless communications 400 of embodiment.For explaining orally purpose, Fig. 4 shows three long-range lists Unit 420,430 and 450 and two base stations 440.It will be recognized that wireless communication system can have much more Remote unit and base station.Remote unit 420,430 and 450 includes comprising stack NMOS crystal The voltage mode driver of pipe 425A, 425B and 425C.Fig. 4 shows from base station 440 to remotely The forward link signal 480 of unit 420,430 and 450, and from remote unit 420,430 and 450 reverse link signal 490 arriving base station 440.

In the diagram, remote unit 420 is illustrated as mobile phone, and remote unit 430 is illustrated as portable meter Calculation machine, and the remote unit that the position that remote unit 450 is illustrated as in wireless local loop system is fixing.Example As, remote unit can be cell phone, handheld personal communication systems (PCS) unit, portable number According to the data cell (such as meter reading equipment) that unit (such as personal digital assistant) and/or position are fixing. Although Fig. 4 has explained orally the voltage-mode that can use the stack nmos pass transistor including the teaching according to the disclosure Remote unit 425A, 425B and 425C of formula driver, but the disclosure be not limited to be explained orally these show Example unit.Such as, stack N-type MOS field is included according to embodiment of the disclosure The voltage mode driver of effect transistor can be used in any equipment suitably.

Fig. 5 is to explain orally (the most disclosed above to include stack nmos pass transistor for semiconductor subassembly Voltage mode driver) the block diagram of design station of circuit, layout and logical design.Design work Standing and 500 include hard disk 501, this hard disk 501 comprises operating system software, supports file and design soft Part (such as Cadence or OrCAD).Design station 500 also includes facilitating circuit 510 or partly leading The display of the design of body assembly 512 (such as including the voltage mode driver of stack nmos pass transistor) Device 502.There is provided storage medium 504 for visibly storage circuit design 510 or semiconductor subassembly 512. Circuit design 510 or semiconductor subassembly 512 can (such as GDSII or GERBER) storages as a file format On storage medium 504.Storage medium 504 can be CD-ROM, DVD, hard disk, flash memory or Other appropriate equipment.Additionally, design station 500 include for from storage medium 504 accept input or Person is by the driving means 503 of output write storage medium 504.

On storage medium 504, the data of record may specify logic circuit configuration, pattern numbers for mask According to or write the mask pattern data of instrument (such as beamwriter lithography) for string.These data can be further Including the logic checking data being associated with logical simulation, such as sequential chart or net circuit.At storage medium 504 Upper offer data facilitate circuit design 510 or half by reducing for the technique number designing semiconductor wafer The design of conductor assembly 512.

Although having elaborated particular electrical circuit system, but those skilled in the art will be appreciated that and not all institute Disclosed Circuits System is all to put into practice necessary to the disclosed embodiments.Additionally, some well-known electricity Road is not described, in order to keep being absorbed in the disclosure.

Method system described herein depends on that application can realize by various means.Such as, these Method system can realize in hardware, firmware, software or its any combination.Hardware is realized, this A little processing units can one or more special ICs (ASIC), digital signal processor (DSP), Digital signal processor (DSPD), PLD (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, electronic device, be designed to carry out Realize in other electronic units of functions described herein or a combination thereof.

Realizing for firmware and/or software, these method systems can be by the module performing function described herein (such as, code, function etc.) realizes.Visibly embody any machine or the computer-readable of instruction Medium can be used for realizing method system described herein.Such as, software code can be stored in memorizer In and performed by processor.When being executed by a processor, executory software code generate realize herein institute in The various method systems of the different aspect of existing teaching and functional operating environment.Memorizer can be implemented in Outside processor inside or processor.As it is used herein, term " memorizer " refers to any kind of For a long time, short-term, volatibility, non-volatile or other memorizeies, and be not limited to any particular type Memorizer or any certain number of memorizer or memory storage media type thereon.

Storage is defined machine or computer-readable Jie of the software code of methods described herein system and function Matter includes Physical computer readable storage media.Storage medium can be any available Jie that can be accessed by a computer Matter.Unrestricted as example, these computer-readable mediums can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage apparatus or storage can be used to refer to Order or the expectation program code of data structure form and any other medium that can be accessed by a computer.As herein Being used, dish (disk) and/or dish (disc) include compact disc (CD), laser dish, laser disc, number The multiplex dish of word (DVD), floppy disk and blu-ray disc, its mid-game the most magnetically reproduces data and dish laser comes Reproduce data optically.Combinations of the above also should be included within the scope of computer readable media.

Except storage on a computer-readable medium, instruction and/or data are alternatively arranged as including within a communication device Transmission medium on signal provide.Such as, communicator can include the letter with indicator and data Number transceiver.These instruction and datas are configured to make one or more processor realize in claim and chat The function stated.

Although having described this teaching and advantage thereof in detail, but it is to be understood that can make various in this article Change, substitute and be changed without to depart from such as the technology by this teaching defined in claims.And, Scope of the present application is not intended to be limited to process described in this description, machine, manufacture, material group One-tenth, device, the particular aspects of method and steps.Because those of ordinary skill in the art will be easily from these public affairs Open and understand, according to this teaching, it is possible to use existing or Future Development to corresponding aspect described herein Perform essentially identical function or reach the process of essentially identical result, machine, manufacture, material composition, Device, method or step.Therefore, claims are intended to such process, machine, manufacture, thing In the range of matter composition, device, method or step are included in it.

Claims (21)

1. an output driver, including: copy Circuits System, it is configured to: generate for first The first bias voltage being biased with triplicate device, wherein said first bias voltage sets described the The defined impedance of one copy device；Generate the second biased electrical for triplicate device is biased Pressure, wherein said first and second bias voltages setting described second and the defined warps of triplicate device Combined impedance, described defined combined impedance is first impedance and described the of described triplicate device The summation of the second impedance of three copy devices；It is respectively coupled in power supply terminal and the first and second difference output ends First pair of mos field effect transistor (MOS) device between son, wherein in response to described A MOS device in first pair of MOS device receives voltage based on described first bias voltage, institute State the 3rd impedance of one MOS device in first pair of MOS device based on described first authentic copy device Described defined impedance；And it is defeated to be respectively coupled in described first and second difference by MOS device Go out second pair of MOS device between terminal and ground terminal, wherein in response to described second pair of MOS device In a MOS device receive voltage based on described first bias voltage and by described second couple of MOS Device is coupled to the MOS device of described ground terminal and is biased with described second bias voltage, as institute State the of the 4th impedance of one MOS device in second pair of MOS device and described MOS device The combined impedance of the summation of five impedances is based on described defined combined impedance.

2. output driver as claimed in claim 1, it is characterised in that described first pair of MOS device or institute At least one stated in second pair of MOS device includes nmos device.

3. output driver as claimed in claim 1, it is characterised in that farther include to operate for based on Input differential signal carrys out one MOS device in described first pair of MOS device and described second right One MOS device in MOS device provides the current-mode of voltage based on described first bias voltage Formula pre-driver.

4. output driver as claimed in claim 1, it is characterised in that described copy Circuits System is configured to Supply voltage is provided to swing to set the output voltage across described first and second Differential output terminals.

5. output driver as claimed in claim 4, it is characterised in that farther include: be configured to from institute State copy Circuits System and receive the Voltage rails circuit of described supply voltage.

6. output driver as claimed in claim 1, it is characterised in that described output driver is integrated into shifting Mobile phone, Set Top Box, music player, video player, amusement unit, navigator, computer, The data sheet that handheld personal communication systems (PCS) unit, portable data units and/or position are fixing In unit.

7. output driver as claimed in claim 1, it is characterised in that described defined impedance and described institute The combined impedance characteristic based on the transmission line coupleding to described first and second Differential output terminals of definition Impedance.

8. output driver as claimed in claim 1, it is characterised in that described 3rd impedance is based on defined Impedance ratio is multiplied by described defined impedance, and wherein said combined impedance is based on described defined Impedance ratio is multiplied by described defined combined impedance.

9. the method operating output driver, including: generate for the first and second copy devices are carried out partially The first bias voltage put, wherein said first bias voltage sets the defined of described first authentic copy device Impedance；Generate for the second bias voltage that triplicate device is biased, wherein said first and the Two bias voltages set described second and the defined combined impedances of triplicate device, described are defined Combined impedance be second resistance of the first impedance and described triplicate device of described triplicate device Anti-summation；It is applied to be coupled respectively to power supply terminal and first by voltage based on described first bias voltage And first pair of mos field effect transistor (MOS) device that second between Differential output terminals In a MOS device, the 3rd of the one MOS device in wherein said first pair of MOS device Impedance described defined impedance based on described first authentic copy device；By based on described first bias voltage Voltage be applied to by MOS device be coupling in described first and second Differential output terminals and ground terminal it Between second pair of MOS device in a MOS device；And described second bias voltage is applied to institute State second pair of MOS device and be coupled to the MOS device of described ground terminal, wherein as described second right 4th impedance of the one MOS device of MOS device is total with the 5th impedance of described MOS device The combined impedance of sum is based on described defined combined impedance.

10. method as claimed in claim 9, it is characterised in that by voltage based on described first bias voltage It is applied to the one MOS device in described first pair of MOS device and described second pair of MOS device In one MOS device based on input differential signal.

11. methods as claimed in claim 9, it is characterised in that farther include: provide supply voltage to be used for Set the output voltage across described first and second Differential output terminals to swing.

12. methods as claimed in claim 11, it is characterised in that farther include: use described supply voltage Generate described first and second bias voltages.

13. methods as claimed in claim 9, it is characterised in that farther include: by described output driver Be integrated into mobile phone, Set Top Box, music player, video player, amusement unit, navigator, Computer, handheld personal communication systems (PCS) unit, portable data units and/or position are fixed Data cell in.

14. methods as claimed in claim 9, it is characterised in that described defined impedance and described defined Combined impedance characteristic impedance based on the transmission line coupleding to described first and second Differential output terminals.

15. methods as claimed in claim 9, it is characterised in that described 3rd impedance is based on defined impedance Ratio is multiplied by described defined impedance, and wherein said combined impedance is based on described defined impedance Ratio is multiplied by described defined combined impedance.

16. 1 kinds of output drivers, including: for generating for the first and second copy devices are biased The device of the first bias voltage, wherein said first bias voltage sets being defined of described first authentic copy device Impedance；For generating the device for the second bias voltage that triplicate device is biased, wherein Described first and second bias voltages setting described second and the defined combined resistances of triplicate device Anti-, described defined combined impedance is the first impedance of described triplicate device and described triplicate The summation of the second impedance of device；It is respectively coupled between power supply terminal and the first and second Differential output terminals The first and second switching devices, wherein in response in described first and second switching devices one switching dress Put and receive voltage based on described first bias voltage, described in described first and second switching devices The 3rd impedance described defined impedance based on described first authentic copy device of individual switching device；And pass through MOS device is coupling in third and fourth between described first and second Differential output terminals and ground terminal Switching device, wherein in response to a switching device in described third and fourth switching device receive based on The voltage of described first bias voltage and described second pair of MOS device is coupled to described ground terminal MOS device is biased with described second bias voltage, as the institute in described third and fourth switching device State the combined impedance of the 4th impedance of a switching device and the summation of the 5th impedance of described MOS device Based on described defined combined impedance.

17. output drivers as claimed in claim 16, it is characterised in that farther include for based on input Differential signal one switching device in described first and second switching devices and described 3rd He One switching device in 4th switching device supplies the dress of voltage based on described first bias voltage Put.

18. output drivers as claimed in claim 16, it is characterised in that farther include for providing power supply Voltage is to set the device of the output voltage swing across described first and second Differential output terminals.

19. output drivers as claimed in claim 16, it is characterised in that described output driver is integrated into Mobile phone, Set Top Box, music player, video player, amusement unit, navigator, computer, The data sheet that handheld personal communication systems (PCS) unit, portable data units and/or position are fixing In unit.

20. output drivers as claimed in claim 16, it is characterised in that described defined impedance and described Defined combined impedance spy based on the transmission line being coupled to described first and second Differential output terminals Property impedance.

21. output drivers as claimed in claim 16, it is characterised in that described 3rd impedance is based on being defined Impedance ratio be multiplied by described defined impedance, and wherein said combined impedance is defined based on described Impedance ratio be multiplied by described defined combined impedance.