CN104752518B - Isolated form high withstand voltage FET - Google Patents
Isolated form high withstand voltage FET Download PDFInfo
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- CN104752518B CN104752518B CN201310753318.2A CN201310753318A CN104752518B CN 104752518 B CN104752518 B CN 104752518B CN 201310753318 A CN201310753318 A CN 201310753318A CN 104752518 B CN104752518 B CN 104752518B
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- pipe
- type
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- region
- withstand voltage
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- 238000005070 sampling Methods 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 230000003139 buffering effect Effects 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Abstract
The invention discloses a kind of isolated form high withstand voltage FET with current sample function, including：One sampling pipe of structure identical and at least one it is sampled pipe, sampling pipe is formed being sampled to separate at the source region on the more finger-like array structure peripheries of pipe, sampling pipe shares drain region and polysilicon field grid with pipe is sampled, sampling pipe source region and it is sampled between pipe source region there is high withstand voltage buffering area in the position close to polysilicon gate, high withstand voltage buffering area is made up of silicon substrate P type substrate, high withstand voltage buffering area by sampling pipe and is sampled the source region of pipe, substrate p-type trap, p-type doped region and isolated across polysilicon gate；Polysilicon gate is across sampling pipe and is sampled the N-type drift region of the source region of pipe, substrate p-type trap and source region.The present invention can reduce integrated area under the premise of keeping sampling pipe and being sampled the high withstand voltage of pipe, and increase is sampled the effective area of pipe, can increase the sampling ratio of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of isolated form high withstand voltage FET.
Background technology
Currently used isolated form high withstand voltage FET sampling tubular construction is divided into discrete type as shown in figure 1, domain is realized
With two kinds of integrated-type.Discrete type sampling pipe be be sampled beside pipe place an independent small tubes be used as sampling pipe, sample
The drain region drift region of pipe, source region manufacture all with channel region with pipe is sampled in size with technique, i.e., section A-A is in sampling pipe
Be sampled that pipe is identical, so ensure that the current characteristics that two pipes are tested under identical voltage conditions is all identical, such energy
Ensure sample rate current and be sampled the linear relationship of electric current and reach sampling purpose.But the shortcomings that this design, is：
1. extra area is needed to place circular sampling pipe, and sampling pipe needs to pass through envelope with the drain terminal for being sampled pipe
Together, sampling pipe encapsulation needs pressure welding point, further increases the area of sampling pipe for load；
2. the minimum effective raceway groove of sampling pipe is exactly round girth, the electric current of such sampling pipe can not do small, adopt accordingly
Sample ratio（Sampling tube current/be sampled tube current, under the conditions of same test）It can not do big；
In order to solve the problems, such as additional areas waste, the sampling pipe design of also a kind of integrated-type, that is, extract and adopted
Egg type high withstand voltage FET is placed as sampling pipe as shown in Fig. 2 so integrated in a pipe position among sample pipe
Sampling pipe and the drain region for being sampled pipe are shared, it is not necessary to extra to increase pressure welding point and cause the increase of area；Sampling pipe is put
Put in the centre for being sampled pipe, the matching properties of two pipes are fine, influenceed very little by process deviation；Sampling pipe current capacity
It can be adjusted by the height of middle egg type sampling pipe, big sampling ratio can be done.But same such design method also has it
Shortcoming：
1. waste a position for being sampled pipe to place sampling pipe, be sampled pipe array heights be designed to it is higher, it is right
The loss for being sampled tube current ability is bigger；
2. the egg type height of sampling pipe can not be made very small, it is made smaller, it is pressure-resistant lower, as shown in Figure 6.
The content of the invention
Keeping sampling pipe the technical problem to be solved in the present invention is to provide a kind of and be sampled under the premise of the high withstand voltage of pipe
Integrated area can be reduced, increase is sampled pipe effective area, can increase the isolated form high withstand voltage FET of sampling ratio.
In order to solve the above technical problems, the isolated form high withstand voltage field-effect provided by the invention with current sample function
Pipe, including：One sampling pipe 301 of structure identical and at least one it is sampled pipe 302（When have it is multiple be sampled pipe when, each quilt
Sampling pipe is connected in parallel）, sampling pipe 301 is being sampled at the source region 202 on the pipe array structure of finger-like more than 302 periphery separation shape
Into, sampling pipe 301 and it is sampled pipe 302 and shares drain region 201 and polysilicon field grid 109, sampling pipe source region 211 and is sampled pipe
There is high withstand voltage buffering area 210 in the position close to polysilicon gate 109 between source region 212, high withstand voltage buffering area 210 is by silicon substrate
Plate P type substrate forms, and high withstand voltage buffering area 210 by sampling pipe and is sampled the He of pipe source region 211 across polysilicon gate 109
212nd, substrate p-type trap 303b and 303a, p-type doped region 304b and 304a are isolated from each other；Sampling pipe polysilicon gate and it is sampled
Pipe polysilicon gate, which is connected, is collectively forming complete closed-loop shaped polysilicon gate 109；Polysilicon gate 109 across sampling pipe and
It is sampled the N-type drift region 302b and 302a of pipe source region 211 and 212, substrate p-type trap 303b and 303a and source region.
Wherein, the sampling pipe or it is sampled pipe and includes the N-type drift region 102 on the top of P type substrate silicon substrate 101, the first N
+ active area 106 and substrate p-type trap 103 are connected together to form source region 202 by the extraction of P+ active areas 108 with metal, N-type drift
Area 102 encases whole source region 202 and isolates substrate p-type trap 103 and P type substrate silicon substrate 101, and field oxygen isolation 105 is formed in N-type
The top of drift region 102, the first p-type doped region 104 are located at the top of N-type drift region 102, the 2nd N+ active areas of N-type drift region 102
107 extractions form drain region 201, the second p-type doping 104a formed below of source region 202, and field oxygen isolates the 105, first p-type doped region
104 and second above p-type doping 104a covered with polysilicon 109, the polysilicon forms source region polycrystalline with the extraction of the first metal 111
Silicon gate, field oxygen, which is isolated on 105, to be connected together and to be formed with the second metal 112 and the 2nd N+ active areas 107 covered with polysilicon 110
Drain region polysilicon field plate, there is the 3rd metal 113, the 3rd metal 113 and source region polysilicon gate in the side of the first metal 111
109 connect together.
Wherein, the first p-type doped region 104 is located at N-type drift region 102 and the top of P type substrate silicon substrate 101, and the first p-type is mixed
The width that miscellaneous area 104 is located at the upper part of P type substrate silicon substrate 101 is that O is 0 micron~10 microns.
Wherein, sampling pipe and the N-type drift for being sampled pipe source region 211 and 212, substrate p-type trap 303b and 303a and source region
Move area 302b and 302a to handle by sphering, be shaped to rounded form.
Wherein, sampling pipe area width W is 1 micron~100 microns.
Wherein, the width S between sampling pipe and the N-type drift region 302b and 302a that are sampled pipe source region is 5 microns~100
Micron.
Wherein, the height D of high withstand voltage buffering area 210 is 5 microns~50 microns, and width L is than sampling pipe and is sampled pipe source region
N-type drift region 302b and 302a between width S it is big 2 microns~20 microns.
The present invention uses two structure same separation type high withstand voltage FETs, by the pipe of current sample from quilt
The periphery source of the pipe of sampling intercepts one section of mode, substantially increases the integrated level of sampling pipe, design high withstand voltage buffering
Area is inserted in sampling pipe and is sampled method between pipe source region N-type drift region, can the substrate p-type trap of current sample pipe and
It is sampled and is isolated entirely from the substrate p-type trap of pipe with N-type injection drift region, realizes in circuit work the complete of two pipes
Isolation, does not leak electricity, and ensure that the sampling pipe under small area has and be sampled the same voltage endurance capability of pipe.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is existing isolated form high withstand voltage FET sampling pipe structural representation one.
Fig. 2 is existing isolated form high withstand voltage FET sampling pipe structural representation two.
Fig. 3 is the relation schematic diagram of existing egg type isolated form high withstand voltage FET voltage endurance capability and egg type height.
Fig. 4 is the overlooking the structure diagram of isolated form high withstand voltage FET of the present invention.
Fig. 5 is isolated form high withstand voltage FET embodiment partial enlarged drawing of the present invention, shows sampling pipe and is sampled pipe
The partial enlargement of region portions.
Fig. 6 is the cross section structure diagram one of sampling pipe embodiment of the present invention, shows A-A positions sectional structure in Fig. 4.
Fig. 7 is the cross section structure diagram of isolated form high withstand voltage FET embodiment of the present invention, its structure as shown in Figure 6
Sampling pipe and be sampled pipe and be combined into.
Fig. 8 is the cross section structure diagram two of sampling pipe embodiment, shows B-B positions sectional structure in Fig. 5.
Fig. 9 is the schematic equivalent circuit that the present invention applies.
Embodiment
As shown in Fig. 4 combinations Fig. 5, the present invention has the isolated form high withstand voltage FET of current sample function, including：Knot
One sampling pipe 301 of structure identical and multiple parallel connections are sampled pipe 302, and sampling pipe 301 is being sampled pipe finger-like array junctions more than 302
Separate to be formed at the source region 202 on structure periphery, sampling pipe 301 and be sampled pipe 302 and share drain region 201 and polysilicon field grid 109,
Sampling pipe source region 211 and it is sampled between pipe source region 212 there is high withstand voltage buffering area in the position close to polysilicon gate 109
210, high withstand voltage buffering area 210 is made up of silicon substrate P type substrate, and high withstand voltage buffering area 210 will be adopted across polysilicon gate 109
Sample pipe and be sampled pipe source region 211 and 212, substrate p-type trap 303b and 303a, p-type doped region 304b and 304a isolation；Sampling pipe
Polysilicon gate is collectively forming complete closed-loop shaped polysilicon gate 109 with being sampled pipe polysilicon gate and be connected；Polysilicon
Grid 109 is across sampling pipe and the N-type drift for being sampled pipe source region 211 and 212, substrate p-type trap 303b and 303a and source region
Area 302b and 302a, sampling pipe area width W are 1 micron~100 microns, sampling pipe and the N-type drift region for being sampled pipe source region
Width S between 302b and 302a is 5 microns~100 microns, and the height D of high withstand voltage buffering area 210 is 5 microns~50 microns, wide
Spend L it is bigger 2 microns than the width S between sampling pipe and the N-type drift region 302b and 302a that are sampled pipe source region~20 microns, sampling
The N-type drift region 302b and 302a for managing and being sampled pipe source region 211 and 212, substrate p-type trap 303b and 303a and source region are passed through
Sphering processing is crossed, rounded form is configured to and improves voltage endurance capability.
As shown in fig. 6, sampling pipe embodiment of the present invention, including：The N-type drift region 102 on the top of P type substrate silicon substrate 101,
First N+ active areas 106 and substrate p-type trap 103 are connected together to form source region 202 by the extraction of P+ active areas 108 with metal, N-type
Drift region 102 encases whole source region 202 and isolates substrate p-type trap 103 and P type substrate silicon substrate 101, and field oxygen isolation 105 is formed
On the top of N-type drift region 102, the first p-type doped region 104 is located at the top of N-type drift region 102, the 2nd N+ of N-type drift region 102
Active area 107, which is drawn, forms drain region 201, and the second p-type doping 104a formed below of source region 202, field oxygen isolates the 105, first p-type
Drawn with the first metal 111 covered with polysilicon 109, the polysilicon above the p-type of doped region 104 and second doping 104a and form source
Area's polysilicon gate, field oxygen is isolated on 105 is connected in one covered with polysilicon 110 with the second metal 112 and the 2nd N+ active areas 107
Rise and form drain region polysilicon field plate, there is the 3rd metal 113, the 3rd metal 113 and source region polysilicon in the side of the first metal 111
Grid 109 connects together.
Add as shown in fig. 7, sharing drain region 201 using the structure shown in two sampling pipe embodiments of the present invention and forming sampling pipe
It is sampled the structure of pipe.
As shown in figure 8, B-B positions sectional structure in Fig. 5 of the present invention, the first p-type doped region 104 is located at N-type drift region 102
With the top of P type substrate silicon substrate 101, i.e. the first p-type doped region and P type substrate silicon substrate 101 has vertical direction to have overlapping region,
Vertical direction refers to from the direction shown in the metal 111 of P type substrate silicon substrate 101 to the first；First p-type doped region 104 is located at p-type
The width of the upper part of substrate silicon substrate 101 is that O is 0 micron~100 microns, i.e. the first p-type doped region and P type substrate silicon substrate
101 width for having vertical direction overlapping region are 0 micron~100 microns.
The present invention is described in detail above by embodiment and embodiment, but these are not composition pair
The limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of isolated form high withstand voltage FET, there is current sample function, including one sampling pipe (301) of structure identical
Pipe (302) is sampled with least one, it is characterised in that：Sampling pipe (301) is being sampled the source region (202) on pipe (302) periphery
Place's separation is formed, and sampling pipe (301) and is sampled pipe (302) shared drain region (201) and polysilicon gate (109), sampling pipe source
Area (211) and it is sampled between pipe source region (212) there is high withstand voltage buffering area in the position close to polysilicon gate (109)
(210), high withstand voltage buffering area (210) is made up of silicon substrate P type substrate, and high withstand voltage buffering area (210) is across polysilicon gate
(109), by sampling pipe and be sampled pipe source region (211 and 212), substrate p-type trap (303b and 303a), p-type doped region (304b and
304a) it is isolated from each other；Sampling pipe polysilicon gate is collectively forming complete closed-loop shaped with being sampled pipe polysilicon gate and be connected
Polysilicon gate (109)；Polysilicon gate (109) is across sampling pipe and is sampled pipe source region (211 and 212), substrate p-type trap
The N-type drift region of (303b and 303a) and source region (302b and 302a).
2. isolated form high withstand voltage FET as claimed in claim 1, it is characterised in that：The sampling pipe is sampled pipe bag
Include：
The N-type drift region (102) on P type substrate silicon substrate (101) top, the first N+ active areas (106) and substrate p-type trap (103)
Connect together to form source region (202) with metal by (108) extraction of P+ active areas, N-type drift region (102) encases whole source region
(202) substrate p-type trap (103) and P type substrate silicon substrate (101) are isolated, field oxygen isolation (105) is formed in N-type drift region
(102) top, the first p-type doped region (104) are located at N-type drift region (102) top, and N-type drift region (102) is active with the 2nd N+
Area (107), which is drawn, forms drain region (201), source region (202) the second p-type doping (104a) formed below, field oxygen isolation (105),
Covered with polysilicon gate (109), the polysilicon gate above first p-type doped region (104) and the second p-type doping (104a)
(109) drawn with the first metal (111) and form source region polysilicon gate, used in field oxygen isolation (105) covered with polysilicon (110)
Second metal (112) and the 2nd N+ active areas (107) connect together to form drain region polysilicon field plate, other in the first metal (111)
Side has the 3rd metal (113), and the 3rd metal (113) connects together with source region polysilicon gate (109).
3. isolated form high withstand voltage FET as claimed in claim 2, it is characterised in that：First p-type doped region (104) is located at
N-type drift region (102) and P type substrate silicon substrate (101) top, the first p-type doped region (104) are located at P type substrate silicon substrate
(101) width (O) of upper part is 0 micron~100 microns.
4. isolated form high withstand voltage FET as claimed in claim 1, it is characterised in that：Sampling pipe and it is sampled pipe source region
The N-type drift region (302b and 302a) of (211 and 212), substrate p-type trap (303b and 303a) and source region is by sphering
Reason, is configured to rounded form.
5. isolated form high withstand voltage FET as claimed in claim 1, it is characterised in that：Sampling pipe area width (W) is 1 micro-
Rice~100 microns.
6. isolated form high withstand voltage FET as claimed in claim 1, it is characterised in that：Sampling pipe and it is sampled pipe source region
Width (S) between N-type drift region (302b and 302a) is 5 microns~100 microns.
7. isolated form high withstand voltage FET as claimed in claim 5, it is characterised in that：High withstand voltage buffering area (210) height
(D) it is 5 microns~50 microns, width (L) is than between sampling pipe and the N-type drift region (302b and 302a) for being sampled pipe source region
Width (S) is big 2 microns~and 20 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753318.2A CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753318.2A CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752518A CN104752518A (en) | 2015-07-01 |
| CN104752518B true CN104752518B (en) | 2018-02-06 |
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ID=53591911
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310753318.2A Active CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
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| CN (1) | CN104752518B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| JP5487852B2 (en) * | 2008-09-30 | 2014-05-14 | サンケン電気株式会社 | Semiconductor device |
| CN103091533B (en) * | 2011-11-03 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
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2013
- 2013-12-31 CN CN201310753318.2A patent/CN104752518B/en active Active
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| CN104752518A (en) | 2015-07-01 |
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