CN104752518A - Isolated high-voltage-resistance field effect transistor - Google Patents
Isolated high-voltage-resistance field effect transistor Download PDFInfo
- Publication number
- CN104752518A CN104752518A CN201310753318.2A CN201310753318A CN104752518A CN 104752518 A CN104752518 A CN 104752518A CN 201310753318 A CN201310753318 A CN 201310753318A CN 104752518 A CN104752518 A CN 104752518A
- Authority
- CN
- China
- Prior art keywords
- type
- region
- sampled
- pipe
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 24
- 238000005070 sampling Methods 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 19
- 230000003139 buffering effect Effects 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241001234523 Velamen Species 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an isolated high-voltage-resistance field effect transistor with a current sampling function. The field effect transistor comprises a sampling tube and at least one sampled tube of the same structures, wherein the sampling tube is separately formed at a source region at the periphery of a multi-finger array structure of the sampled tube; a drain region and a polycrystalline silicon field gate are shared by the sampling tube and the sampled tube; a high-voltage-resistance buffer region is arranged at a position close to the polycrystalline silicon gate between the sampling tube source region and the sampled tube source region, consists of a silicon substrate P type substrate and crosses the polycrystalline silicon gate to isolate the source regions of the sampling tube and the sampled tube, a substrate P type well and a P type doped region; the polycrystalline silicon gate crosses the source regions of the sampling tube and the sampled tube, the substrate P type well and an N type drift region of the source region. According to the transistor, the integrated area can be reduced on the premise that high voltage resistance of the sampling tube and the sampled tube is kept, the effective area of the sampled tube is increased, and the sampling ratio of the device can be increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the high withstand voltage field effect transistor of a kind of isolated form.
Background technology
As shown in Figure 1, domain realizes being divided into discrete type and integrated-type two kinds the high withstand voltage field effect transistor sampling pipe structure of isolated form conventional at present.Discrete type sampling pipe be be sampled pipe side place one independently small tubes as sampling pipe, the drift region, drain region of sampling pipe, source region and channel region are with to be sampled pipe all the same with manufacture technics in size, namely section A-A is identical with being sampled pipe at sampling pipe, the current characteristics that such guarantee two pipes are tested under identical voltage conditions is all identical, can ensure sample rate current like this and is sampled the linear relationship of electric current and reaches sampling object.But the shortcoming of this design is:
1. need extra area to place circular sampling pipe, and sampling pipe and the drain terminal being sampled pipe need to be connected together by encapsulation, sampling pipe encapsulation needs pressure welding point, further increases the area of sampling pipe;
2. the effective raceway groove of minimum sampling pipe is exactly the girth of circle, and the electric current of such sampling pipe cannot do little, and corresponding sampling cannot be done greatly than (sampling pipe electric current/be sampled tube current, under same test condition);
In order to solve the problem of additional areas waste, also has a kind of sampling pipe design of integrated-type, namely extract the pipe position be sampled in the middle of pipe and place the high withstand voltage field effect transistor of egg type as sampling pipe as shown in Figure 2, integrated like this sampling pipe and the drain region being sampled pipe are shared, unnecessary extra increase pressure welding point and cause the increase of area; Sampling pipe is placed on the centre being sampled pipe, and the matching properties of two pipes is fine, and the impact by process deviation is very little; Sampling pipe current capacity can be adjusted by the height of middle egg type sampling pipe, can do ratio of sampling greatly.But design so equally also has its shortcoming:
1. the position wasting a velamen sampling pipe, to place sampling pipe, is sampled pipe array heights and designs higher, larger to the loss being sampled tube current ability;
2. the egg type height of sampling pipe can not do very little, does less, withstand voltage lower, as shown in Figure 6.
Summary of the invention
The technical problem to be solved in the present invention be to provide a kind of keep sampling pipe and be sampled pipe the withstand voltage prerequisite of height under can reduce integrated area, increase be sampled pipe effective area, can increase sample ratio isolated form height withstand voltage field effect transistor.
For solving the problems of the technologies described above, the high withstand voltage field effect transistor of isolated form with current sample function provided by the invention, comprise: the identical sampling pipe of structure 301 and at least one be sampled pipe 302(when have multiple be sampled pipe time, respectively be sampled pipe to be connected in parallel), sampling pipe 301 is separated at source region 202 place being sampled pipe finger-like more than 302 array structure periphery and is formed, sampling pipe 301 and be sampled pipe 302 and share drain region 201 and polysilicon field grid 109, sampling pipe source region 211 and be sampled between pipe source region 212, near the position of polysilicon gate 109, there is high withstand voltage buffering area 210, high withstand voltage buffering area 210 is made up of silicon substrate P type substrate, high withstand voltage buffering area 210 is across polysilicon gate 109, by sampling pipe and be sampled pipe source region 211 and 212, substrate P type trap 303b and 303a, P type doped region 304b and 304a is isolated from each other, sampling pipe polysilicon gate be sampled pipe polysilicon gate and be connected and common form complete closed-loop shaped polysilicon gate 109, polysilicon gate 109 is across sampling pipe and be sampled pipe source region 211 and 212, the N-type drift region 302b in substrate P type trap 303b and 303a and source region and 302a.
Wherein, described sampling pipe or be sampled the N-type drift region 102 that pipe comprises P type substrate silicon substrate 101 top, one N+ active area 106 and substrate P type trap 103 are connected together by P+ active area 108 extraction metal and form source region 202, N-type drift region 102 encases whole source region 202 and substrate P type trap 103 and P type substrate silicon substrate 101 is isolated, field oxygen isolation 105 is formed in N-type drift region 102 top, one P type doped region 104 is positioned at N-type drift region 102 top, N-type drift region 102 is drawn with the 2nd N+ active area 107 and is formed drain region 201, the 2nd P type doping 104a is formed below source region 202, field oxygen isolation 105, polysilicon 109 is coated with above one P type doped region 104 and the 2nd P type doping 104a, this polysilicon is drawn with the first metal 111 and is formed source region polysilicon gate, oxygen isolation 105 is coated with polysilicon 110 second metal 112 and the 2nd N+ active area 107 to connect together formation drain region polysilicon field plate, at the first metal 111 side, there is the 3rd metal 113, 3rd metal 113 connects together with source region polysilicon gate 109.
Wherein, a P type doped region 104 is positioned at N-type drift region 102 and P type substrate silicon substrate 101 top, and the width that a P type doped region 104 is positioned at P type substrate silicon substrate 101 upper part is O is 0 micron ~ 10 microns.
Wherein, sampling pipe and be sampled pipe source region 211 and 212, the N-type drift region 302b in substrate P type trap 303b and 303a and source region and 302a all through sphering process, is shaped to rounded form.
Wherein, sampling pipe area width W is 1 micron ~ 100 microns.
Wherein, sampling pipe and the width S be sampled between the N-type drift region 302b in pipe source region and 302a are 5 microns ~ 100 microns.
Wherein, high withstand voltage buffering area 210 height D is 5 microns ~ 50 microns, and width L is than sampling pipe and large 2 microns ~ 20 microns of width S being sampled between the N-type drift region 302b in pipe source region and 302a.
The present invention adopts the high withstand voltage field effect transistor of two structure same separation types, by the pipe of current sample being intercepted the mode of a section from the periphery source of the pipe be sampled, substantially increase the integrated level of sampling pipe, design high withstand voltage buffering area to be inserted in sampling pipe and to be sampled method between the N-type drift region of pipe source region, the substrate P type trap of current sample pipe and can be sampled with the injection of the substrate P type trap N-type of pipe that drift region is completely isolated opens, in realizing circuit work, two pipes is completely isolated, not electric leakage, and the sampling pipe under ensure that small size has and is sampled the same voltage endurance capability of pipe.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the high withstand voltage field effect transistor sampling pipe structural representation one of existing isolated form.
Fig. 2 is the high withstand voltage field effect transistor sampling pipe structural representation two of existing isolated form.
Fig. 3 is the relation schematic diagram of the high withstand voltage field effect transistor voltage endurance capability of existing egg type isolated form and egg type height.
Fig. 4 is the plan structure schematic diagram of the high withstand voltage field effect transistor of isolated form of the present invention.
Fig. 5 is the high withstand voltage field effect transistor embodiment partial enlarged drawing of isolated form of the present invention, display sampling pipe and the partial enlargement being sampled pipe region portions.
Fig. 6 is the sectional structure schematic diagram one of sampling pipe embodiment of the present invention, A-A position sectional structure in display Fig. 4.
Fig. 7 is the sectional structure schematic diagram of the high withstand voltage field effect transistor embodiment of isolated form of the present invention, its as shown in Figure 6 structure sampling pipe and be sampled pipe and be combined into.
Fig. 8 is the sectional structure schematic diagram two of sampling pipe embodiment, B-B position sectional structure in display Fig. 5.
Fig. 9 is the schematic equivalent circuit that the present invention applies.
Embodiment
As shown in Fig. 4 composition graphs 5, the present invention has the high withstand voltage field effect transistor of isolated form of current sample function, comprise: the sampling pipe 301 that structure is identical and multiple parallel connection are sampled pipe 302, sampling pipe 301 is separated at source region 202 place being sampled pipe finger-like more than 302 array structure periphery and is formed, sampling pipe 301 and be sampled pipe 302 and share drain region 201 and polysilicon field grid 109, sampling pipe source region 211 and be sampled between pipe source region 212, near the position of polysilicon gate 109, there is high withstand voltage buffering area 210, high withstand voltage buffering area 210 is made up of silicon substrate P type substrate, high withstand voltage buffering area 210 is across polysilicon gate 109, by sampling pipe and be sampled pipe source region 211 and 212, substrate P type trap 303b and 303a, P type doped region 304b and 304a isolates, sampling pipe polysilicon gate be sampled pipe polysilicon gate and be connected and common form complete closed-loop shaped polysilicon gate 109, polysilicon gate 109 is across sampling pipe and be sampled pipe source region 211 and 212, the N-type drift region 302b in substrate P type trap 303b and 303a and source region and 302a, sampling pipe area width W is 1 micron ~ 100 microns, sampling pipe and the width S be sampled between the N-type drift region 302b in pipe source region and 302a are 5 microns ~ 100 microns, high withstand voltage buffering area 210 height D is 5 microns ~ 50 microns, width L is than sampling pipe and large 2 microns ~ 20 microns of width S being sampled between the N-type drift region 302b in pipe source region and 302a, sampling pipe and be sampled pipe source region 211 and 212, the N-type drift region 302b in substrate P type trap 303b and 303a and source region and 302a is all through sphering process, be configured as rounded form and improve voltage endurance capability.
As shown in Figure 6, sampling pipe embodiment of the present invention, comprise: the N-type drift region 102 on P type substrate silicon substrate 101 top, one N+ active area 106 and substrate P type trap 103 are connected together by P+ active area 108 extraction metal and form source region 202, N-type drift region 102 encases whole source region 202 and substrate P type trap 103 and P type substrate silicon substrate 101 is isolated, field oxygen isolation 105 is formed in N-type drift region 102 top, one P type doped region 104 is positioned at N-type drift region 102 top, N-type drift region 102 is drawn with the 2nd N+ active area 107 and is formed drain region 201, the 2nd P type doping 104a is formed below source region 202, field oxygen isolation 105, polysilicon 109 is coated with above one P type doped region 104 and the 2nd P type doping 104a, this polysilicon is drawn with the first metal 111 and is formed source region polysilicon gate, oxygen isolation 105 is coated with polysilicon 110 second metal 112 and the 2nd N+ active area 107 to connect together formation drain region polysilicon field plate, at the first metal 111 side, there is the 3rd metal 113, 3rd metal 113 connects together with source region polysilicon gate 109.
As shown in Figure 7, adopt the structure shown in two sampling pipe embodiments of the present invention to share drain region 201 to form sampling pipe and add the structure being sampled pipe.
As shown in Figure 8, B-B position sectional structure in Fig. 5 of the present invention, one P type doped region 104 is positioned at N-type drift region 102 and P type substrate silicon substrate 101 top, namely a P type doped region and P type substrate silicon substrate 101 have vertical direction to have overlapping region, and vertical direction refers to from the direction shown in P type substrate silicon substrate 101 to the first metal 111; The width that one P type doped region 104 is positioned at P type substrate silicon substrate 101 upper part is O is 0 micron ~ 100 microns, and namely a P type doped region and P type substrate silicon substrate 101 have the width of vertical direction overlapping region to be 0 micron ~ 100 microns.
Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. the high withstand voltage field effect transistor of isolated form has current sample function, comprise an identical sampling pipe (301) of structure and at least one is sampled pipe (302), it is characterized in that: sampling pipe (301) is separated at source region (202) place being sampled pipe (302) periphery and is formed, sampling pipe (301) and be sampled pipe (302) and share drain region (201) and polysilicon field grid (109), sampling pipe source region (211) and be sampled between pipe source region (212), near the position of polysilicon gate (109), there is high withstand voltage buffering area (210), high withstand voltage buffering area (210) is made up of silicon substrate P type substrate, high withstand voltage buffering area (210) is across polysilicon gate (109), by sampling pipe and be sampled pipe source region (211 and 212), substrate P type trap (303b and 303a), P type doped region (304b and 304a) is isolated from each other, sampling pipe polysilicon gate be sampled pipe polysilicon gate and be connected and common form complete closed-loop shaped polysilicon gate (109), polysilicon gate (109) across sampling pipe and be sampled pipe source region (211 and 212), substrate P type trap (303b and 303a) and source region N-type drift region (302b and 302a) from.
2. the high withstand voltage field effect transistor of isolated form as claimed in claim 1, is characterized in that: described sampling pipe or be sampled pipe and comprise:
The N-type drift region (102) on P type substrate silicon substrate (101) top, one N+ active area (106) and substrate P type trap (103) are connected together by P+ active area (108) extraction metal and form source region (202), N-type drift region (102) encases whole source region (202) by substrate P type trap (103) and P type substrate silicon substrate (101) isolation, field oxygen isolation (105) is formed in N-type drift region (102) top, one P type doped region (104) is positioned at N-type drift region (102) top, N-type drift region (102) is drawn with the 2nd N+ active area (107) and is formed drain region (201), below, source region (202) is formed with the 2nd P type doping (104a), field oxygen isolation (105), one P type doped region (104) and the 2nd P type doping (104a) top are coated with polysilicon (109), this polysilicon is drawn with the first metal (111) and is formed source region polysilicon gate, oxygen isolation (105) is coated with polysilicon (110) the second metal (112) and the 2nd N+ active area (107) to connect together formation drain region polysilicon field plate, at the first metal (111) side, there is the 3rd metal (113), 3rd metal (113) and source region polysilicon gate (109) connect together.
3. the high withstand voltage field effect transistor of isolated form as claimed in claim 2, it is characterized in that: a P type doped region (104) is positioned at N-type drift region (102) and P type substrate silicon substrate (101) top, the width that a P type doped region (104) is positioned at P type substrate silicon substrate (101) upper part is 0 micron ~ 100 microns for (O).
4. the high withstand voltage field effect transistor of isolated form as claimed in claim 1, it is characterized in that: sampling pipe and be sampled pipe source region (211 and 212), substrate P type trap (303b and 303a) and source region N-type drift region (302b and 302a) all through sphering process, be configured as rounded form.
5. the high withstand voltage field effect transistor of isolated form as claimed in claim 1, is characterized in that: sampling pipe area width (W) is 1 micron ~ 100 microns.
6. the high withstand voltage field effect transistor of isolated form as claimed in claim 1, is characterized in that: the width (S) between sampling pipe and the N-type drift region (302b and 302a) being sampled pipe source region is 5 microns ~ 100 microns.
7. the high withstand voltage field effect transistor of isolated form as claimed in claim 5, it is characterized in that: high withstand voltage buffering area (210) highly (D) is 5 microns ~ 50 microns, larger than the width (S) between sampling pipe and the N-type drift region (302b and 302a) being sampled pipe source region 2 microns ~ 20 microns of width (L).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753318.2A CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753318.2A CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752518A true CN104752518A (en) | 2015-07-01 |
| CN104752518B CN104752518B (en) | 2018-02-06 |
Family
ID=53591911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310753318.2A Active CN104752518B (en) | 2013-12-31 | 2013-12-31 | Isolated form high withstand voltage FET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752518B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046859A1 (en) * | 1999-02-05 | 2000-08-10 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| CN101714558A (en) * | 2008-09-30 | 2010-05-26 | 三垦电气株式会社 | A semiconductor device |
| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
-
2013
- 2013-12-31 CN CN201310753318.2A patent/CN104752518B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046859A1 (en) * | 1999-02-05 | 2000-08-10 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| CN101714558A (en) * | 2008-09-30 | 2010-05-26 | 三垦电气株式会社 | A semiconductor device |
| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752518B (en) | 2018-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105448961B (en) | The terminal protection structure of superjunction devices | |
| CN103633083B (en) | Form the domain structure of the resistance to compressive resistance of superelevation | |
| CN108122975A (en) | Superjunction devices | |
| CN101969073A (en) | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor | |
| CN106816468B (en) | Lateral diffusion metal oxide semiconductor field effect transistor with RESURF structure | |
| CN109755241A (en) | A kind of power MOSFET device | |
| CN103700697B (en) | Longitudinally super-junction metal oxide field effect transistor | |
| CN105070756A (en) | Superhigh-voltage LDMOS device structure | |
| CN106057868A (en) | Longitudinal super-junction enhanced MIS HEMT device | |
| CN103050523B (en) | Insulated gate bipolar transistor and manufacture method thereof | |
| CN103928527A (en) | Junction terminal structure of transverse high-voltage power semiconductor device | |
| CN102832213B (en) | Lateral insulator gate bipolar transistor (LIGBT) device with electronic static discharge (ESD) protection function | |
| CN109755289A (en) | A kind of groove-shaped super junction power device | |
| CN106571388B (en) | Transverse diffusion metal oxide semiconductor field effect pipe with RESURF structures | |
| CN106158927A (en) | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method | |
| CN103354237B (en) | Semiconductor device | |
| CN103839982A (en) | Planar gate super-junction product gate layout structure | |
| WO2021223357A1 (en) | Semiconductor device | |
| CN107591445B (en) | Super junction device and manufacturing method thereof | |
| CN104752518A (en) | Isolated high-voltage-resistance field effect transistor | |
| CN203690304U (en) | Vertical super junction metal-oxide -semiconductor field effect transistor | |
| CN104714073B (en) | The current sampling circuit realized with LDMOS device | |
| CN106941122A (en) | Semiconductor device and its manufacture method | |
| WO2019128587A1 (en) | Semiconductor power device | |
| WO2024131255A1 (en) | Semiconductor superjunction power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |