CN104752314A - Semiconductor device with STI structure and preparation method - Google Patents
Semiconductor device with STI structure and preparation method Download PDFInfo
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- CN104752314A CN104752314A CN201310743496.7A CN201310743496A CN104752314A CN 104752314 A CN104752314 A CN 104752314A CN 201310743496 A CN201310743496 A CN 201310743496A CN 104752314 A CN104752314 A CN 104752314A
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- reflecting wall
- sti
- sti structure
- wall structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The invention provides a semiconductor device with an STI structure and a preparation method. The preparation method is that a reflecting wall is formed in the STI structure while the STI structure is formed; the reflecting wall can stop light reflecting to photoresist to cause excessive exposure during performing subsequent photoetching process for the semiconductor device with the STI structure, thus the photoresist can be kept in good appearance all the time, and a device with an ideal appearance can be prepared; meanwhile, an anti-reflection layer for assisting photoetching is not needed, so that the production cost can be reduced.
Description
Technical field
The present invention relates to semiconductor preparation field, be specifically related to a kind of semiconductor device and the preparation method with sti structure.
Background technology
In the preparation technology of semiconductor chip, STI(ShallowTrenchIsolation, shallow trench isolation from) play very important status, because it can realize highdensity isolation, be widely used in Deep submicron devi8 and DRAM(DynamicRandomAccessMemory, dynamic random access memory) etc. the manufacture of high density memory circuit, but constantly reducing along with device critical dimensions, problem is also appeared in one's mind thereupon.
In the preparation technology of some STI, the sidewall forming STI is generally skew wall, simultaneously in semiconductor preparing process, one complete operation may need through carrying out tens of roads photoetching process, such as, after carrying out first time Patternized technique formation STI, follow-uply also need to carry out a Patternized technique again other techniques (as techniques such as ion implantations) are carried out to STI, but those skilled in the art find, when carrying out subsequent pattern metallization processes, the photoresist mask above device very easily produces the generation of overexposure phenomenon.
As shown in Figure 1, after etching forms sti structure, because process requirements also needs to carry out a Patternized technique again, photoresist is remained with above part sti structure sidewall, but in exposure imaging process, the skew wall that light runs into sti structure can produce reflection, after constantly reflecting, and the residue photoresist (or claiming photoresist) likely reflexed to above device, cause photoresist over-exposed.As shown in the figure, light constantly reflects in sti structure, finally the photoresist retained above sti structure sidewall is exposed, and then result in photoresist and produce a certain amount of loss, unsatisfactory for mask carries out the device topography that follow-up technique prepares with this photoresist, this is the main contributor causing fault.
Because photoetching process plays very important role in semiconductor preparation field always, it directly affects the device topography and electric property finally prepared, and the precision therefore how improving photoetching process is the very important research direction of semicon industry always.In the prior art, general employing applies one deck anti-reflecting layer in advance to reduce the impact of reflection on photoresist of light bottom photoresist, but its cost is higher, and cannot be suitable in the technique including ion implantation: when some carries out ion implantation technology, need to carry out ion processes to remain photoresist for mask to specific region, but because anti-reflecting layer can form a barrier effect to the ion injected, and then effect is injected in impact.In order to solve traditional anti-reflecting layer limitation in process, develop the comparatively advanced anti-reflecting layer of one at present, the impact of this anti-reflecting layer on ion implantation is less, but uses the cost of anti-reflecting layer very high, adds production cost equally.
Therefore, how under the prerequisite ensureing production cost, improve photoetching process and also improve the device topography finally prepared, always for those skilled in the art endeavour the direction of research.
Summary of the invention
The present invention is in STI preparation technology, by when carrying out Patternized technique, the photoetching offset plate figure of reflecting wall structure is defined in STI, and reflecting wall structure is formed while the final STI that formed, this reflecting wall structure can effectively be avoided when carrying out subsequent optical carving technology, due to the reflection of light and then cause the phenomenon of overexposure to produce to photoresist.
The technical solution used in the present invention is:
A preparation method for sti structure, wherein, comprises the following steps:
Semi-conductive substrate is provided, the upper surface of described Semiconductor substrate is formed with etching barrier layer and hard mask layer successively according to order from bottom to top;
Carry out Patternized technique, form the photoresist with STI figure and reflecting wall figure on the surface of described hard mask layer;
Continuation for mask, etches the upper surface of described hard mask layer to described etching barrier layer with described photoresist, after removing described photoresist, in residue hard mask layer, forms STI figure and reflecting wall figure;
With described residue hard mask layer for mask etching forms the sti structure with reflecting wall structure, and remove the remaining hard mask layer of types of flexure and remaining etching barrier layer.
The preparation method of above-mentioned sti structure, wherein, after formation has the residue hard mask layer of STI figure and reflecting wall figure, if the size of described reflecting wall figure is greater than process requirements, anisotropic etching technics is then adopted to carry out selective etch, to reduce the width of reflecting wall figure in this residue hard mask layer to residue hard mask layer.
The preparation method of above-mentioned sti structure, wherein, residue is before hard mask layer carries out selective etch, first adopts Patternized technique to utilize photoresist to be covered in the region except the hard mask layer of reflecting wall figure.
The preparation method of above-mentioned sti structure, wherein, the height of described reflecting wall structure is less than the described sti structure degree of depth.
The preparation method of above-mentioned sti structure, wherein, the difference range between described reflecting wall structure height and the described sti structure degree of depth is 70nm ~ 270nm.
The preparation method of above-mentioned sti structure, wherein, the scope of the beeline between described reflecting wall structure and adjacent sti structure sidewall and the width sum of this reflecting wall structure is 50 ~ 200nm.
The preparation method of above-mentioned sti structure, wherein, the scope of the beeline between adjacent described reflecting wall structure and the width sum of this reflecting wall structure is 65 ~ 260nm.
There is a semiconductor device for sti structure, wherein, comprise a substrate, described substrate is formed with sti structure, and be also provided with reflecting wall structure in the lower surface of this sti structure;
By the light of described reflecting wall structure reflects in Patternized technique, to avoid the photoresist mask overexposure in Patternized technique.
Above-mentioned semiconductor device, wherein, described sti structure and reflecting wall structure are formed by etched substrate simultaneously.
Above-mentioned semiconductor device, wherein, described reflecting wall structure height is lower than the described sti structure degree of depth, and the difference between described reflecting wall structure height and the described sti structure degree of depth is 70nm ~ 270nm.
Above-mentioned semiconductor device, wherein, the beeline between described reflecting wall structure and adjacent sti structure sidewall and the width sum of this reflecting wall structure are 50 ~ 200nm.
Above-mentioned semiconductor device, wherein, the beeline between adjacent described reflecting wall structure and the width sum of reflecting wall structure are 65 ~ 260nm.
Sti structure provided by the invention is when carrying out follow-up Patternized technique, light constantly reflects between sti structure sidewall and reflecting wall structure, can effectively avoid due to light reflection and then phenomenon photoresist being caused to overexposure, also can have with good pattern when ensure that the Patternized technique of photoresist after completing STI, and then to make the device finally prepared more meet process requirements, and then boost device performance and product yield.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the schematic diagram of prior art overexposure when carrying out photoetching;
Fig. 2-8A is the flow chart of STI preparation method provided by the invention;
Fig. 8 B is the sti structure vertical view that the present invention prepares formation;
Fig. 9 be the present invention prepare there is the schematic diagram that STI device carries out follow-up photoetching.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The invention provides a kind of STI preparation method, concrete steps are as follows:
Step S1: first provide semi-conductive substrate 1, form shallow trench in order to preparation, on this substrate, table 1 face is formed with etching barrier layer 2 and hard mask layer 3 from bottom to top successively, as shown in Figure 2.
Step S2: carry out patterning and etching technics, above hard mask layer 3, form the photoresist 4 with STI figure and reflecting wall figure, concrete steps are:
1) hard mask layer 3 upper surface is covered by spin coating one deck photoresist;
2) mask plate having photoengraving pattern by carries out exposure imaging technique and forms the photoresist 4 with STI figure and reflecting wall figure;
3) stop for mask etches hard mask layer 3 to etching barrier layer 2 upper surface downwards with photoresist 4, and remove photoresist 4, form the residue hard mask layer 3 ' with STI figure and reflecting wall structure graph, as shown in Figure 4.
After above step completes, if due to technology or cost limit and cause the residue hard mask layer 3 ' size obtaining reflecting wall structure graph to be greater than process requirements, the width that following technique reduces the residue hard mask layer 3 ' of reflecting wall figure further can be proceeded:
Step S2-A: carry out Patternized technique, utilizes photoresist to be covered in the region except the hard mask layer of reflecting wall figure, and exposes the residue hard mask layer 3 ' of reflecting wall structure graph, as shown in Figure 5;
Step S2-B: adopt the first residue hard mask layer 3 ' of anisotropic etch process to reflecting wall structure graph to carry out selective etch, to reduce the first residue hard mask layer 3 ' width of reflecting wall structure graph, remove photoresist, as shown in figs. 6-7.
Step S3: to remain hard mask layer 3 " for mask etching forms sti structure and reflecting wall structure 6, and removes types of flexure residue hard mask layer 3 " and remaining etching barrier layer, structure shown in final formation Fig. 8 A.As shown in the figure, reflecting wall structure 6 height of formation will lower than the degree of depth of sti structure (shallow trench namely formed), and preferably, the difference range between reflecting wall structure 6 height and the sti structure degree of depth is 70nm ~ 270nm;
Fig. 8 B is depicted as the vertical view of Fig. 8 A, when carrying out first time Patternized technique, corresponding mask plate is selected to define distance between distance between reflecting wall structure 6 and STI sidewall 7 and neighboring reflection wall construction 6 according to process requirements, further, as shown in Figure 8 B, the scope of the width sum D1 of the beeline between reflecting wall structure 6 and adjacent sti structure sidewall and this reflecting wall structure is 50 ~ 200nm; The scope of the width sum D2 of the beeline between neighboring reflection wall construction and this reflecting wall structure is 65 ~ 260nm.
After having prepared the device shown in Fig. 8 A, because technique needs the photoetching process also may will carrying out one or many, as shown in Figure 9, after Patternized technique, photoresist is formed above part sti structure sidewall, and carry out exposure imaging technique, in the process, light runs into STI skew wall and produces reflection, but because the present invention defines reflecting wall structure in the preparation of sti structure sidewall, light can not carry out re-expose to the photoresist above device after constantly reflecting between each reflecting wall structure of sti structure sidewall, also can have with good pattern when ensure that the Patternized technique of photoresist after completing STI, and then to make the device finally prepared more meet process requirements, and then boost device performance and product yield.
Further, because the present invention defines the position relationship of difference in height and reflecting wall and STI sidewall between the height of reflecting wall structure 6 and shallow trench, at utmost can reduce reflection ray and re-expose is carried out to the photoresist above device, and then ensure the pattern of photoresist, finally prepare ideal device.Meanwhile, the reflecting wall structure that the present invention is finally prepared 6 pairs of devices also can not impact, and remove without the need to adopting additional technique.
Present invention also offers a kind of semiconductor device with sti structure, as shown in figures 8 a-8b, comprise a substrate 1 ', in substrate 1 ', be formed with sti structure, and be also provided with reflecting wall structure 6 in the lower surface of this sti structure, wherein, sti structure and reflecting wall structure are formed by etched substrate simultaneously, by penetrating wall construction reflection light in a lithographic process, to avoid carrying out in photoetching process, due to light continuous reflection so that overexposure is caused to photoresist, affect photoresist pattern.
Wherein, in an embodiment of the present invention, the scope of the width sum D1 of the beeline between reflecting wall structure 6 and adjacent sti structure sidewall and this reflecting wall structure is 50 ~ 200nm; The scope of the width sum D2 of the beeline between neighboring reflection wall construction and this reflecting wall structure is 65 ~ 260nm; Meanwhile, reflecting wall structure 6 is highly less than the degree of depth of sti structure (i.e. sti trench groove), concrete, and the difference H scope between reflecting wall structure 6 height and sti trench groove depth is 70nm ~ 270nm.
Sti structure provided by the invention is when carrying out Patternized technique, light constantly reflects between sti structure sidewall and reflecting wall structure 6, define position and the height of reflecting wall structure 6 simultaneously, and then effectively avoid due to light reflection and then phenomenon photoresist being caused to overexposure, also can have with good pattern when ensure that the Patternized technique of photoresist after completing STI, and then to make the device finally prepared more meet process requirements, and then boost device performance and product yield.
In sum, owing to present invention employs above technical scheme, while etching forms sti structure, yet forms both reflecting wall structure, this reflecting wall structure can effectively avoid the photoresist of subsequent technique due to the problem being subject to overexposure and then cause pattern undesirable, ensure that and remain a good device topography after sti structure carries out repeatedly Patternized technique again, improve device performance and product yield; Simultaneously, because reflecting wall structure can effectively reflect light, therefore when carrying out Patternized technique, without the need to adopting anti-reflecting layer, photoetching process is improved, therefore also can not the technique follow-up to patterning impact (as techniques such as ion implantation technologies), process variations is little, realisation comparatively strong, can be widely used in having in the semiconductor device fabrication processes of sti structure.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (12)
1. a preparation method for sti structure, is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, the upper surface of described Semiconductor substrate is formed with etching barrier layer and hard mask layer successively according to order from bottom to top;
Carry out Patternized technique, form the photoresist with STI figure and reflecting wall figure on the surface of described hard mask layer;
Continuation for mask, etches the upper surface of described hard mask layer to described etching barrier layer with described photoresist, after removing described photoresist, in residue hard mask layer, forms STI figure and reflecting wall figure;
With described residue hard mask layer for mask etching forms sti structure and reflecting wall structure, and remove the remaining hard mask layer of types of flexure and remaining etching barrier layer.
2. the preparation method of sti structure as claimed in claim 1, it is characterized in that, after formation has the residue hard mask layer of STI figure and reflecting wall figure, if the size of described reflecting wall figure is greater than process requirements, anisotropic etching technics is then adopted to carry out selective etch, to reduce the width of reflecting wall figure in this residue hard mask layer to residue hard mask layer.
3. the preparation method of sti structure as claimed in claim 2, is characterized in that, before residue hard mask layer carries out selective etch, first adopts Patternized technique to utilize photoresist to be covered in the region except the hard mask layer of reflecting wall figure.
4. the preparation method of sti structure as claimed in claim 1, it is characterized in that, the height of described reflecting wall structure is less than the described sti structure degree of depth.
5. the preparation method of sti structure as claimed in claim 4, it is characterized in that, the difference range between described reflecting wall structure height and the described sti structure degree of depth is 70nm ~ 270nm.
6. the preparation method of sti structure as claimed in claim 1, it is characterized in that, the scope of the beeline between described reflecting wall structure and adjacent sti structure sidewall and the width sum of this reflecting wall structure is 50 ~ 200nm.
7. the preparation method of sti structure as claimed in claim 1, it is characterized in that, the scope of the beeline between adjacent described reflecting wall structure and the width sum of this reflecting wall structure is 65 ~ 260nm.
8. there is a semiconductor device for sti structure, it is characterized in that, comprise a substrate, described substrate is formed with sti structure, and be also provided with reflecting wall structure in the lower surface of this sti structure;
By the light of described reflecting wall structure reflects in Patternized technique, to avoid the photoresist mask overexposure in Patternized technique.
9. semiconductor device as claimed in claim 8, it is characterized in that, described sti structure and reflecting wall structure are formed by etched substrate simultaneously.
10. semiconductor device as claimed in claim 8, it is characterized in that, described reflecting wall structure height is lower than the described sti structure degree of depth, and the difference between described reflecting wall structure height and the described sti structure degree of depth is 70nm ~ 270nm.
11. semiconductor device as claimed in claim 8, is characterized in that, the beeline between described reflecting wall structure and adjacent sti structure sidewall and the width sum of this reflecting wall structure are 50 ~ 200nm.
12. semiconductor device as claimed in claim 8, is characterized in that, the beeline between adjacent described reflecting wall structure and the width sum of reflecting wall structure are 65 ~ 260nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841560A (en) * | 2017-11-29 | 2019-06-04 | 台湾积体电路制造股份有限公司 | Barrier structure on isolation structure |
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| CN102403314A (en) * | 2010-09-08 | 2012-04-04 | 上海华虹Nec电子有限公司 | Active area sidewall in bipolar CMOS (Complementary Metal Oxide Semiconductor) process and manufacturing method |
| CN102646573A (en) * | 2011-02-17 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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| JP2009266876A (en) * | 2008-04-22 | 2009-11-12 | Denso Corp | Method of manufacturing semiconductor device |
| CN102403314A (en) * | 2010-09-08 | 2012-04-04 | 上海华虹Nec电子有限公司 | Active area sidewall in bipolar CMOS (Complementary Metal Oxide Semiconductor) process and manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841560A (en) * | 2017-11-29 | 2019-06-04 | 台湾积体电路制造股份有限公司 | Barrier structure on isolation structure |
| US10930502B2 (en) | 2017-11-29 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Blocking structures on isolation structures |
| CN109841560B (en) * | 2017-11-29 | 2021-06-08 | 台湾积体电路制造股份有限公司 | Barrier structures on isolation structures |
| US11621165B2 (en) | 2017-11-29 | 2023-04-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Blocking structures on isolation structures |
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