CN104752178A - Semiconductor device fabrication method - Google Patents
Semiconductor device fabrication method Download PDFInfo
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- CN104752178A CN104752178A CN201310745197.7A CN201310745197A CN104752178A CN 104752178 A CN104752178 A CN 104752178A CN 201310745197 A CN201310745197 A CN 201310745197A CN 104752178 A CN104752178 A CN 104752178A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000005389 semiconductor device fabrication Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000002347 injection Methods 0.000 claims abstract description 27
- 239000007924 injection Substances 0.000 claims abstract description 27
- 230000008021 deposition Effects 0.000 claims abstract description 14
- 238000011049 filling Methods 0.000 claims abstract description 9
- 238000002360 preparation method Methods 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 13
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000007790 solid phase Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device fabrication method. The method comprises forming gates on a semiconductor substrate; forming source/drain regions in the semiconductor substrate on the two sides of the gates; etching the source/drain regions to form grooves, performing preamorphization injection on the groove bottoms and side walls, and performing epitaxial growth to form amorphous regions filling the grooves; performing tensile stress film deposition and solid-phase epitaxial growth on the amorphous regions to form stacked staggered structures in the formed source/drain regions of the semiconductor device. Compared with the prior art, the method has the advantages that the stacked staggered structures can be formed in the formed source/drain regions of the semiconductor device finally as well, and accordingly, the semiconductor device performance is improved.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of preparation method of semiconductor device.
Background technology
Along with the continuous progress of semiconductor technology, especially when the process node of semiconductor reaches 32nm(nanometer) below time, in order to improve the carrier concentration in semiconductor device, stress technique is introduced into into.Such as, at CMOS(Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductors (CMOS)) in, in order to improve NMOS(N-Metal-Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS)) the conductive capability of conducting channel, form a kind of stacking fault (stacking fault) structure in the source/drain region of NMOS to increase the tensile stress (tensile stress) of conducting channel and then to strengthen electron mobility.
The structure of existing CMOS as shown in Figure 1.Existing CMOS comprise in substrate 1 formed NMOS and PMOS two parts, between NMOS and PMOS by the STI(shallow trench isolation be formed in substrate 1 from) 2.NMOS comprises the source/drain region 4 of the grid 3 that substrate 1 is formed and the substrate 1 being arranged in grid 3 both sides, substrate in grid 3 bottom and between source/drain region 4 forms the conducting channel of NMOS, and the both sides of grid 3 are also formed with side wall 5 to prevent the electric leakage between grid 3 and source/drain region 4.PMOS comprises the source/drain region 4 ' of the grid 3 ' that substrate 1 is formed and the substrate 1 being arranged in grid 3 ' both sides, be positioned in grid 3 ' bottom the conducting channel that substrate between source/drain region 4 ' forms PMOS, the both sides of grid 3 ' are also formed with side wall 5 ' to prevent the electric leakage between grid 3 ' and source/drain region 4 '.
In prior art, when the process node of semiconductor reaches below 32nm, (detailed process can see paper " NovelStress-memorization-Technology (SMT) for High Electron Mobility Enhancement of GateLast HKMG Devices (Samsung) " as follows to introduce a kind of method of stress to prepare stacking fault in NMOS in CMOS, IEDM, 2010,10.1).
As shown in Figure 2, degree of depth PAI(Pre-amorphization Implantation is carried out, pre-amorphous injection to the source/drain region 4 of NMOS), impurity is N-type impurity, forms non-crystalline areas 6, as shown in mesh-like area in Fig. 2 with substrate 1 residing for source/drain region 4.
Afterwards, as shown in Figure 3, at the surface deposition tensile stress film 7 of NMOS area.
Subsequently, as shown in Figure 4, SPER(Solid Phase Epitaxial Regrowth is carried out to non-crystalline areas 6, solid phase epitaxy).The non-crystalline areas 6 formed in the source/drain region 4 of NMOS owing to can be subject to the impact of top tensile stress film 7 exerted forces, and then makes the part silicon layer in non-crystalline areas 6 disappear in SPER process, and then forms stacking fault (stacking fault) 8.As shown by the arrows in Figure 4, this stacking fault 8 causes the substrate 1 of its both sides to produce power to this stacking fault 8, and then applies tensile stress to the conducting channel in the substrate 1 of grid 1 bottom.
Finally, as shown in Figure 5, tensile stress film 7 is removed, to complete the introduced stress of NMOS.After removing tensile stress film 7, stacking fault 8 can forever retain in the source/drain region 4 of grid 3 both sides, and then produces permanent tensile stress effect to the conducting channel between the source/drain region 4 in the substrate 1 of grid 1 bottom.Due to the effect of the tensile stress that stacking fault 8 causes, enhance the electron mobility (being greater than 10%) in NMOS conducting channel, and then enhance the performance of nmos device.
A kind of above-mentioned method preparing stacking fault is provide only to promote the performance of NMOS in prior art.Whether also there are other methods preparing stacking fault, need further research.
Summary of the invention
In view of this, the invention provides a kind of preparation method of new semiconductor device, to form stacking fault to promote the performance of semiconductor device in the source/drain region of semiconductor device.
The technical scheme of the application is achieved in that
A preparation method for semiconductor device, comprising:
Semiconductor substrate is provided, forms grid on the semiconductor substrate, and form source/drain region in the Semiconductor substrate of described grid both sides;
The Semiconductor substrate of source/drain region is etched, to form groove in the Semiconductor substrate of source/drain region;
Pre-amorphous injection is carried out to the bottom of described groove and sidewall;
Epitaxial growth is carried out, to form the non-crystalline areas of filling up groove to the bottom of the groove after pre-amorphous injection and sidewall;
At Semiconductor substrate, grid and non-crystalline areas surface deposition tensile stress film;
Solid phase epitaxy is carried out to non-crystalline areas, to form stacking fault.
Further, described Semiconductor substrate is P type substrate, and source/drain region is N-type source/drain region.
Further, after forming non-crystalline areas, also comprise before deposition tensile stress film:
N-type doping is carried out to non-crystalline areas.
Further, C, Si or Ge is adopted to carry out described pre-amorphous injection.
Further, when carrying out described pre-amorphous injection, Semiconductor substrate temperature is-150 ~ 0 DEG C.
Further, the process of described pre-amorphous injection adopts ion implantation means to realize, and the ion energy adopted is 500eV ~ 30KeV, and dopant dose is 5 × 10
13~ 20 × 10
13atom/cm
2.
Further, the angle between the normal of the upper surface of described ion implantation direction and Semiconductor substrate is 5 ~ 30 °.
Further, described N-type doping adopts P ion to adulterate.
Further, after the described stacking fault of formation, also comprise: remove described tensile stress film.
As can be seen from such scheme, the preparation method of semiconductor device of the present invention, form grid on a semiconductor substrate, and source/drain region is formed in the Semiconductor substrate of described grid both sides, etch to form groove to source/drain region again, afterwards pre-amorphous injection is carried out to the bottom of groove and sidewall, carry out epitaxial growth again to form the non-crystalline areas of filling up groove, compared with prior art, the present invention can form Stacking Fault Structure equally in the source/drain region of the final semiconductor device (as NMOS) formed, and then improves the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 is existing CMOS structure schematic diagram;
Fig. 2 carries out the structural representation after degree of depth PAI to the source/drain region of NMOS when being the stacking fault in existing preparation NMOS;
Structural representation when Fig. 3 is the stacking fault in existing preparation NMOS after NMOS surface deposition tensile stress film;
Fig. 4 carries out the structural representation after SPER to the non-crystalline areas of NMOS when being the stacking fault in existing preparation NMOS;
Fig. 5 removes the structural representation after tensile stress film when being the stacking fault in existing preparation NMOS;
Fig. 6 is preparation method's embodiment flow chart of semiconductor device of the present invention;
Fig. 7 be form stacking fault in the preparation method of semiconductor device of the present invention before constructive embodiment schematic diagram;
Fig. 8 forms embodiment schematic diagram after groove for the inventive method in structure shown in Fig. 7;
Fig. 9 is that the inventive method carries out the embodiment schematic diagram after pre-amorphous injection to the bottom of groove and sidewall;
Figure 10 is the embodiment schematic diagram after forming non-crystalline areas in the inventive method;
Figure 11 is the embodiment schematic diagram in the inventive method, non-crystalline areas being carried out to N-type doping;
Figure 12 is the embodiment schematic diagram in the inventive method after deposition tensile stress film;
Figure 13 is the embodiment schematic diagram after forming stacking fault in the inventive method;
Figure 14 is the embodiment schematic diagram after removing tensile stress film in the inventive method.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
As shown in Figure 6, the preparation method of semiconductor device of the present invention, comprising:
Semiconductor substrate is provided, forms grid on the semiconductor substrate, and form source/drain region in the Semiconductor substrate of described grid both sides;
The Semiconductor substrate of source/drain region is etched, to form groove in the Semiconductor substrate of source/drain region;
Pre-amorphous injection is carried out to the bottom of described groove and sidewall;
Epitaxial growth is carried out, to form the non-crystalline areas of filling up groove to the bottom of the groove after pre-amorphous injection and sidewall;
At Semiconductor substrate, grid and non-crystalline areas surface deposition tensile stress film;
Solid phase epitaxy is carried out to described non-crystalline areas, to form stacking fault.
The preparation method of semiconductor device of the present invention, mainly for the preparation of nmos device, therefore semiconductor device is NMOS, and Semiconductor substrate is P type substrate, and the source/drain region of semiconductor device is N-type source/drain region.Because stacking fault to be prepared is arranged in the source/drain region of semiconductor device, and method of the present invention first will filling up groove again after source/drain region forms groove after decrystallized doping and epitaxial growth, like this when preparing stacking fault, the doping content of filling up the N-type ion in the non-crystalline areas of groove is lower than the doping content of the N-type ion of original source/drain region.Therefore in method of the present invention, in order to make the N-type ion concentration of the source/drain region after forming stacking fault identical or close with the N-type ion concentration of original source/drain region, after formation non-crystalline areas, before deposition tensile stress film, also comprise the step of described non-crystalline areas being carried out to N-type doping further, so just, after can ensureing to form stacking fault, the N-type ion concentration of source/drain region can not change.
In addition, in NMOS device manufacturing process, after formation stacking fault, deposited tensile stress film is also needed to remove, so that carry out manufacturing process subsequently, such as ILD(Inter Layer Dielectric, interlayer dielectric layer) deposition and via(through hole) the technique such as preparation.
Below in conjunction with Fig. 7 to Figure 14, the preparation method of semiconductor device of the present invention is specifically introduced.
Step 1, as shown in Figure 7, provide Semiconductor substrate 1, described Semiconductor substrate 1 forms grid 3, and form source/drain region 4 in the Semiconductor substrate 1 of described grid 3 both sides.
After this step 1, just make a kind of semiconductor structure conventional in this area.As an embodiment, Semiconductor substrate 1 is P type substrate, and source/drain region 4 is N-type source/drain region, therefore, in this step 1, the semiconductor embodiments formed is NMOS, NMOS in this NMOS embodiment such as CMOS, for the ease of demonstration, all only illustrates this NMOS embodiment in Fig. 7 to Figure 14.
The material such as silicon substrate of Semiconductor substrate 1, described grid 3 such as polysilicon gate or metal gates, the N-type of source/drain region 4 is adulterated such as P(phosphorus) ion doping.
Continue with reference to shown in Fig. 7, the both sides of grid 3 also have side wall 5.Those skilled in the art should know, the effect of side wall 5 is when carrying out the preparation of source/drain region 4, the ion injected source/drain region 4 is avoided to enter grid 3 and make to produce between grid 3 and source/drain region 4 to leak electricity, those skilled in the art also should know simultaneously, side wall 5 can be sandwich construction, be such as offset side wall (offset spacer) near grid 3 place, the outside of offset side wall is master wall (main spacer).
Step 2, as shown in Figure 8, the Semiconductor substrate 1 of source/drain region 4 to be etched, to form groove 91 in the Semiconductor substrate 1 of source/drain region 4.
In this step 2, form groove 91 and specifically can adopt with the following method:
Comprising the total surface-coated photoresist of Semiconductor substrate 1 and grid 3, the light shield for the formation of groove 91 is adopted to expose photoresist, photoresist is developed, so that the photoresist on the surface of position of groove 91 will be formed in the Semiconductor substrate 1 removing position, source/drain region 4, be that mask etches (such as dry method or wet etching means) to form groove 91 to Semiconductor substrate 1 again with photoresist, finally adopt the means such as such as ashing to remove remaining photoresist.
Step 3, as shown in Figure 9, carries out pre-amorphous injection to the bottom of groove 91 and sidewall.
In this step 3, adopt C(carbon), Si(silicon) or Ge(germanium) pre-amorphous injection (PAI) is carried out to the bottom of groove 91 and sidewall, after pre-amorphous injection, form more shallow non-crystalline areas 61 at the sidewall of the bottom of groove 91 and groove 91.In order to all more shallow non-crystalline areas 61 can be formed at the sidewall of the bottom of groove 91 and groove 91, adopt oblique pre-amorphous injection means to the bottom of 91 of groove and wall doping C, Si or Ge of groove 91 in this step 3, as shown by the arrows in Figure 9, C, Si, or the object that Ge injects is only that surface is decrystallized.As a specific embodiment, pre-amorphous injection process in this step 3 adopts low-temperature-doped (cold implant) means, during pre-amorphous injection, the temperature of Semiconductor substrate 1 is-150 ~ 0 DEG C, pre-amorphous injection process adopts ion implantation means to realize, ion is C ion, Si ion or Ge ion, and the ion energy adopted is 500eV(electronvolt) ~ 30KeV(kiloelectron-volt), dopant dose is 5 × 10
13~ 20 × 10
13atom/cm
2(atom/square centimeter), the angle between the normal of ion implantation direction during doping and the upper surface of Semiconductor substrate 1 is 5 ~ 30 ° (degree).
Step 4, as shown in Figure 10, carries out epitaxial growth, to form the non-crystalline areas 61 of filling up described groove 91 to the bottom of the groove 91 after pre-amorphous injection and sidewall.
In this step 4, be to pre-amorphous injection after the bottom of groove 91 and groove 91 sidewall after pre-amorphous injection carry out epitaxially grown, as a specific embodiment, epitaxial growth is selective epitaxy growth (SelectiveEpitaxy), the material of growth is SiC(carborundum), be the SiC of e-SiC(Selective SiC epitaxy, selective epitaxy growth in the non-crystalline areas 61 that epitaxial growth is formed).
Step 5, as shown in figure 11, N-type doping is carried out to non-crystalline areas 61.
Generate because source/drain region 4 is through N-type doping, again because in abovementioned steps 2 material of place, source/drain region 4 Semiconductor substrate 1 carried out removing to form groove 91, thus with in rearward recess 91 the N-type ion concentration in epitaxially grown non-crystalline areas 61 different from the N-type ion concentration of the source/drain region 4 before formation groove 91.If do not carry out N-type doping to this non-crystalline areas 61, the electric conductivity of prepared semiconductor device will be affected.So need after completing steps 4 fills up the non-crystalline areas 61 of groove 91 with formation, N-type doping is carried out to non-crystalline areas 61, substantially identical with the N-type ion concentration of the source/drain region 4 formed before groove 91 to ensure the N-type ion concentration in the non-crystalline areas 61 after adulterating.In semiconductor fabrication, N-type doping generally can adopt P(phosphorus) method of ion doping forms source/drain region 4, so as a specific embodiment, the N-type doping in this step 5 also adopts P ion to adulterate.In this step 5, N-type doping can be ion implantation, also can be extension situ grow doping (In-situ doping).The SiC of e-SiC:P(epitaxial growth situ doping P is formed in non-crystalline areas 61) after carrying out growth in situ doping.
Step 6, as shown in figure 12, at the surface deposition tensile stress film 71 of Semiconductor substrate 1, grid 3 and non-crystalline areas 61.
In this step 6, be the total surface deposition tensile stress film 71 formed after step 5, i.e. Semiconductor substrate 1 surface after step 5, grid 3 surface and non-crystalline areas 61 surface deposition tensile stress film 71.The tensile stress film 71 deposited such as SiN(silicon nitride) film, the method preparing SiN film can be adopted in prior art to deposit.
Step 7, as shown in figure 13, solid phase epitaxy is carried out to non-crystalline areas 61, to form stacking fault 81.
In this step 7, be form stacking fault 81 in the Semiconductor substrate 1 of source/drain region 4.Solid phase epitaxy process in this step 7 specifically can adopt method for annealing to realize, annealing temperature such as 500 ~ 700 DEG C, annealing time 50 ~ 90min(minute), during annealing, gas can adopt N2(nitrogen).Solid phase epitaxy carries out for non-crystalline areas 61, after completing solid phase epitaxy, non-crystalline areas 61 position forms stacking fault 81, and in the annealing process of solid phase epitaxy, non-crystalline areas 61 also there occurs structural change, and non-crystalline areas 61 is disappeared.Simultaneously the formation of stacking fault 81 and the disappearance of non-crystalline areas 61 carry out in the method for annealing of solid phase epitaxy.
Step 8, as shown in figure 14, removes tensile stress film 71.
This step 8 can adopt dry method or wet etching means to remove described tensile stress film.Dry etching is reactive ion etching means such as.
The preparation method of semiconductor device provided by the present invention, form grid on a semiconductor substrate, and source/drain region is formed in the Semiconductor substrate of described grid both sides, etch to form groove to source/drain region again, afterwards pre-amorphous injection is carried out to the bottom of groove and sidewall, carry out epitaxial growth again to form the non-crystalline areas of filling up groove, compared with prior art, the present invention can form Stacking Fault Structure equally in the source/drain region of the final semiconductor device (as NMOS) formed, and then improves the performance of semiconductor device.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided, forms grid on the semiconductor substrate, and form source/drain region in the Semiconductor substrate of described grid both sides;
The Semiconductor substrate of source/drain region is etched, to form groove in the Semiconductor substrate of source/drain region;
Pre-amorphous injection is carried out to the bottom of described groove and sidewall;
Epitaxial growth is carried out, to form the non-crystalline areas of filling up groove to the bottom of the groove after pre-amorphous injection and sidewall;
At Semiconductor substrate, grid and non-crystalline areas surface deposition tensile stress film;
Solid phase epitaxy is carried out to non-crystalline areas, to form stacking fault.
2. the preparation method of semiconductor device according to claim 1, is characterized in that:
Described Semiconductor substrate is P type substrate, and source/drain region is N-type source/drain region.
3. the preparation method of semiconductor device according to claim 2, is characterized in that, after forming non-crystalline areas, also comprises before deposition tensile stress film:
N-type doping is carried out to non-crystalline areas.
4. the preparation method of the semiconductor device according to any one of claims 1 to 3, is characterized in that:
C, Si or Ge is adopted to carry out described pre-amorphous injection.
5. the preparation method of semiconductor device according to claim 4, is characterized in that:
When carrying out described pre-amorphous injection, Semiconductor substrate temperature is-150 ~ 0 DEG C.
6. the preparation method of semiconductor device according to claim 4, is characterized in that:
The process of described pre-amorphous injection adopts ion implantation means to realize, and the ion energy adopted is 500eV ~ 30KeV, and dopant dose is 5 × 10
13~ 20 × 10
13atom/cm
2.
7. the preparation method of semiconductor device according to claim 6, is characterized in that:
Angle between the normal of the upper surface of described ion implantation direction and Semiconductor substrate is 5 ~ 30 °.
8. the preparation method of semiconductor device according to claim 3, is characterized in that:
Described N-type doping adopts P ion to adulterate.
9. the preparation method of semiconductor device according to claim 1, is characterized in that, after the described stacking fault of formation, also comprises:
Remove described tensile stress film.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113497118A (en) * | 2020-03-19 | 2021-10-12 | 三菱电机株式会社 | Silicon carbide semiconductor device and method for manufacturing same |
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| CN102388442A (en) * | 2009-01-30 | 2012-03-21 | 先进微装置公司 | In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile |
| CN103199064A (en) * | 2012-01-05 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Method of forming a semiconductor device |
| CN103295963A (en) * | 2012-03-02 | 2013-09-11 | 台湾积体电路制造股份有限公司 | Semiconductor device having a strained region |
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| CN113497118A (en) * | 2020-03-19 | 2021-10-12 | 三菱电机株式会社 | Silicon carbide semiconductor device and method for manufacturing same |
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