CN104750639A - Enhanced DMA controller based on AMBA bus - Google Patents
Enhanced DMA controller based on AMBA bus Download PDFInfo
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- CN104750639A CN104750639A CN201510167612.4A CN201510167612A CN104750639A CN 104750639 A CN104750639 A CN 104750639A CN 201510167612 A CN201510167612 A CN 201510167612A CN 104750639 A CN104750639 A CN 104750639A
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Abstract
The invention discloses an enhanced DMA controller based on an AMBA bus, and belongs to the technical field of DMA. The DMA controller comprises a slave machine interface module mounted on an APB bus, a parameter RAM and a control module thereof, a transmission request link module, a transmission control module, and a master machine interface module mounted on an AHB bus, accordingly increasing the data transfer efficiency among memories, reducing the load of the CPU, and improving the system performance. The link trigger among channels allows the DMA controller to transfer data of complex formats, thereby increasing the transmission efficiency.
Description
Technical field
The invention discloses the enhancement mode dma controller based on AMBA bus, belong to DMA(Direct Memory Access, direct memory access) technical field.
Background technology
Dma controller is current main flow SOC (system on a chip) (SOC, System on Chip) equipment required in system and embedded system, its function replaces CPU to complete a large amount of, complicated data handling process, and without the need to the intervention of CPU, to improve system works efficiency.Along with the development of SOC system, in prior art, DMA controller is often directly hung on the system bus, and its DASD and I/O equipment are completed by bus, generally possess hyperchannel work, can carry the function of the data of certain format.Along with the continuous growth of data carrying demand, the dma controller of prior art is difficult to realize the efficient carrying of mass data between internal memory, therefore needs a kind of dma controller badly, improves the handling efficiency of mass data between internal memory.
Summary of the invention
Technical matters to be solved by this invention is the deficiency for above-mentioned background technology, provide the enhancement mode dma controller based on AMBA bus, achieve the data-moving of dma controller in AMBA bus, solve the technical matters that the data handling efficiency of existing dma controller is low.
The present invention adopts following technical scheme for achieving the above object:
Based on the enhancement mode dma controller of AMBA bus, comprising: carry in APB bus from machine interface module, parameter RAM and control module thereof, transmission request chain module, transmission control module, the host interface module of carry on ahb bus, wherein:
Parameter RAM and control module thereof: input termination carry in APB bus from machine interface module, export the input end of terminated transmis-sion request chain module, store the described channel transfer parameter obtained from machine interface module, the transmission request generated by channel transfer parameter is sent to transmission request chain module, described channel transfer parameter comprises: channel priorities, transmitted data bits are wide, source address, destination address, transmission counting and channel link information;
Transmission request chain module: the input end exporting termination transmission control module, exports transmission request queue according to priority arrangement to transmission control module;
Transmission control module: first exports the host interface module of termination carry on ahb bus, another input end of second output termination parameter RAM and control module thereof, process transmission request one by one according to priority and obtain read/write requests, the data-moving between source port and destination interface is realized, by the transmission counting of renewal, channel link information feed back to parameter RAM and control module thereof by described host interface module.
As the further prioritization scheme of the described enhancement mode dma controller based on AMBA bus, control module in parameter RAM and control module thereof, comprise: with transmission control module second output terminal, the state machine that is connected from machine interface module, the request be connected with state machine output terminal sends module, described state machine updating maintenance channel transfer parameter also realizes peripheral hardware to parameter RAM read-write operation, and described request sends the channel transfer parameter that module upgrades by state machine and obtains transmission request.
Further, the described enhancement mode dma controller based on AMBA bus, described transmission request chain module adopts arbitration mechanism to carry out prioritization to transmission request.
Further, the described enhancement mode dma controller based on AMBA bus also comprises the interrupt control logic module be connected with the 3rd output terminal of transmission control module, by transmission control module export be transmitted signal or error of transmission signal obtains look-at-me, the CPU of look-at-me to SOC system controls.
Further, described based in the enhancement mode dma controller of AMBA bus, transmission control module comprises: queuing register and order sending module, queuing register input terminated transmis-sion request chain module output terminal, queuing register first exports termination command sending module input end, queuing register second exports another input end of termination parameter RAM and control module thereof, and queuing register the 3rd output terminal exports and is transmitted signal or error of transmission signal to interrupt control logic module
Described queuing register obtains read/write requests according to FIFO principle process transmission request, the transformation parameter of queuing register real-time update treatment channel, order sending module carries out read/write operation according to read/write requests to the host interface module of carry on ahb bus.
The present invention adopts technique scheme, has following beneficial effect:
(1) there are 16 passages, 16 kinds of transmission requests can be accepted, hyperchannel switches, each passage supports a software asks and 31 hardware requests, the priority of passage is able to programme, the priority of passage only need being set in channel transfer parameter, according to priority, transmission request insertion can being transmitted request queue accordingly when processing transmission request.
(2) transmission of several data form can be realized, support one dimension transmission and two dimension transmission, one dimension transmission can be divided into units synchronization and frame synchronization again, two dimension transmission be divided into units synchronization and block synchronous.
(3) support that link triggers, can forward when a channel transfer completes the transmission that another passage that chain has connected continues this channel data to, there is higher transfer efficiency
(4) transmission request chain has three to transmit request queue, and transmission request is inserted transmission request queue by the priority according to channel parameters, and transmission control module goes the transmission request process of the queue front that priority is higher at every turn.
Accompanying drawing explanation
Fig. 1 is enhancement mode dma controller structural representation of the present invention;
Fig. 2 is event argument form;
Fig. 3 is the state machine of RAM director mode one;
Fig. 4 is the state machine of RAM director mode two;
Fig. 5 is that Q writes state of a control machine;
Fig. 6 is that Q reads state of a control machine;
Fig. 7 is transmission control module structural drawing.
Embodiment
Be described in detail below in conjunction with the technical scheme of accompanying drawing to invention.
As shown in Figure 1, the dma controller of the present embodiment, comprise AHB host interface module, parameter RAM and controller module thereof, transmission request chain module, transmission control module, interrupt control logic module, APB is from machine interface module.Division and the connection of this example Neutron module there is no specific specifications, and therefore, this dividing mode and connected mode are improved based on the characteristic optimizing of this example.
Below in conjunction with Fig. 1, introduced the concrete function of the modules of the enhancement mode dma controller of this example by specific works flow process.
1), after dma controller resets, can configure corresponding channel parameters by APB from machine interface polls, now, dma controller is as slave.DMA event argument as shown in Figure 2, mainly comprises option parameter, SRC/DST address, element count, frame/array count, unit index and frame/array index, element count heavy duty, chained address; Wherein,
Option parameter, comprises that channel priorities, transmitted data bits are wide, source/order address change mode, whether supports link, interrupted the information such as code;
SRC/DST address, 32 potential sources/destination address section determines the start byte address of source and destination;
Element count, element count be one 16 without value of symbol, this value is the unit number in the number of unit in a frame or an array;
Frame/array count, frame/array count is similarly one 16 without value of symbol, and it determines the number of array in the number of frame in a 1D block or 2D block;
Unit index and frame/array index, 16 of unit index and frame/array index have value of symbol to be used for changing address;
Element count heavy duty, after in a frame, last unit is transmitted, 16 are used to overriding unit counting section without symbolic unit counting heavy duty value;
Chained address, chained address defines DMA and is loaded into or heavily loaded next transformation parameter entry address of low 16 in parameter RAM.
2) channel parameters of this example dma controller stores based on RAM, and the channel parameters come from machine interface by APB is stored into RAM by parameter RAM controller.Parameter RAM and controller module are the fundamental mark that this DMA is different from common DMA, and it controls and safeguards the renewal of each channel transfer parameter, generate the transmission request of passage.Parameter RAM is for depositing the transformation parameter of user program configuration, parameter RAM size is 2KB, can by the dual-port of 8 8bit × 256 (being divided into port A and B) SRAM form many bodies intersect storer realize, wherein, port A realizes RAM controller to the renewal of parameter RAM and maintenance, and port B realizes the read-write of peripheral bus to parameter RAM.The major function of RAM controller receives from the read-write of peripheral bus to parameter RAM, and trigger according to event, the transformation parameter of respective channel is taken out from parameter RAM, generate channel transfer request and submit to transmission request chain, after request is submitted to, then the contents such as the data counts information of transformation parameter in parameter RAM, source address and destination address are upgraded.RAM controller can be divided into RAM state of a control machine and channel transfer request to send module two parts.Wherein, channel transfer request sends the transmission request that synchronous event starts by module primary responsibility and delivers to transmission request chain, and RAM state of a control machine more complicated, two state machines can be divided into again, respectively two kinds of mode of operations of corresponding RAM controller:
Pattern one: RAM controller passes through the A port realization of dual-port SRAM to the renewal of parameter RAM and maintenance, and its state machine as shown in Figure 3
Pattern two: RAM controller passes through the B port controlling peripheral bus of dual-port SRAM to the read-write operation of parameter RAM, and its state machine as shown in Figure 4
3) transmission request chain module, is responsible for receiving all channel transfer request, and according to priority delivers to transmission request queue, comprises transmission request arbitration modules in transmission request chain, ensures that each transmission request enters queue according to the order of sequence.Transmission request arbitration is responsible for arbitrating all transmission requests, ensures each transmission request is according to priority orderly to enter transmission request queue.Transmission request queue has three: Q0, Q1 and Q2, and their 26S Proteasome Structure and Function is consistent, and only priority is different, receives the transmission request of three class different priorities respectively, and the process of transmission control module is waited in transmission request in queue according to the principle of first in first out.Transmission request queue is made up of memory bank and memory controller.Memory bank is realized by many bodies intersection SRAM of 48 × 192bit, and can preserve 48 transmission requests, corresponding address is numbered 0 ~ 63, and wherein address number 0 ~ 15 is Q0 queue, and 16 ~ 31 is Q1 queue, and 32 ~ 47 is Q2 queue.It is 16 that each queue is maximum length, and actual length available can be set in the annular first in first out structure of any value between 0 to 16.Storage controller controls read-write operation to queue memory bank, is responsible for the transmission request of reception according to priority to write toward each queue, and according to the read command of transmission control module, reads transmission request deliver to transmission control module and carry out data transmission from the head position of queue.Therefore, memory controller can be divided into six control modules: Q0 writing controller, Q0 Read Controller, Q1 writing controller, Q1 Read Controller, Q2 writing controller, Q2 Read Controller.Fig. 5 is the state machine of writing controller, and Fig. 6 is the state machine of Read Controller
4) transmission control module is the core of DMA controller, its structural drawing as shown in Figure 7, queuing register group processes the transmission request obtaining resource, extract source address, destination address, transmission counting and other control information transmissions, generate read and write transmission request, after arbitration, order sending module is submitted in the transmission request that reads or writes satisfied condition and carries out data transmission, in transmitting procedure, the renewal of queuing register group controls transfer parameter.After order sending module receives read request, when source port is not in a hurry (Busy signal is that low level represents that corresponding ports is idle), read command is sent out to source port, when source port is by (Ready signal is that high level represents that data encasement is complete) during DSR, cache module receives and preserves the data read, when data all receive and destination interface not busy, write order and data are issued destination interface by order sending module, realize the data transmission from source to object.
5) data transmission is undertaken by ahb bus, i.e. the function of AHB host interface.
6) when the transmission request in queue processes, interrupt control logic will produce interruption, and notice CPU is transmitted.
Visible, enhancement mode dma controller provided by the invention, can improve the data handling efficiency between internal memory, thus offloading the CPU, improve system performance; Interchannel provided by the invention can also link triggering, and this makes multi-channel DMA controller, can carry complex format data; Channel priorities is able to programme, and the automatism of controller is higher, and transfer efficiency is higher.
The above is only embodiments of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (5)
1. based on the enhancement mode dma controller of AMBA bus, it is characterized in that, comprise: carry in APB bus from machine interface module, parameter RAM and control module thereof, transmission request chain module, transmission control module, the host interface module of carry on ahb bus, wherein:
Parameter RAM and control module thereof: input termination carry in APB bus from machine interface module, export the input end of terminated transmis-sion request chain module, store the described channel transfer parameter obtained from machine interface module, the transmission request generated by channel transfer parameter is sent to transmission request chain module, described channel transfer parameter comprises: channel priorities, transmitted data bits are wide, source address, destination address, transmission counting and channel link information;
Transmission request chain module: the input end exporting termination transmission control module, exports transmission request queue according to priority arrangement to transmission control module;
Transmission control module: first exports the host interface module of termination carry on ahb bus, another input end of second output termination parameter RAM and control module thereof, process transmission request one by one according to priority and obtain read/write requests, the data-moving between source port and destination interface is realized, by the transmission counting of renewal, channel link information feed back to parameter RAM and control module thereof by described host interface module.
2. the enhancement mode dma controller based on AMBA bus according to claim 1, it is characterized in that, control module in described parameter RAM and control module thereof, comprise: with transmission control module second output terminal, the state machine that is connected from machine interface module, the request be connected with state machine output terminal sends module, described state machine updating maintenance channel transfer parameter also realizes peripheral hardware to parameter RAM read-write operation, and described request sends the channel transfer parameter that module upgrades by state machine and obtains transmission request.
3. the enhancement mode dma controller based on AMBA bus according to claim 2, is characterized in that, described transmission request chain module adopts arbitration mechanism to carry out prioritization to transmission request.
4. the enhancement mode dma controller based on AMBA bus according to claims 1 to 3, it is characterized in that, enhancement mode dma controller also comprises the interrupt control logic module be connected with the 3rd output terminal of transmission control module, by transmission control module export be transmitted signal or error of transmission signal obtains look-at-me.
5. the enhancement mode dma controller based on AMBA bus according to claim 4, it is characterized in that, described transmission control module comprises: queuing register and order sending module, queuing register input terminated transmis-sion request chain module output terminal, queuing register first exports termination command sending module input end, queuing register second exports another input end of termination parameter RAM and control module thereof, queuing register the 3rd output terminal exports and is transmitted signal or error of transmission signal to interrupt control logic module
Described queuing register obtains read/write requests according to FIFO principle process transmission request, the transformation parameter of queuing register real-time update treatment channel, order sending module carries out read/write operation according to read/write requests to the host interface module of carry on ahb bus.
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| CN106789078A (en) * | 2016-12-29 | 2017-05-31 | 记忆科技(深圳)有限公司 | A kind of digital signature identification system based on ahb bus |
| CN113434441A (en) * | 2021-06-24 | 2021-09-24 | 深圳市航顺芯片技术研发有限公司 | DMA transmission method, device, controller and readable storage medium |
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