CN104750155A

CN104750155A - LDO (low dropout regulator) circuit with external capacitance detecting function

Info

Publication number: CN104750155A
Application number: CN201510173937.3A
Authority: CN
Inventors: 梁青武
Original assignee: SHANGHAI LINGWOBO INTELLIGENT TECHNOLOGY Co Ltd
Current assignee: SHANGHAI LINGWOBO INTELLIGENT TECHNOLOGY Co Ltd
Priority date: 2015-04-13
Filing date: 2015-04-13
Publication date: 2015-07-01
Anticipated expiration: 2035-04-13
Also published as: CN104750155B

Abstract

The invention relates to an LDO (low dropout regulator) circuit with an external capacitance detecting function. The LDO circuit comprises a built-in voltage reference source, an amplifier, a linear switch M1, partial pressure feedback loops R1 and R2, a core circuit and a stray capacitance C1, and a preset plug-in capacitor Cext; the LDO circuit further comprises a capacitance detecting switch S1, a level detection circuit, a clock and time sequence circuit; capacitance detecting switches are linked to both ends of R1 in parallel and connected with the clock and time sequence circuit, one end of the level detection circuit is connected to the output end of the amplifier, and the other end is connected with the clock and time sequence circuit. Compared with the prior art, the LDO circuit is convenient to operate, high in reliability, low in cost, and the like.

Description

A kind of LDO circuit with external capacitor measuring ability

Technical field

The present invention relates to a kind of LDO circuit, especially relate to a kind of LDO circuit with external capacitor measuring ability.

Background technology

LDO, for generating a more stable output voltage, generally includes a voltage-reference, an amplifier, a linear switch (triode or metal-oxide-semiconductor) and a dividing potential drop feedback control loop.By feedback control loop, output voltage stabilization on a default magnitude of voltage.Usual meeting is a plug-in electric capacity on output voltage node, as the dominant pole of whole feedback control loop.

Along with CMOS integrated level is more and more higher, in chip, built-in LDO also gets more and more with the way obtaining stable core voltage, and if Fig. 1, Vhigh are LDO input voltage, Vlow is LDO output voltage, is also the supply voltage of kernel circuitry.C1 is chip internal parasitic load capacitance, and capacitance is generally 10pF ~ 10nF magnitude; Cext is chip plug-in capacitor, and as the dominant pole of whole feedback control loop, its capacitance is generally arranged on 0.1uF ~ 100uF magnitude.

With regard to chip work itself, such configuration is very ripe, without any problem.But on end product, there will be such situation: if board-level circuit Vlow node capacitor Cext rosin joint, or to weld capacitor's capacity not enough or damage, then LDO can be caused to work abnormal, the even output voltage vibration of AC response difference.Institute thinks and guarantees product quality, needs to increase capacitance test circuit on board-level circuit, adds production complexity and the cost of end product.

Summary of the invention

Object of the present invention is exactly the LDO circuit providing a kind of easy to operate, reliability is high, cost is low band external capacitor measuring ability in order to overcome defect that above-mentioned prior art exists.

Object of the present invention can be achieved through the following technical solutions:

A kind of LDO circuit with external capacitor measuring ability, comprise built-in voltage reference source, amplifier, linear switch M1, dividing potential drop feedback control loop R1 and R2, kernel circuitry and stray capacitance C1, and default plug-in capacitor Cext, described built-in voltage reference source is connected to amplifier negative terminal, described amplifier anode is connected between R1 and R2, described amplifier out connects the grid of linear switch M1, the source electrode of described linear switch M1 and drain electrode meet input node Vhigh and the output node Vlow of LDO respectively, described kernel circuitry and stray capacitance C1 and default plug-in capacitor Cext are connected on Vlow, it is characterized in that, described LDO circuit also comprises capacitance detecting switch S 1, level sensitive circuit, and clock and sequential circuit, described capacitance detecting switch in parallel is at R1 two ends and be connected with clock and sequential circuit, described level sensitive circuit one end is connected on amplifier out, the other end is connected with clock and sequential circuit.

Described linear switch M1 is PMOS.

Described capacitance detecting switch S 1 is CMOS gate-controlled switch, and its control signal is provided by clock and sequential circuit.

Described level sensitive circuit concrete function is as follows:

Described clock and sequential control circui capacitance detecting switch S 1 close, then Vlow voltage is directly inputted into amplifier anode, amplifier exports high level makes M1 end, and Vlow is discharged by R2 until equal built-in voltage reference source voltage, and amplifier output voltage will slowly fall back former operating voltage; In amplifier rejuvenation, described level sensitive circuit setting between in detecting amplifier whether maintain high level always, if yes, then judge to preset plug-in capacitor Cext capacitance normal, otherwise the default plug-in capacitor Cext of judgement does not connect or capacitance is abnormal.

Described clock and sequential circuit, provide a clock for sequential control and level sensitive circuit used establish interval time, and control capacitance detector switch S1 closed and opening.

Compared with prior art, the present invention has the following advantages:

1, easy to operate, without the need to increasing capacitance test circuit on board-level circuit; By running external capacitor trace routine on end product, can judge that whether external capacitor is qualified.

2, reliability is high, and when can consider that detection finds that external capacitor is defective, chip automatically switches to internal compensation pattern to ensure LDO output voltage nonoscillatory, increases the reliability of end product further.

3, chip circuit is simple, and cost is low, controls also simple.

Accompanying drawing explanation

Fig. 1 is the theory diagram of existing LDO circuit;

Fig. 2 is the LDO schematic block circuit diagram of band external capacitor measuring ability set forth in the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.

Embodiment

As Fig. 2, with a LDO circuit for external capacitor measuring ability, comprise built-in voltage reference source, amplifier, linear switch M1 (PMOS), dividing potential drop feedback control loop R1 and R2, kernel circuitry and stray capacitance C1, preset plug-in capacitor Cext, capacitance detecting switch S 1, level sensitive circuit, clock and sequential circuit.Described built-in voltage reference source is connected to amplifier negative terminal, amplifier anode connects R1R2 feedback node, amplifier out connects the grid of M1, the source electrode of M1 and drain electrode meet input and output node Vhigh and Vlow of LDO respectively, and kernel circuitry and stray capacitance C1 and default plug-in capacitor Cext are connected on Vlow; Capacitance detecting switch in parallel is at R1 two ends, and amplifier exports and is connected to level sensitive circuit, and level sensitive circuit exported to by clock and sequential circuit simultaneously.

Described built-in voltage reference source, amplifier, linear switch M1 (PMOS), dividing potential drop feedback control loop R1 and R2, kernel circuitry and stray capacitance C1, default plug-in capacitor Cext, and industry use is as broad as long.This example assumes: Vhigh=5V, Vlow=1.8V, built-in voltage reference source=1.2V, R1=60K Ω, R2=120K Ω, C1=1nF, Cext preset value=1uF.

Described capacitance detecting switch S 1 is CMOS gate-controlled switch, and control signal is provided by clock and sequential circuit.

Described clock and sequential circuit, be responsible for providing the clock of a degree of precision for sequential control and level sensitive circuit computing time, and gauge tap S1 closed and opening.This example assumes: clock frequency is 100KHz ± 50%, the fixed count being supplied to level sensitive circuit is 128 cycles, and namely Fixed Time Interval is 1.28ms ± 50%.

When after triggering capacitance detecting function, sequential circuit gauge tap S1 closes, then Vlow voltage is directly inputted into amplifier anode, and amplifier exports high level makes M1 end, Vlow is discharged by R2 until equal built-in voltage reference source voltage, and amplifier output voltage will slowly fall back former operating voltage.If Cext capacitance is normal, be then about R2*Cext=120ms release time; If Cext does not connect, be then about R2*C1=120us=0.1ms release time.In this rejuvenation, level sensitive circuit is at a fixed time after interval 1.28ms ± 50% time, and whether detecting amplifier output terminal still maintains high level.If be still high level, then Cext capacitance is normal; If lower than detection threshold, then Cext does not connect or capacitance exception.

Claims

1. the LDO circuit with external capacitor measuring ability, comprise built-in voltage reference source, amplifier, linear switch M1, dividing potential drop feedback control loop R1 and R2, kernel circuitry and stray capacitance C1, and default plug-in capacitor Cext, described built-in voltage reference source is connected to amplifier negative terminal, described amplifier anode is connected between R1 and R2, described amplifier out connects the grid of linear switch M1, the source electrode of described linear switch M1 and drain electrode meet input node Vhigh and the output node Vlow of LDO respectively, described kernel circuitry and stray capacitance C1 and default plug-in capacitor Cext are connected on Vlow, it is characterized in that, described LDO circuit also comprises capacitance detecting switch S 1, level sensitive circuit, and clock and sequential circuit, described capacitance detecting switch in parallel is at R1 two ends and be connected with clock and sequential circuit, described level sensitive circuit one end is connected on amplifier out, the other end is connected with clock and sequential circuit.

2. a kind of LDO circuit with external capacitor measuring ability according to claim 1, it is characterized in that, described linear switch M1 is PMOS.

3. a kind of LDO circuit with external capacitor measuring ability according to claim 1, is characterized in that, described capacitance detecting switch S 1 is CMOS gate-controlled switch, and its control signal is provided by clock and sequential circuit.

4. a kind of LDO circuit with external capacitor measuring ability according to claim 1, it is characterized in that, described level sensitive circuit concrete function is as follows:

5. a kind of LDO circuit with external capacitor measuring ability according to claim 1, it is characterized in that, described clock and sequential circuit, provide a clock for sequential control and level sensitive circuit used establish interval time, and control capacitance detector switch S1 closed and opening.