CN104749848A - Array substrate, display device and manufacturing method - Google Patents
Array substrate, display device and manufacturing method Download PDFInfo
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- CN104749848A CN104749848A CN201510190864.9A CN201510190864A CN104749848A CN 104749848 A CN104749848 A CN 104749848A CN 201510190864 A CN201510190864 A CN 201510190864A CN 104749848 A CN104749848 A CN 104749848A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention provides an array substrate, a display device and a manufacturing method. The array substrate comprises an underlayment substrate; a transparent conductive graphic, a grid electrode, an active layer, and a source electrode connected with the active layer are formed on the underlayment substrate, wherein an insulating layer with a through hole is arranged between the transparent conductive graphic and the source electrode; the transparent conductive graphic comprises a first part which is connected with the active layer through the through layer; the first part is used as a grain electrode and forms a thin film transistor structure with the grid electrode, the active layer and the source electrode. Compared with the prior art, the array substrate is high in opening rate and supports fine display effect.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly a kind of array base palte, display device and method for making.
Background technology
In existing array base palte, pixel electrode is all be connected with the drain electrode of thin film transistor (TFT).For the bottom gate type array base palte shown in Fig. 1, the thin film transistor (TFT) on underlay substrate 1 comprises gate electrode 2, source electrode 5, drain electrode 6 and connects the active layer 4 of source electrode 5 and drain electrode 6.The pixel electrode 8 of array base palte is connected with drain electrode 6 by the via hole of passivation layer 7.
As seen in Figure 1, thin-film transistor structure of the prior art is tiled by source electrode 5, active layer 4 and drain electrode 6 and forms, therefore in occupation of very large area (a region namely in Fig. 1).On array base palte, the aperture opening ratio of array base palte mainly determined by the size of thin film transistor (TFT), and therefore existing thin-film transistor structure have impact on the aperture opening ratio of array base palte.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte, display device and method for making, effectively can improve the aperture opening ratio of array base palte.
For solving the problems of the technologies described above, embodiments of the invention provide a kind of array base palte, comprise underlay substrate, the source electrode described underlay substrate being formed with transparent conductive pattern, gate electrode, active layer and being connected with described active layer;
The insulation course comprising via hole is provided with between described transparent conductive pattern and described source electrode;
Described transparent conductive pattern comprises the Part I be connected with described active layer by described via hole, and described Part I, as drain electrode, with described gate electrode, active layer and source electrode, forms thin-film transistor structure.
Wherein, described transparent conductive pattern also comprises the Part II as pixel electrode.
Wherein, described insulation course is passivation layer, and described passivation layer is positioned at above described source electrode;
Described underlay substrate is also formed with gate insulation layer, and described gate insulation layer is arranged between described gate electrode and described source electrode.
Wherein, described insulation course is gate insulation layer, and described gate insulation layer is arranged between described gate electrode and described source electrode;
Described transparent conductive pattern and described gate electrode are arranged with layer.
Wherein, described active layer is oxide semiconductor layer.
In addition, another embodiment of the present invention also provides a kind of display device, comprises above-mentioned array base palte.
In addition, another embodiment of the present invention also provides a kind of method for making of array base palte, at least be included in the step of the insulation course of source electrode underlay substrate being formed with transparency conducting layer and described thin film transistor (TFT) described in transparent conductive pattern, thin film transistor (TFT) and interval, described insulation course has via hole;
Wherein, in the step forming thin film transistor (TFT), gate electrode, source electrode and active layer is only formed;
Form the described transparent conductive pattern including the Part I be connected with described active layer by described via hole, described Part I, as drain electrode, with described gate electrode, active layer and source electrode, forms thin-film transistor structure.
Wherein, described transparent conductive pattern also comprises the Part II as pixel electrode.
Wherein, described insulation course is passivation layer, and described method for making specifically comprises:
Underlay substrate is formed gate electrode and sweep trace;
On the underlay substrate being formed with gate electrode and sweep trace, form gate insulation layer;
On the underlay substrate being formed with gate insulation layer, the active layer forming source electrode, data line and be connected with this source electrode;
On the underlay substrate being formed with source electrode, data line and active layer, form the passivation layer with via hole;
On the underlay substrate being formed with passivation layer, form transparent conductive pattern, the Part I of described transparent conductive pattern, by the via hole of described passivation layer, is connected with described active layer.
Wherein, described insulation course is gate insulation layer, and described method for making specifically comprises:
Underlay substrate is formed gate electrode, sweep trace and transparent conductive pattern;
On the underlay substrate being formed with gate electrode, sweep trace and transparent conductive pattern, form the gate insulation layer with via hole;
On the underlay substrate being formed with gate insulation layer, the active layer forming source electrode, data line and be connected with this source electrode, described active layer is connected with the Part I of described transparent conductive pattern by the via hole of described gate insulation layer.
The beneficial effect of technique scheme of the present invention is as follows:
In the solution of the present invention, thin film transistor (TFT) is no longer tile in the prior art to form, but some is formed in via hole on the insulating layer, forms the spatial structure of vertical separation.Therefore compared to prior art, the area occupied of thin film transistor (TFT) is less, thus shortens the gap on whole array base palte between each pixel region, and then improves aperture opening ratio.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing top gate type array base palte;
Fig. 2 is in array base palte of the present invention, the structural representation of thin film transistor (TFT);
Fig. 3-Fig. 6 is respectively the structural representation of the corresponding different implementation of array base palte of the present invention;
Fig. 7 A-Fig. 7 D is the detailed maps of the method for making of array base palte of the present invention;
Fig. 8 A-Fig. 8 B is the detailed maps of another method for making of array base palte of the present invention.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
For above-mentioned prior art problem, embodiments of the invention provide a kind of array base palte of new construction, effectively can improve aperture opening ratio.Exemplarily property introduction, for the bottom gate type array base palte shown in Fig. 2, this array base palte comprises: underlay substrate 1, the source electrode 6 underlay substrate 1 being formed transparent conductive pattern 6, gate electrode 2, active layer 4 and being connected with described active layer 4;
Wherein, the insulation course 7 comprising via hole is provided with between transparent conductive pattern and source electrode 6;
Transparent conductive pattern 6 comprises the Part I be connected with described active layer by the via hole of insulation course, and described Part I, as drain electrode, with gate electrode 2, active layer 4 and source electrode 5, forms thin-film transistor structure.
In the array base palte of the present embodiment, a part for thin film transistor (TFT) is formed in via hole on the insulating layer, thus forms the spatial structure of vertical separation.Compare known with Fig. 1, the thin film transistor (TFT) area b of the present embodiment is obviously less than thin film transistor (TFT) area a of the prior art, amasss therefore, it is possible to allow pixel electrode occupy more multiaspect, thus improves the aperture opening ratio of array base palte.
The array base-plate structure of the present embodiment is introduced in detail below by several implementation.
Implementation one
In this implementation one, as shown in Figure 3, array base palte comprises:
Underlay substrate 1;
Be formed in the gate electrode 2 on underlay substrate 1, gate insulation layer 3, active layer 4 (active layer can be oxide semiconductor layer), source electrode 5.Source electrode 5 is also formed the passivation layer 7 with via hole, and this passivation layer 7 is insulation course mentioned above.Passivation layer 7 is formed with transparent conductive pattern further, and transparent conductive pattern is made up of two parts, namely as the Part I of drain electrode 6 and the Part II as pixel electrode 8.
As seen in Figure 3, in the array base-plate structure of this implementation one, drain electrode 1 be vertically be formed in passivation layer 7 via hole among, compared with forming with the tiling of prior art, decrease horizontal area occupied.This finally makes whole thin film transistor (TFT) less, thus shortens the spacing between each pixel region, makes the aperture opening ratio of array base palte obtain effective lifting.
Certainly, as a preferred version, on above-mentioned basis, pixel electrode is namely as whole transparent conductive pattern.Namely pixel electrode directly replaces drain electrode to be connected with active layer.Thus, the array base-plate structure of prior art unlike, whole thin-film transistor structure does not need to comprise drain electrode again, can reduce area occupied further.
Implementation two
In this implementation two, as shown in Figure 4, array base palte comprises:
Underlay substrate 1;
The active layer 4 that underlay substrate 1 is formed and source electrode 5.Above source electrode 5, be also provided with the gate insulation layer 3 with via hole, this gate insulation layer 3 is insulation course mentioned above.Gate insulation layer 3 is provided with gate electrode 2 further, and the transparent conductive pattern be made up of drain electrode 6 and pixel electrode 8.
With implementation one unlike, the array base palte shown in implementation two is top gate structure, and the advantage of this structure is: gate electrode 2 and transparent conductive pattern can be arranged with material with layer, and can be formed by patterning processes.
Implementation three
In this implementation two, as shown in Figure 5, array base palte comprises:
Underlay substrate 1;
Be formed in the gate electrode 2 on underlay substrate 1 and transparent conductive pattern.Transparent conductive pattern is made up of two parts, namely as the Part I of drain electrode 6 and the Part II as pixel electrode 8.Gate electrode 2 is formed the gate insulation layer 3 with via hole.Above gate insulation layer 3, form source electrode 5 and active layer 4.Wherein, active layer 4 is connected with drain electrode 6 by the via hole on gate insulation layer 3, and then forms the thin-film transistor structure be made up of source electrode 5, active layer 4 and drain electrode 6.
As seen in Figure 5, in the array base-plate structure of this implementation three, active layer 4 be vertically be formed in gate insulation layer 3 via hole among, compared with forming with the tiling of prior art, more can save area occupied.This finally makes the area of whole thin film transistor (TFT) less, thus shortens the spacing between each pixel region, makes the aperture opening ratio of array base palte obtain effective lifting.
Certainly, as a preferred version, on the basis of above-mentioned implementation three, using pixel electrode as whole transparent conductive pattern, pixel electrode directly replaces drain electrode to be connected with active layer.Thus, pixel region can be allowed further to have more multiaspect amass.
Need to be described, the same with implementation two, the array base palte of implementation three also can adopt top gate structure, no longer repeats herein.
In addition, another embodiment of the present invention also provides a kind of method for making of array base palte, at least be included in the step of insulation course of source electrode underlay substrate being formed with transparent conductive pattern, thin film transistor (TFT) and spaced transparent conductive layer and thin film transistor (TFT), described insulation course has via hole.
Wherein, in the step forming thin film transistor (TFT), gate electrode, source electrode and active layer is only formed;
Part I in the transparent conductive pattern formed is connected with active layer by via hole, and described Part I, as drain electrode, with described gate electrode, active layer and source electrode, forms thin-film transistor structure.
In the manufacture method of the present embodiment, thin film transistor (TFT) is understood in some via hole be formed on insulation course, thus forms the spatial structure of vertical separation.Therefore compared to prior art, the horizontal area occupied of thin film transistor (TFT) is less, thus shortens the gap on whole array base palte between each pixel region, and then improves aperture opening ratio.
Particularly, above-mentioned transparent conductive pattern also comprises the Part II as pixel electrode.Preferably, as shown in Figure 6, the transparent conductive pattern of the present embodiment is all made up of pixel electrode 8, and thin-film transistor structure is without the need for drain electrode.Pixel electrode 8, directly by active layer 4, obtains the data-signal in source electrode 5.And in the method for making of existing array base palte (with reference to figure 1), need to produce drain electrode 6, and pixel electrode 8 is the data-signals obtained by drain electrode 6 in source electrode 5.Contrasted known by both, the thin film transistor (TFT) that the method for making of the present embodiment obtains, because save drain electrode, can effectively reduce horizontal area occupied.
Below in conjunction with several embodiment, method for making of the present invention is described in detail.
Embodiment one
In embodiment one, provide the method for making of the array base palte shown in a kind of Fig. 3, main flow comprises:
As shown in Figure 7 A, underlay substrate forms gate electrode 2 and sweep trace; Wherein, sweep trace is connected with gate electrode 2, obtains in a patterning processes with material etch;
As shown in Figure 7 B, on the underlay substrate 1 being formed with gate electrode 2 and sweep trace, deposition gate insulation layer 3 further;
As seen in figure 7 c, on the underlay substrate 1 depositing gate insulation layer 3, form source electrode 5, data line and active layer 4 further; Unlike the prior art: this step does not form drain electrode; In addition, also need to be described, the formation method of source electrode 5, data line and active layer 4 like the prior art, obtains by a patterning processes or twice patterning processes, no longer repeats herein;
As illustrated in fig. 7d, on the underlay substrate 1 being formed with source electrode 5 and active layer 4, form the passivation layer 7 with via hole further, the position of this via hole is corresponding with active layer 4;
Finally, on the underlay substrate 1 being formed with passivation layer 7, form the transparent conductive pattern be made up of drain electrode 6 and pixel electrode 8 two parts further, finally obtain array base palte as shown in Figure 3.
In the method for making of embodiment one, can using pixel electrode 8 as whole transparent conductive pattern, pixel electrode 8 is directly connected with active layer 4 by the via hole of regulation, thus increases aperture opening ratio.
Embodiment two
In embodiment two, provide the method for making of the array base palte shown in a kind of Fig. 5, main flow comprises:
As shown in Figure 8 A, on underlay substrate 1, form gate electrode 2 and transparent conductive pattern 8; Wherein, preferably, in this step, gate electrode 2 and transparent conductive pattern 8 can adopt same material etch to form, and are making with in a patterning processes;
As shown in Figure 8 B, on the underlay substrate 1 being formed with gate electrode 2 and transparent conductive pattern 8, form the gate insulation layer 3 with via hole further, the position of this via hole is corresponding with transparent conductive pattern 8;
Finally, on the underlay substrate 1 being formed with gate insulation layer 3, be formed with active layer 4 and source electrode 5 further, obtain array base-plate structure as shown in Figure 5; Wherein, preferably, in this step, active layer 4 and source electrode 5 can make at a patterning processes and obtain.
Be more than the Making programme of embodiment two, but as a kind of feasible implementation, protective seam together with can also depositing further with above source electrode 5 at active layer 4, for the protection of source electrode 5 and active layer 4.
Visible, the method for making of embodiment two only needs twice composition skill, can not only improve aperture opening ratio, can also reduce Production Time and cost of manufacture, therefore have very high practical value.
In addition, another embodiment of the present invention also provides a kind of display device comprising above-mentioned array base palte.Described display device can be the products such as mobile phone, PAD, TV, compared to existing technology, have higher aperture opening ratio, and then display effect is finer and smoother.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. an array base palte, comprises underlay substrate, the source electrode described underlay substrate being formed with transparent conductive pattern, gate electrode, active layer and being connected with described active layer; It is characterized in that,
The insulation course comprising via hole is provided with between described transparent conductive pattern and described source electrode;
Described transparent conductive pattern comprises the Part I be connected with described active layer by described via hole, and described Part I, as drain electrode, with described gate electrode, active layer and source electrode, forms thin-film transistor structure.
2. array base palte according to claim 1, is characterized in that,
Described transparent conductive pattern also comprises the Part II as pixel electrode.
3. array base palte according to claim 1, is characterized in that,
Described insulation course is passivation layer, and described passivation layer is positioned at above described source electrode;
Described underlay substrate is also formed with gate insulation layer, and described gate insulation layer is arranged between described gate electrode and described source electrode.
4. array base palte according to claim 1, is characterized in that,
Described insulation course is gate insulation layer, and described gate insulation layer is arranged between described gate electrode and described source electrode;
Described transparent conductive pattern and described gate electrode are arranged with layer.
5. array base palte according to claim 1, is characterized in that,
Described active layer is oxide semiconductor layer.
6. a display device, is characterized in that, comprises the array base palte as described in any one of claim 1-5.
7. the method for making of an array base palte, at least be included in the step of the insulation course of source electrode underlay substrate being formed with transparency conducting layer and described thin film transistor (TFT) described in transparent conductive pattern, thin film transistor (TFT) and interval, described insulation course has via hole, it is characterized in that:
In the step forming thin film transistor (TFT), only form gate electrode, source electrode and active layer;
Form the described transparent conductive pattern including the Part I be connected with described active layer by described via hole, described Part I, as drain electrode, with described gate electrode, active layer and source electrode, forms thin-film transistor structure.
8. method for making according to claim 7, is characterized in that,
Described transparent conductive pattern also comprises the Part II as pixel electrode.
9. method for making according to claim 8, is characterized in that,
Described insulation course is passivation layer, and described method for making specifically comprises:
Underlay substrate is formed gate electrode and sweep trace;
On the underlay substrate being formed with gate electrode and sweep trace, form gate insulation layer;
On the underlay substrate being formed with gate insulation layer, the active layer forming source electrode, data line and be connected with this source electrode;
On the underlay substrate being formed with source electrode, data line and active layer, form the passivation layer with via hole;
On the underlay substrate being formed with passivation layer, form transparent conductive pattern, the Part I of described transparent conductive pattern, by the via hole of described passivation layer, is connected with described active layer.
10. method for making according to claim 8, is characterized in that,
Described insulation course is gate insulation layer, and described method for making specifically comprises:
Underlay substrate is formed gate electrode, sweep trace and transparent conductive pattern;
On the underlay substrate being formed with gate electrode, sweep trace and transparent conductive pattern, form the gate insulation layer with via hole;
On the underlay substrate being formed with gate insulation layer, the active layer forming source electrode, data line and be connected with this source electrode, described active layer is connected with the Part I of described transparent conductive pattern by the via hole of described gate insulation layer.
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| CN104749848B (en) | 2018-11-02 |
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